CN103324559A - Speed testing method for data transmitting from PCIExpress master to equipment based on FPGA (field programmable gate array) - Google Patents
Speed testing method for data transmitting from PCIExpress master to equipment based on FPGA (field programmable gate array) Download PDFInfo
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- CN103324559A CN103324559A CN2013102626890A CN201310262689A CN103324559A CN 103324559 A CN103324559 A CN 103324559A CN 2013102626890 A CN2013102626890 A CN 2013102626890A CN 201310262689 A CN201310262689 A CN 201310262689A CN 103324559 A CN103324559 A CN 103324559A
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Abstract
The invention discloses a speed testing method for data transmitting from a PCIExpress master to equipment based on FPGA (field programmable gate array). The speed testing method includes S1, modifying a transmitting layer of the FPGA, and adding speed testing codes for testing the speed of data transmitted between the master and the equipment; S2, arranging a read equipment performance counter; S3, allowing the testing codes to read a counter value of the read equipment performance counter, and calculating transmitting speed: S=V/(C/H=V*H/C. S represents speed for equipment reading data, C represents the counter value of the equipment performance counter, H represents frequency of a clock of the equipment, and V represents the number of bytes of the data read by the device from a driving memory. By the aid of the speed testing method, the counter value can be read after data is read by a driving program arrange equipment every time, the transmission speed can be calculated immediately, calculation is free of affection by the master and other external factors, testing objectivity is good, and testing results are accurate.
Description
Technical field
The present invention relates to a kind of PCI Express main frame based on FPGA to the data rate method of testing of equipment, belong to field of computer technology.
Background technology
FPGA(Field-Programmable Gate Array), it is field programmable gate array, occur as a kind of semi-custom circuit in special IC (ASIC) field, both solved the deficiency of custom circuit, overcome again the limited shortcoming of original programming device gate circuit number.With traditional logic circuit and gate array (such as PAL, GAL and CPLD device) compare, FPGA has different structures, FPGA utilizes small-sized look-up table, and (16 * 1RAM) realize combinational logic, each look-up table is connected to the input end of a d type flip flop, trigger drives other logical circuits again or drives I/O, consisted of thus the basic logic unit module that not only can realize combination logic function but also can realize the sequential logic function, these intermodules utilize metal connecting line to be connected to each other or are connected to the I/O module.The logic of FPGA realizes by loading programming data to inner static storage cell, being stored in value in the memory cell has determined between the logic function of logical block and each module or the connecting mode between module and I/O, and final decision the achieved function of FPGA, FPGA allows unlimited programming.
Utilize FPGA to realize that the maximum reason of PCI Express is its reconfigurability.To this new technology of PCI Express, specification is in the stage of continuous variation.When specification changes, by reconfigurability can be corresponding change, the upgrading that software programming realizes version is carried out in former design.Adopt the built-in high-speed transceiver module of some FPGA and programmable structure, Virtex series such as Xilinx, its built-in high-speed transceiver (Rocket IOTMGTP transceiver) can be supported the 2.5Gbps speed that PCI Express agreement is required, the 8B/10B encoding and decoding can be extracted clock reliably from data, realize clock recovery, cost and difficulty be can reduce, design difficulty and cycle reduced.FPGA supplier tests the module among the FPGA and IP kernel for PCI Express specially, has guaranteed the compatibility of product.
The concrete technology that does not have in the market the speed of swap data between the test PCI Express equipment of standard and the host driver, there is following problem in some known measuring technologies at present:
1, speed is not high, and the exchanges data speed of host driver and equipment room only can reach 150MBytes/s;
2, the Test Host driver is different with the standard of exchanged between equipment speed, does not have at present objective method of testing.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of test speed fast, each driver arranges the value that the equipment read data later on just can read-out counter, can calculate at once the speed of transmission, be not subjected to other external actions such as main frame during the counting, the test objectivity is good, and test result is accurately based on the PCI Express main frame of the FPGA data rate method of testing to equipment.
The objective of the invention is to be achieved through the following technical solutions: based on the PCI Express main frame of the FPGA data rate method of testing to equipment, it may further comprise the steps:
S1: the transport layer to FPGA is made amendment, and adds therein the code that tests the speed of data rate between Test Host and the equipment;
S2: arrange one and read the equipment performance counter;
S3: the described code that tests the speed reads the described count value of reading the equipment performance counter, and by the following method computation host to the data rate of equipment:
S=V/ (C/H)=V*H/C, wherein, S be the speed of equipment read data be main frame to the data rate of equipment, unit is Mbyte/s, C is the count value of equipment performance counter; H is the frequency of the clock of equipment, and unit is MHz; V is equipment from the byte number of the data that drive memory read back, and unit is byte.
The described equipment performance counter of reading adopts hardware language to describe program design.
The described width of reading the equipment performance counter is 32bit.
Read the memory headroom that operates in of equipment performance counter, driver can only be read and can not write.
Read the equipment performance counter to add that 1 operation occurs in be the rising edge of equipment clock signal.
Reading the enabled condition that the equipment performance counter adds 1 operation is that equipment is under the normal running conditions and driver arranges equipment requirement equipment from the moment of host memory read data.
Read end condition that the equipment performance counter adds 1 operation and be equipment and be under the normal running conditions and equipment runs through moment of total data from host memory according to the requirement of driver, read the equipment performance counter and no longer count this moment, keeps count value constant.
The zero clearing condition of reading the equipment performance counter can only be equipment whole when sending and receiving state machine and resetting, and count value all can remain unchanged in other situations.
The invention has the beneficial effects as follows:
1, test speed is fast, and each driver arranges the value that the equipment read data later on just can read-out counter, can calculate at once the speed of transmission;
2, be not subjected to other external actions such as main frame during the counting, the test objectivity is good, and test result is accurate;
3, only need to be at counter of equipment design just, simple to operate, expense is little, does not take the resource of system, does not affect data transmission efficiency.
Embodiment
Further specify technical scheme of the present invention below in conjunction with specific embodiment, but the content that the present invention protects is not limited to the following stated.
Based on the PCI Express main frame of the FPGA data rate method of testing to equipment, it may further comprise the steps:
S1: the transport layer to FPGA is made amendment, and adds therein the code that tests the speed of data rate between Test Host and the equipment;
S2: arrange one and read the equipment performance counter;
S3: the described code that tests the speed reads the described count value of reading the equipment performance counter, and by the following method computation host to the data rate of equipment:
S=V/ (C/H)=V*H/C, wherein, S be the speed of equipment read data be main frame to the data rate of equipment, unit is Mbyte/s, C is the count value of equipment performance counter; H is the frequency of the clock of equipment, and unit is MHz; V is equipment from the byte number of the data that drive memory read back, and unit is byte.
The described equipment performance counter of reading adopts hardware language to describe program design, and the width of counter is 32bit.
The described memory headroom that operates in of reading the equipment performance counter, driver can only be read and can not write.
Read the equipment performance counter to add that 1 operation occurs in be the rising edge of equipment clock signal.
Reading the enabled condition that the equipment performance counter adds 1 operation is that equipment is under the normal running conditions and driver arranges equipment requirement equipment from the moment of host memory read data.
Read end condition that the equipment performance counter adds 1 operation and be equipment and be under the normal running conditions and equipment runs through moment of total data from host memory according to the requirement of driver, read the equipment performance counter and no longer count this moment, keeps count value constant.
The zero clearing condition of reading the equipment performance counter can only be equipment whole when sending and receiving state machine and resetting, and count value all can remain unchanged in other situations.
Claims (8)
1. based on the PCI Express main frame of the FPGA data rate method of testing to equipment, it is characterized in that: it may further comprise the steps:
S1: the transport layer to FPGA is made amendment, and adds therein the code that tests the speed of data rate between Test Host and the equipment;
S2: arrange one and read the equipment performance counter;
S3: the described code that tests the speed reads the described count value of reading the equipment performance counter, and by the following method computation host to the data rate of equipment:
S=V/ (C/H)=V*H/C, wherein, S be the speed of equipment read data be main frame to the data rate of equipment, unit is Mbyte/s, C is the count value of equipment performance counter; H is the frequency of the clock of equipment, and unit is MHz; V is equipment from the byte number of the data that drive memory read back, and unit is byte.
2. the PCI Express main frame based on FPGA according to claim 1 is characterized in that to the data rate method of testing of equipment: the described equipment performance counter of reading adopts hardware language to describe program design.
3. the PCI Express main frame based on FPGA according to claim 1 is to the data rate method of testing of equipment, and it is characterized in that: the described width of reading the equipment performance counter is 32bit.
4. the PCI Express main frame based on FPGA according to claim 1 is to the data rate method of testing of equipment, and it is characterized in that: the described memory headroom that operates in of reading the equipment performance counter, driver can only be read and can not write.
5. the PCI Express main frame based on FPGA according to claim 1 is characterized in that to the data rate method of testing of equipment: described read the equipment performance counter to add that 1 operation occurs in be the rising edge of equipment clock signal.
6. the PCI Express main frame based on FPGA according to claim 1 is characterized in that to the data rate method of testing of equipment: described to read the enabled condition that the equipment performance counter adds 1 operation be that equipment is under the normal running conditions and driver arranges equipment requirement equipment from the moment of host memory read data.
7. the PCI Express main frame based on FPGA according to claim 1 is to the data rate method of testing of equipment, it is characterized in that: described to read end condition that the equipment performance counter adds 1 operation be that equipment is under the normal running conditions and equipment runs through moment of total data from host memory according to the requirement of driver, read the equipment performance counter and no longer count this moment, keeps count value constant.
8. the PCI Express main frame based on FPGA according to claim 1 is to the data rate method of testing of equipment, it is characterized in that: the described zero clearing condition of reading the equipment performance counter can only be equipment whole when sending and receiving state machine and resetting, and count value all can remain unchanged in other situations.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013102626890A CN103324559A (en) | 2013-06-27 | 2013-06-27 | Speed testing method for data transmitting from PCIExpress master to equipment based on FPGA (field programmable gate array) |
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| CN2013102626890A CN103324559A (en) | 2013-06-27 | 2013-06-27 | Speed testing method for data transmitting from PCIExpress master to equipment based on FPGA (field programmable gate array) |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120092040A1 (en) * | 2007-04-19 | 2012-04-19 | Microsoft Corporation | Field-Programmable Gate Array Based Accelerator System |
| CN102521184A (en) * | 2011-12-20 | 2012-06-27 | 北京遥测技术研究所 | Method for achieving data high-speed transmission on component interconnect (PCI) bus |
| WO2012138111A2 (en) * | 2011-04-01 | 2012-10-11 | Taejin Info Tech Co., Ltd. | Dynamic random access memory for a semiconductor storage device-based system |
| CN103176068A (en) * | 2011-12-23 | 2013-06-26 | 中国人民解放军海军航空仪器计量站 | Bus-based test module |
-
2013
- 2013-06-27 CN CN2013102626890A patent/CN103324559A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120092040A1 (en) * | 2007-04-19 | 2012-04-19 | Microsoft Corporation | Field-Programmable Gate Array Based Accelerator System |
| WO2012138111A2 (en) * | 2011-04-01 | 2012-10-11 | Taejin Info Tech Co., Ltd. | Dynamic random access memory for a semiconductor storage device-based system |
| CN102521184A (en) * | 2011-12-20 | 2012-06-27 | 北京遥测技术研究所 | Method for achieving data high-speed transmission on component interconnect (PCI) bus |
| CN103176068A (en) * | 2011-12-23 | 2013-06-26 | 中国人民解放军海军航空仪器计量站 | Bus-based test module |
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