CN103324117B - The microprocessor of blood analyser/field programmable gate array two stage control system - Google Patents
The microprocessor of blood analyser/field programmable gate array two stage control system Download PDFInfo
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Abstract
The microprocessor of a kind of blood analyser/field programmable gate array two stage control system, is mainly made up of ARM microprocessor+on-site programmable gate array FPGA.System makes full use of the respective advantage of ARM Yu FPGA, the management and control achieving instrument separates, whole instrument, with ARM as core, is managed as a whole by i.e. first order control system, finishing man-machine interaction, analysis result show, image procossing, report printing, the management work such as data storage；Second level control system is with FPGA as core, give full play to that FPGA real-time is good, aboundresources, processing speed fast, can concurrent working and programmable advantage, complete analysis action and data sampling and processing, storage, malfunction monitoring etc. and control function, and achieve the flexible design of electronic system；Connected by SPI communication module between two stage control system.Each performs its own functions for two-stage system, collaborative work, improves the real-time of system, motility and reliability.
Description
Technical field
The invention belongs to Clinical Laboratory manufacturing field of equipment, relate to blood analyser.
Background technology
At present, the control system of domestic main flow automatic blood analyzer, mostly sampling use the system structure of ARM mainboard+driving plate.This system structure, ARM microprocessor should control function by driving plate to complete analysis action and the malfunction monitoring etc. such as motor drivings, electromagnetic valve ON/OFF, again data acquisition, process, show, store and man-machine interaction etc. manages work.Owing to embedded OS easily occurs the phenomenons such as deadlock, thread deadlock in running, not only have influence on image procossing, data show, the management work such as man-machine interaction, the faults such as serious appearance motor desynchronizing, electromagnetic valve switch time delay, directly influence the collection of signal and completing of Instrumental Analysis action.It addition, ARM mainboard is coupled with driving plate by data wire, address wire and control line, owing on line is more, therefore on line poor reliability, easily by external interference, directly influence the reliability of system.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, devise the two stage control system being made up of ARM microprocessor (management level)+on-site programmable gate array FPGA (Basic automation level).System makes full use of the respective advantage of ARM Yu FPGA, it is achieved that the management and control of instrument separates, i.e. first order control system, with ARM as core, completes that analysis result show, image procossing, report printing, data storage etc. manage work；Second level control system, with FPGA as core, completes analysis action and data sampling and processing, storage, malfunction monitoring etc. and controls function；Information exchange between two stage control system is realized by SPI communication interface.The control functions such as two stage control system is few due on line, the analysis action of instrument, by FPGA complete independently, therefore improve reliability and the real-time of system.
Technical solutions according to the invention are: devise the two stage control system being made up of ARM+FPGA and realize the administration by different levels to blood analyser and control.It is attached by SPI communication interface between two-stage system.
The first order, with ARM as hardware platform, is set up the management environment with embedded Windows CE 5.0 as operating system, is completed the overall management to whole instrument, it is achieved that visualize man-machine function of exchange and the management to blood analyser various functions Yu data sheet；Under the mode that management and control separates, ARM primary processor no longer carries out the work such as numerous and diverse analysis action control, data acquisition, data process, it is absorbed in the overall management to whole system, the functions such as finishing man-machine interaction, analysis result show, image procossing, report printing, data storage, external communication, make system run more stable, reliable.
The second level is with FPGA as core, give full play to that FPGA real-time is good, aboundresources, processing speed fast, can concurrent working and programmable advantage, ON/OFF and multichannel data parallel high-speed Real-time Collection while achieving the parallel drive of multichannel motor, multipath electrovalve, process and store, complete the monitoring to system hardware state simultaneously, improve the real-time of system；Utilize the programmable feature of FPGA, the flexible design of electronic system can be realized, i.e. under different requirements, can be reset by FPGA internal circuit configuration and realize difference in functionality, thus greatly improve the motility of Circuits System hardware capability, make single circuit system have the function of many different circuit structures, meet different demands, therefore improve the motility of system.
Information exchange between two stage control system is realized by SPI communication interface.The control functions such as two stage control system is few due on line, the analysis action of instrument, by FPGA complete independently, therefore improve reliability and the real-time of system.
Described first order control system is with microprocessor as core, also include human-computer interaction interface module, LPT external printer module, outside SD card memory module, the USB2.0 interface module of standard, standard RG45 Network Interface Module, standard VGA interface module, standard RS232 interface module, SPI communication module and power supply interface module, described module is connected with ARM respectively.
Described second level control system is with field programmable gate array as core, also including that SPI communication module, power supply interface module, motor drive module, electromagnetic valve ON/OFF module, SDRAM memory module, I/O expand module, Power Entry Module, digital output modul module, state detection module, signal acquisition module, described module is connected with FPGA respectively.
It is connected by SPI communication module between microprocessor with field programmable gate array.
The work process of the present invention is: during instrument work, user can carry out various operation by first order control system human-computer interaction interface to instrument, including historical results review, historical report singles print, analyzes Action Selection, various auxiliary movement selections etc..When user selects Instrumental Analysis motion action, by ARM by SPI communication interface to FPGA transmitting control commands.FPGA resolves after receiving the order that ARM sends, according to command context, control blood analyser and complete corresponding actions, hemocyte signal is acquired simultaneously, the digital signal collected is temporarily stored into SDRAM memory module after treatment, the analysis result kept in SDRAM is uploaded to ARM by SPI communication module after terminating by signals collecting, it is managed collectively by ARM, after analysis action completes, release symbol is uploaded to ARM by SPI by FPGA, represent that this action completes, lower set can be carried out.After ARM receives the data that FPGA uploads, shown on liquid crystal display screen by human-computer interaction interface or USB interface module, result is stored in the data base of outside SD memory module simultaneously, and prints analysis report.
The specific works flow process of two stage control system is.
First order control system workflow.
S1, system initialization.After system electrification, embedded OS and user's setup parameter are initialized by instrument.
S2, entrance human-computer interaction interface.User can carry out various operation by human-computer interaction interface to instrument, including selecting the operation of various auxiliary movement, the operation of selection analysis sampling action, system management operation.
If S3 user's selection analysis action, then jump to step S4；If user selects auxiliary movement, then jump to step S8；If with selecting system management operation, then jumping to step S9.
S4, ARM send analysis action directive by SPI communication module to FPGA.
S5, ARM receive, by SPI communication module, the sampled data that FPGA uploads.
After S6, ARM have received the data that FPGA uploads, by human-computer interaction interface or USB interface, the data received are shown in LCDs, result are stored in the data base of outside SD card memory module simultaneously and are analyzed report printing by LPT external printer module.
After S7, release, jump to step S2 and carry out next operation for user.
S8, ARM send auxiliary movement control command by SPI communication module to FPGA.Jump to step S7 and wait release.
System is managed by S9, user, look back including historical results, user's setup parameter is revised, report prints, carried out data transmission by RS232 and carry out communication operation by network interface or USB interface with the external world, and this operation jumps to step S2 and supplies user to carry out next operation after terminating.
Second level control system workflow.
After S1, system electrification, user's setup parameter is initialized.
S2, system wait, at SPI communication module, the control command that ARM sends, and after receiving order resolve order.
If the order that S3 ARM sends is for analyzing action command, then jump to step S4；If the order that ARM sends is auxiliary movement order, then jump to step S8.
S4, it is analyzed action by motor drive module, electromagnetic valve ON/OFF control module, and by state detection module, system mode is monitored.
S5, carrying out data acquisition by signal acquisition module, the data collected are temporarily stored into SDRAM memory module after treatment.
The data stored in SDRAM are uploaded to ARM by SPI communication module after terminating by S6, sampling.
By SPI communication module to ARM sending action end mark after S7, release, jump to the wait of step S2 and order next time.
S8, completed corresponding auxiliary movement by motor drive module, electromagnetic valve ON/OFF control module, and jump to step S7 and wait release.
The invention has the beneficial effects as follows, make full use of the respective advantage of ARM Yu FPGA, it is achieved that the management and control of instrument separates.With ARM as hardware platform, by setting up the management environment with embedded Windows CE 5.0 as operating system, complete the overall management to whole instrument, it is achieved that visualize man-machine function of exchange and the management to blood analyser various functions Yu data sheet；Utilize that FPGA real-time is good, aboundresources, processing speed fast, can concurrent working and programmable advantage, it is achieved that the real-time of system controls and multidiameter delay high-speed data acquisition and process and the flexible design of electronic system.And only carrying out information exchange, simple in construction by a SPI communication interface between two-stage system, on line is few, and therefore capacity of resisting disturbance is strong, and communication is reliable.Whole analyser is managed as a whole by first order control system, and Each performs its own functions for two-stage system, collaborative work, improves the speed of service of instrument, optimizes the performance of instrument, enhances the real-time of system, motility and reliability simultaneously.
Accompanying drawing explanation
Accompanying drawing 1 is the two stage control system structural representation of the present invention.
Accompanying drawing 2 is ARM first order control system functional interface schematic diagram.
Accompanying drawing 3 is FPGA second level control system high-level schematic functional block diagram.
Accompanying drawing 4 is the SPI communication module connection diagram between two stage control system of the present invention.
Accompanying drawing 5 is the power interface connection diagram between two stage control system of the present invention.
Accompanying drawing 6 is signal acquisition circuit figure of the present invention.
Accompanying drawing 7 is state detection circuit figure of the present invention.
Accompanying drawing 8 is digital output modul circuit diagram of the present invention.
Accompanying drawing 9 is motor-drive circuit figure of the present invention.
Accompanying drawing 10 is solenoid valve control circuit figure of the present invention.
Accompanying drawing 11 is SDRAM memory module circuit diagram of the present invention.
Accompanying drawing 12 is power input interface circuit diagram of the present invention.
Accompanying drawing 13 is first order control system workflow diagram of the present invention.
Accompanying drawing 14 is the second level of the present invention control system workflow diagram.
Detailed description of the invention
Embodiment.
The present invention will be described further by following example in conjunction with accompanying drawing.
Accompanying drawing 1 is two stage control system structural representation of the present invention.Mainly it is made up of first order control system, second level control system and SPI communication.Wherein first order control system is based on ARM, and second level control system is based on FPGA, and first order control system is attached with SPI communication with second level control system, so that two stage control system becomes an entirety.The operating system of first order control system is embedded Windows CE 5.0.
Accompanying drawing 2 is ARM first order control system functional interface schematic diagram of the present invention.Mainly it is made up of ARM microprocessor, human-computer interaction interface module, outside SD card memory module, LPT external printer module, USB interface module, SPI communication module, power supply interface module, RS232 interface module, USB2.0 interface module, RG45 Network Interface Module.Wherein module is driven to realize man-machine dialog interface with the built-in LCD of ARM；Module is driven to realize access and the management of data with the storage of ARM built-in SD card；Printer driver is realized with the external printer LPT interface of standard or USB 2.0 interface of standard；The communication with first order control system is realized with SPI interface；System power supply is realized with power supply interface module；Meanwhile, system provides 1 standard VGA interface, 4 standard USB 2.0 interfaces, 3 standard RS232 interfaces, 1 LPT interface, 1 RG45 network interface；Wherein ARM primary processor is SAMSUNG S3C2442B；LCD module is LQ104V1DG52；SD card is Kingston 2G, 4G, 8G or 16G；RS232 baud rate is 115200, stops position 1bit, data bit 8 bits, no parity check position；Power Interface Standard is as shown in Figure 5；SPI interface standard is as shown in Figure 4.Remaining standard interface all can connect the common apparatus of correspondence.
Accompanying drawing 3 is the FPGA second level of the present invention control system functional interface schematic diagram.Mainly it is made up of FPGA, power interface, SPI communication module, signal acquisition module, state detection module, digital output modul module, Power Entry Module, I/O expansion module, motor drive module, electromagnetic valve ON/OFF module, SDRAM memory module.It is main composition second level control system with FPGA.The communication with first order control system is realized with SPI interface；Realized to the power supply of first order control system by power interface；Control A/D converter by SPI and realize signals collecting, 8 road signals can be carried out parallel acquisition and process simultaneously；Realized the state-detection of whole system by SPI control A/D converter and MUX, 8 kinds of different status signals of system can be detected；5 LED light-emitting diode switchs controls can be realized by digital output modul and a buzzer warning is controlled；No. 4 motor parallel drive and controls are realized by motor drive module；The 24 parallel ON/OFF of way solenoid valve and controls are realized by electromagnetic valve ON/OFF module；2 road SDRAM parallel control are realized by SDRAM control module；Power supply input directly connects external power source, it is achieved whole system is powered；I/O expands interface and expands use as later stage system.EP2C20F484C8 during wherein FPGA is altera corp's CycloneII series；The interface standard of SPI interface and second level control system is as shown in Figure 4；Power Interface Standard is as shown in Figure 5；SPI realizes A/D control and signal acquisition circuit figure as shown in Figure 6；SPI controls A/D and multiplexer realizes state detection circuit figure as shown in Figure 7；Digital output modul circuit is as shown in Figure 8；Motor driving controling circuit is as shown in Figure 9；Solenoid valve control circuit is as shown in Figure 10；SDRAM control module circuit diagram is as shown in figure 11；Power input interface is as shown in figure 12.
Accompanying drawing 4 is the SPI communication interface schematic diagram of two stage control system of the present invention.Mainly it is made up of FPGA SPI interface and ARM SPI interface.SPI communication interface achieves the information exchange between two stage control system and data transmission, and two stage control system is connected as an entirety.Wherein CS, CLK, MISO, MOSI of first order control system is connected with second level control system CS, CLK, MOSI, MISO end respectively.
Accompanying drawing 5 is that the two stage control system FPGA second level of the present invention control system supplies electrical schematic to ARM first order control system.Mainly it is made up of second level control system power interface and first order control system power interface.The power supply being achieved first order control system by power interface is supplied, and makes first order control system normally work.Power Interface Standard is: 1 foot is+5VDC, 2 feet are+12VDC, 3 feet are-12VDC, 4 feet are GND；Wherein the 1 of second level control system power interface, 2,3,4 feet are connected with 1,2,3,4 feet of first order control system power interface respectively.
Accompanying drawing 6 is signal acquisition module circuit diagram of the present invention.Mainly it is made up of DAD5, RAD5, UAD5.Wherein signal input is signal input part to be collected, and signal input requirements is 0-5VDC；DAD5 is pressure limiting diode, and voltage limiting value is 5VDC, and to protect UAD5, DAD5 one end is connected with the common port of signal input part and RAD5, other end ground connection；RAD5 is build-out resistor, and to be stably input to the signal of UAD5, RAD5 one end is connected with signal input part and DAD5 common port, 3 feet of another termination UAD5；UAD5 is A/D converter, it is achieved the conversion of analogue signal to digital signal, and 1 foot of UAD5 connects+5V power supply, 2 foot ground connection, and 3 feet connect RAD5 mono-foot, and 4,5,6 feet are connected with AD_CLK5, AD_DATA5, AD_CS5 of FPGA respectively；CAD9 Yu CAD10 realizes+5V power filter jointly, provides stable working power for UAD5.Wherein signal input requirements is 0-5VDC signal；DAD5 is 5V crest stabilivolt, and model is LL60；RAD5 resistance is 100；UAD5 model is ADS7883；CAD9 is 100nF；CAD10 is 10uF.
Accompanying drawing 7 is state detection module circuit diagram of the present invention.Mainly it is made up of U9, DAD3, RAD3, UAD3.nullWherein U9 is multichannel quick closing valve selector，Realize the signal switching of different conditions detection，1 foot of U9 is connected with the PRINTER of printer test side，2 feet are connected with temperature sensor outfan TEMP，3 feet and RAD3、The common port of DAD3 is connected，The outfan VOL1 that 4 feet detect with aperture voltage 1 is connected，The outfan VOL2 that 5 feet detect with aperture voltage 2 is connected，6、7、8 foot ground connection，9、10、11 feet respectively with the A_CD4051 of FPGA、B_CD4051、C_CD4051 is connected，12 feet are connected with the outfan PRESS of pressure transducer，13 feet are connected with cleanout fluid testing circuit outfan DET，14 feet are connected with diluent testing circuit outfan DIL，15 feet are connected with the outfan LYSE of hemolysin testing circuit，16 feet connect+5V power supply.DAD3 is pressure limiting diode, and voltage limiting value is 5VDC, and to protect UAD3, DAD3 one end is connected with 3 feet of U9 and the common port of RAD3, other end ground connection；RAD3 is build-out resistor, and to be stably input to the signal of UAD3, RAD3 one end is connected with 3 feet and the DAD3 common port of U9,3 feet of another termination UAD3；UAD3 is A/D converter, it is achieved the conversion of analogue signal to digital signal, and 1 foot of UAD3 connects+5V power supply, 2 foot ground connection, and 3 feet connect RAD3 mono-foot, and 4,5,6 feet are connected with AD_CLK3, AD_DATA3, AD_CS3 of FPGA respectively；CAD5 Yu CAD6 realizes+5V power filter jointly, provides stable working power for UAD3.Wherein U9 model is CD4051；DAD3 is 5V crest stabilivolt, and model is LL60；RAD3 resistance is 100；UAD3 model is ADS7883；CAD5 is 100nF；CAD6 is 10uF.
Accompanying drawing 8 is digital output modul module circuit diagram of the present invention.Mainly it is made up of U27, U50, J6.Wherein U27 is level latch, improve the driving force of FPGA output signal, the 1 of U27,3,4,5,6,7 feet connect respectively FPGA LED_Yellow0, LED_Red0, LED_Green0, LED_Green1, LED_Yellow1, Buzzer0 end be connected, 2,8 foot ground connection, 9 feet are connected with 2 feet of U50,10 feet are connected with 1 foot of U50, and 11,12,13,14,16 feet are connected with 2,4,6,8,10 feet of J6 respectively；U50 is buzzer interface；J6 is LED light-emitting diodes interface tube, the 1 of J6,3,5,7,9 feet are connected with+24V power supply by R78, R79, R80, R81, R82 respectively.R85 is impedance matching resistor, and its two ends are connected with 1,2 feet of U50 respectively；R78, R79, R80, R81, R82 are current-limiting resistance.Wherein U27 model is ULN2003D；U50 is 2Pin buzzer interface；J6 is 10Pin LED light-emitting diodes interface tube；R85 resistance is 100K；R78, R79, R80, R81, R82 resistance is 4.7K.
Accompanying drawing 9 is motor drive module circuit diagram of the present invention.Mainly it is made up of U8 with J19.nullWherein U8 is motor drive ic，Realize motor to drive，The 33 of U8、45、47 feet respectively with the DIRECTION of FPGA、CLK、ENABLE end is connected，35、42、48 pass through R32 respectively、R33、R34 with 3.3V power supply is connected，30、31 feet are connected with+5V power supply，26、26、55、56 feet are connected with+24V_MOTOR power supply，6、7 feet are connected with 2 feet of J19，10、11 feet are connected with 3 feet of J19，19、20 feet are connected with 4 feet of J19，61、62 feet are connected with 1 foot of J19，2、4 feet pass through R44 ground connection，13、14 feet pass through R43 ground connection，16、35、38、39、43、50、51、64 foot ground connection，53 feet pass through C24 ground connection；J19 is motor wire base；R32, R33, R34 are current-limiting resistance；C16, C17 collectively constitute filter circuit, filter the interference of+5V；C18, C19 collectively constitute filter circuit and filter the interference signal of+24V_MOTOR；R43, R44 are current-limiting resistance.Wherein U8 is TB6560AFG；R32, R33, R34 resistance is 10K；C16, C19 are the electric capacity of 10uF；C17, C18 are the electric capacity of 100nF；C24 is the electric capacity of 300PF；R43, R44 resistance is 0.33 Ω.
Accompanying drawing 10 is solenoid valve control module circuit of the present invention.Mainly it is made up of R15, Q1, J1.Wherein R15 is current-limiting resistance, and one end is connected with the control end of the Valve1 of FPGA, and the other end is connected with 2 feet of Q1；Q1 is CMOS audion, the 1 foot ground connection of Q1, and 2 feet are connected with R15 one end, and 3 feet are connected with 1 foot of J1；J1 is electromagnetic valve wire base, and 1 foot of J1 is connected with 3 feet of Q1, and 2 feet are connected with+24V_VALVE power supply.Wherein R15 resistance is 180 Ω；Q1 model is 2N5551.
Accompanying drawing 11 is the SDRAM memory module circuit diagram of the present invention.Mainly it is made up of US1, thus realizes storage and the reading of data.nullThe 1 of US1、14、27、3、9、43、49 feet are connected with 3.3V power supply，16、17、18、19 respectively at the SDRAM_WE of FPGA、SDRAM_CAS、SDRAM_RAS、SDRAM_CE is connected，20、21 feet are respectively at the SDRAM_BA0 of FPGA、SDRAM_BA1 is connected，23、24、25、26、27、28、29、30、31、32、33、34、35、36 feet are respectively at the SDRAM_A0 of FPGA、SDRAM_A1、SDRAM_A2、SDRAM_A3、SDRAM_A4、SDRAM_A5、SDRAM_A6、SDRAM_A7、SDRAM_A8、SDRAM_A9、SDRAM_A10、SDRAM_A11、SDRAM_A12 is connected，2、4、5、7、10、11、13、42、44、45、47、48、50、51、53 feet are respectively at the SDRAM_DQ0 of FPGA、SDRAM_DQ1、SDRAM_DQ2、SDRAM_DQ3、SDRAM_DQ4、SDRAM_DQ5、SDRAM_DQ6、SDRAM_DQ7、SDRAM_DQ8、SDRAM_DQ9、SDRAM_DQ10、SDRAM_DQ11、SDRAM_DQ12、SDRAM_DQ13、SDRAM_DQ14、SDRAM_DQ15 is connected，15、39 feet are respectively at the SDRAM_DQM0 of FPGA、SDRAM_DQM1 is connected，28、41、54、6、12、46、52 foot ground connection，37、38 feet respectively with the SDRAM_CKE of FPGA、SDRAM_CLK is connected.
Accompanying drawing 12 is the power supply interface module circuit diagram of the present invention.J1-1 connects external input power, and external input power is+12VDC.
During instrument work, order is sent to FPGA by ARM, FPGA resolves after receiving the order that ARM sends, according to command context, control blood analyser executor and complete corresponding actions, cell signal etc. is acquired simultaneously, gather signal and be temporarily stored into SDRAM module after treatment, the result kept in SDRAM is uploaded to ARM by SPI communication module after terminating by sampling, it is managed collectively by ARM, after action completes, release symbol is uploaded to ARM by SPI by FPGA, represents that this action completes, can carry out lower set.
The specific works flow process of two stage control system of the present invention is.
1, first order control system workflow is as shown in figure 13.
After S1, system electrification, embedded OS and user's setup parameter are initialized by instrument.Including: the initialization of motor action step number, each parametric calibration factor initialization etc..
S2, entrance human-computer interaction interface, user can carry out various operation by human-computer interaction interface to instrument, by the switching at each interface and click different buttons, different operations can be completed, including selecting the operation of various auxiliary movement, selection analysis motion action, system management operation.
If S3 user's selection analysis action, then jump to step S4；If user selects auxiliary movement, then jump to step S8；If with selecting system management operation, then jumping to step S9.
S4, ARM send analysis action directive by SPI communication module to FPGA.
S5, ARM receive, by SPI communication module, the sampled data that FPGA uploads.
After S6, ARM have received the data that FPGA uploads, by human-computer interaction interface or USB interface, analysis result is shown in LCDs, result is stored in the data base of outside SD card memory module simultaneously and carries out report by LPT external printer module and print, also data can be sent to LIS system by RS232.
After S7, release, jump to step S2 and carry out next operation for user.
S8, ARM send auxiliary movement control command by SPI communication module to FPGA.Jump to step S7 and wait release.
System is managed by S9, user, look back including historical data, the amendment of user's setup parameter, report print, carried out data transmission by RS232 and carried out and the operation such as extraneous communication by network interface or USB interface, and this operation jumps to step S2 and supplies user to carry out next operation after terminating.
2, the workflow of second level control system is as shown in figure 14.
After S1, system electrification, user's setup parameter is initialized.Including each electromagnetic valve, reset motor, SDRAM initialization etc..
S2, system wait, at SPI communication module, the control command that ARM sends, and when detecting that ARM has control command to send to FPGA, FPGA starts SPI data reception module, receives the control command that ARM sends, and resolves order.
If the order that S3 ARM sends is for analyzing action command, then jump to step S4；If it is auxiliary movement control command that ARM is sent to order, then jump to step S8.
S4, it is analyzed action by motor drive module, electromagnetic valve ON/OFF control module, carries out display lamp by digital output modul module breakdown action, and by state detection module, system mode is monitored.
S5, carrying out data acquisition by signal acquisition module, data are temporarily stored into SDRAM memory module after treatment.
The data stored in SDRAM are uploaded to ARM by SPI communication module after terminating by S6, sampling.
By SPI communication module to ARM sending action end mark after S7, release, jump to the control commands next time to be received such as step S2.
S8, completed corresponding actions by motor drive module, electromagnetic valve ON/OFF control module, and jump to step S7 and wait release.
3, carrying out information exchange by SPI communication module between two-stage system, line is few, simple in construction, and therefore capacity of resisting disturbance is strong, and the transmission of signal is more stable, reliable.
In instrument work process, first order control system managing instrument as a whole, clearly, Each performs its own functions, thus improves the real-time of system, motility and reliability in the two-stage system division of labor.
Claims (2)
1. the microprocessor of a blood analyser/field programmable gate array two stage control system, it is characterized in that being made up of two stage control system, wherein: first order control system is with microprocessor as core, second level control system is with field programmable gate array as core, first order control system is attached with SPI communication with second level control system, and the operating system of first order control system is embedded Windows CE 5.0；
Described first order control system is made up of ARM microprocessor, human-computer interaction interface module, outside SD card memory module, LPT external printer module, USB interface module, SPI communication module, power supply interface module, RS232 interface module, USB2.0 interface module, RG45 Network Interface Module；Wherein module is driven to realize man-machine dialog interface with the built-in LCD of ARM；Module is driven to realize access and the management of data with the storage of ARM built-in SD card；Printer driver is realized with the external printer LPT interface of standard or USB 2.0 interface of standard；The communication with first order control system is realized with SPI interface；System power supply is realized with power supply interface module；Meanwhile, system provides 1 standard VGA interface, 4 standard USB 2.0 interfaces, 3 standard RS232 interfaces, 1 LPT interface, 1 RG45 network interface；Wherein ARM primary processor is SAMSUNG S3C2442B；LCD module is LQ104V1DG52；SD card is Kingston 2G, 4G, 8G or 16G；RS232 baud rate is 115200, stops position 1bit, data bit 8 bits, no parity check position；
Described second level control system is made up of FPGA, power interface, SPI communication module, signal acquisition module, state detection module, digital output modul module, Power Entry Module, I/O expansion module, motor drive module, electromagnetic valve ON/OFF module, SDRAM memory module；It is main composition second level control system with FPGA；The communication with first order control system is realized with SPI interface；Realized to the power supply of first order control system by power interface；Control A/D converter by SPI and realize signals collecting, 8 road signals can be carried out parallel acquisition and process simultaneously；Realized the state-detection of whole system by SPI control A/D converter and MUX, 8 kinds of different status signals of system can be detected；5 LED light-emitting diode switchs controls can be realized by digital output modul and a buzzer warning is controlled；No. 4 motor parallel drive and controls are realized by motor drive module；The 24 parallel ON/OFF of way solenoid valve and controls are realized by electromagnetic valve ON/OFF module；2 road SDRAM parallel control are realized by SDRAM control module；Power supply input directly connects external power source, it is achieved whole system is powered；I/O expands interface and expands use as later stage system；EP2C20F484C8 during wherein FPGA is altera corp's CycloneII series；
Described SPI communication, is made up of FPGA SPI interface and ARM SPI interface；SPI communication interface achieves the information exchange between two stage control system and data transmission, and two stage control system is connected as an entirety；Wherein CS, CLK, MISO, MOSI of first order control system is connected with second level control system CS, CLK, MOSI, MISO end respectively.
2. the control method of the microprocessor of the blood analyser described in claim 1/field programmable gate array two stage control system, is characterized in that being realized by the following step:
First order control system:
S1, system initialization: after system electrification, embedded OS and user's setup parameter are initialized by instrument；
S2, entrance human-computer interaction interface: user can carry out various operation by human-computer interaction interface to instrument, including selecting the operation of various auxiliary movement, the operation of selection analysis sampling action, system management operation；
If S3 user's selection analysis action, then jump to step S4；If user selects auxiliary movement, then jump to step S8；If with selecting system management operation, then jumping to step S9；
S4, ARM send analysis action directive by SPI communication module to FPGA；
S5, ARM receive, by SPI communication module, the sampled data that FPGA uploads；
After S6, ARM have received the data that FPGA uploads, by human-computer interaction interface or USB interface, the data received are shown in LCDs, result are stored in the data base of outside SD card memory module simultaneously and are analyzed report printing by LPT external printer module；
After S7, release, jump to step S2 and carry out next operation for user；
S8, ARM send auxiliary movement control command by SPI communication module to FPGA, jump to step S7 and wait release；
System is managed by S9, user, look back including historical results, user's setup parameter is revised, report prints, carried out data transmission by RS232 and carry out communication operation by network interface or USB port with the external world, and this operation jumps to step S2 and supplies user to carry out next operation after terminating；
Second level control system:
After S1, system electrification, user's setup parameter is initialized；
S2, system wait, at SPI communication module, the control command that ARM sends, and after receiving order resolve order；
If the order that S3 ARM sends is for analyzing action command, then jump to step S4；If the order that ARM sends is auxiliary movement order, then jump to step S8；
S4, it is analyzed action by motor drive module, electromagnetic valve ON/OFF control module, and by state detection module, system mode is monitored；
S5, carrying out data acquisition by signal acquisition module, the data collected are temporarily stored into SDRAM memory module after treatment；
The data stored in SDRAM are uploaded to ARM by SPI communication module after terminating by S6, sampling；
By SPI communication module to ARM sending action end mark after S7, release, jump to the wait of step S2 and order next time；
S8, completed corresponding auxiliary movement by motor drive module, electromagnetic valve ON/OFF control module, and jump to step S7 and wait release.
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| CN103324117B (en) * | 2013-05-24 | 2016-09-28 | 南昌大学 | The microprocessor of blood analyser/field programmable gate array two stage control system |
| CN104571059B (en) * | 2015-01-22 | 2017-11-10 | 山东省科学院能源研究所 | A kind of medical stroke of trigger automatic control system |
| CN106383223A (en) * | 2016-08-31 | 2017-02-08 | 世纪亿康（天津）医疗科技发展有限公司 | Blood coagulation and platelet function analyzer |
| CN109426595A (en) * | 2017-08-21 | 2019-03-05 | 上海奕瑞光电子科技股份有限公司 | A kind of analysis system, method and the application of FPGA log |
| CN109470548A (en) * | 2018-12-18 | 2019-03-15 | 北矿检测技术有限公司 | A kind of electric-control system for pyrohydrolysis process |
| CN110154803A (en) * | 2019-04-09 | 2019-08-23 | 浙江腾亿新能源科技有限公司 | Direct-current charging post control device a kind of succinct and that compatibility is high |
| CN115524505A (en) * | 2022-08-29 | 2022-12-27 | 中山市创艺生化工程有限公司 | Blood analyzer based on double-platform system work |
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