CN103324117A - Microprocessor/FPGA two-step control system of blood analyzer - Google Patents

Microprocessor/FPGA two-step control system of blood analyzer Download PDF

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Publication number
CN103324117A
CN103324117A CN2013101959707A CN201310195970A CN103324117A CN 103324117 A CN103324117 A CN 103324117A CN 2013101959707 A CN2013101959707 A CN 2013101959707A CN 201310195970 A CN201310195970 A CN 201310195970A CN 103324117 A CN103324117 A CN 103324117A
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module
fpga
arm
control system
interface
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CN103324117B (en
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龙伟
赵雄锋
孙少杰
仝建
李蒙
林斌飞
张晓�
张星原
卢斌
万里霞
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Nanchang University
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Nanchang University
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Abstract

A microprocessor/FPGA two-step control system of a blood analyzer is mainly composed of an ARM microprocessor and a FPGA. According to the system, by the utilization of advantages of the ARM microprocessor and advantages of the FPGA, management and control of the instrument are separated, namely, the ARM serves as a core of a first-step control system and manages the whole instrument in an overall mode, and management work, such as human-computer interaction, displaying of analyzed results, image processing, report printing and data storage, is finished. The FPGA serves as a core of a second-step control system, the advantages that the FPGA is good in real-time performance, rich in resources, rapid in processing, capable of working concurrently and programmable are brought into full play, control functions of analysis of action, collection, processing and storage of data, failure monitoring and the like are finished, and the flexible design of an electronic system is achieved; the two steps of control systems are connected through an SPI communication module. The two steps of control systems perform own functions respectively and work cooperatively, and real-time performance, flexibility and reliability of the system are improved.

Description

The microprocessor of blood analyser/field programmable gate array two stage control system
Technical field
The invention belongs to the clinical examination manufacturing field of equipment, relate to blood analyser.
Background technology
At present, the control system of domestic main flow automatic blood analyzer, mostly the system architecture of ARM mainboard+drive plate is adopted in sampling.This system architecture, the ARM microprocessor should be finished motor-driven, solenoid valve ON/OFF etc. by drive plate and analyze the control functions such as action and malfunction monitoring, the again management work such as data acquisition, processing, demonstration, storage and man-machine interaction.Because embedded OS is prone to the phenomenons such as deadlock, thread deadlock in operational process, not only have influence on the management work such as image processing, data demonstration, man-machine interaction, the faults such as serious appearance motor desynchronizing, electromagnetic valve switch time-delay directly have influence on the collection of signal and finishing of instrumental analysis action.In addition, the ARM mainboard connects with drive plate by data line, address wire and control line, because on line is more, so the on line poor reliability, be subject to external interference, directly have influence on the reliability of system.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, designed the two stage control system by ARM microprocessor (management level)+on-site programmable gate array FPGA (Basic automation level) forms.System takes full advantage of ARM and FPGA advantage separately, has realized that the management and control of instrument separates, and namely first order control system is finished the management work such as analysis result demonstration, image processing, reporting printing, data storage take ARM as core; Second level control system is finished the control functions such as analysis action and data sampling and processing, storage, malfunction monitoring take FPGA as core; Message exchange between the two stage control system realizes by the SPI communication interface.Two stage control system is because on line is few, and therefore the control such as the analysis action of instrument function has improved reliability and the real-time of system by the FPGA complete independently.
Technical solutions according to the invention are: designed the two stage control system that is comprised of ARM+FPGA and realized differentiated control and control to blood analyser.Connect by the SPI communication interface between the two-stage system.
The first order is take ARM as hardware platform, the management environment of foundation take embedded Windows CE 5.0 as operating system, finish the overall management to whole instrument, realized visual man-machine function of exchange and to the management of blood analyser various functions and data sheet; Under the mode that management and control separates, the ARM primary processor no longer carries out the work such as numerous and diverse analysis action control, data acquisition, data processing, be absorbed in the overall management to whole system, the functions such as finishing man-machine interaction, analysis result demonstration, image processing, reporting printing, data storage, external communication make system's operation more stable, reliable.
The second level is take FPGA as core, but give full play to that the FPGA real-time is good, aboundresources, the fast concurrent working of processing speed and programmable advantage, ON/OFF and multichannel data parallel high-speed Real-time Collection when having realized parallel drive, the multipath electrovalve of multichannel motor, process and store, finish simultaneously the monitoring to the system hardware state, improved the real-time of system; Utilize the programmable characteristics of FPGA, can realize the flexible design of electronic system, namely under different requirements, can reset by the FPGA internal circuit configuration and realize difference in functionality, thereby improved greatly the dirigibility of Circuits System hardware capability, make the single circuit system have the function of many different circuit structures, meet the different needs, the dirigibility that has therefore improved system.
Message exchange between the two stage control system realizes by the SPI communication interface.Two stage control system is because on line is few, and therefore the control such as the analysis action of instrument function has improved reliability and the real-time of system by the FPGA complete independently.
Described first order control system is take microprocessor as core, also comprise human-computer interaction interface module, LPT external printer module, outside SD card memory module, the USB2.0 interface module of standard, standard RG45 Network Interface Module, standard VGA interface module, standard RS232 interface module, SPI communication module and power supply interface module, described module is connected with ARM respectively.
Described second level control system is take field programmable gate array as core, comprise that also SPI communication module, power supply interface module, motor drive module, solenoid valve ON/OFF module, SDRAM memory module, I/O expand module, Power Entry Module, switching value control module, state detection module, signal acquisition module, described module is connected with FPGA respectively.
Be connected by the SPI communication module between microprocessor and the field programmable gate array.
The course of work of the present invention is: during instrument work, the user can carry out various operations to instrument by first order control system human-computer interaction interface, comprises that historical results is looked back, the historical report singles print, analyzes Action Selection, various auxiliary movement selections etc.When user selection instrumental analysis motion action, send control command by the SPI communication interface to FPGA by ARM.FPGA resolves after receiving the order that ARM sends, according to command context, the control blood analyser is finished corresponding actions, simultaneously the haemocyte signal is gathered, the digital signal that collects is temporary in the SDRAM memory module after treatment, after signals collecting finishes analysis result temporary among the SDRAM is uploaded to ARM by the SPI communication module, carry out unified management by ARM, FPGA was uploaded to ARM by SPI with the release symbol after the analysis action was finished, represent that this action finishes, can carry out lower set.ARM is presented at it on liquid crystal display by human-computer interaction interface or VGA interface module after receiving the data that FPGA uploads, and the result is stored in the database of outside SD memory module simultaneously, and prints analysis report.
The specific works flow process of two stage control system is.
First order control system workflow.
S1, system initialization.After system powered on, instrument carried out initialization to embedded OS and user's setup parameter.
S2, enter human-computer interaction interface.The user can carry out various operations to instrument by human-computer interaction interface, comprises selecting various auxiliary movement operations, the operation of selection analysis sampling action, system management operation.
If S3 user selection analysis action then jumps to step S4; If the user selection auxiliary movement then jumps to step S8; If use the selective system bookkeeping, then jump to step S9.
S4, ARM send to FPGA by the SPI communication module and analyze action directive.
S5, ARM receive the sampled data that FPGA uploads by the SPI communication module.
After S6, ARM receive the data that FPGA uploads, by human-computer interaction interface or VGA interface the data that receive are shown on the LCDs, simultaneously the result are stored in the database of outside SD card memory module and carry out analysis report by LPT external printer module and print.
After S7, the release, jump to step S2 and carry out next operation for the user.
S8, ARM send the auxiliary movement control command by the SPI communication module to FPGA.Jump to step 7 and wait for release.
S9, user manage system, comprise historical results review, the modification of user's setup parameter, reporting printing, carry out data transmission and carry out the operations such as communication by network interface or USB interface and the external world by RS232, jump to step S2 behind this EO and carry out next operation for the user.
Second level control system workflow.
S1, system power on and rear user's setup parameter are carried out initialization.
S2, system wait for the control command that ARM sends at the SPI communication module, order are resolved after receiving order.
If the order that S3 ARM sends then jumps to step S4 for analyzing action command; If the order that ARM sends is the auxiliary movement order, then jump to step S8.
S4, analyze action by pieces such as motor drive module, solenoid valve ON/OFF control moulds, and by state detection module system state is monitored.
S5, carry out data acquisition by signal acquisition module, the data that collect were temporary in the SDRAM memory module after passing and processing.
After S6, sampling finish by the SPI communication module with the data upload of storing among the SDRAM to ARM.
Pass through the SPI communication module after S7, the release to ARM sending action end mark, jump to step S2 and wait for next time order.
S8, finish corresponding auxiliary movement by pieces such as motor drive module, solenoid valve ON/OFF control moulds, and jump to step S7 and wait for release.
The invention has the beneficial effects as follows, take full advantage of ARM and FPGA advantage separately, realized that the management and control of instrument separates.Take ARM as hardware platform, by setting up the management environment take embedded Windows CE 5.0 as operating system, finish the overall management to whole instrument, realized visual man-machine function of exchange and to the management of blood analyser various functions and data sheet; But utilize that the FPGA real-time is good, aboundresources, the fast concurrent working of processing speed and programmable advantage, realized the real-time control of system and the flexible design of multidiameter delay high-speed data acquisition and processing and electronic system.And only carry out message exchange by a SPI communication interface between the two-stage system, simple in structure, on line is few, so antijamming capability is strong, and communication is reliable.Whole analyser is managed as a whole by first order control system, and Each performs its own functions for two-stage system, collaborative work, has improved the travelling speed of instrument, has optimized the performance of instrument, has strengthened simultaneously real-time, dirigibility and the reliability of system.
Description of drawings
Accompanying drawing 1 is two stage control system structural representation of the present invention.
Accompanying drawing 2 is ARM first order control system functional interface schematic diagram.
Accompanying drawing 3 is FPGA second level control system high-level schematic functional block diagram.
Accompanying drawing 4 is the SPI communication module connection diagram between the two stage control system of the present invention.
Accompanying drawing 5 is the power interface connection diagram between the two stage control system of the present invention.
Accompanying drawing 6 is signal acquisition circuit figure of the present invention.
Accompanying drawing 7 is state detection circuit figure of the present invention.
Accompanying drawing 8 is switching value control circuit figure of the present invention.
Accompanying drawing 9 is motor-drive circuit figure of the present invention.
Accompanying drawing 10 is solenoid valve control circuit figure of the present invention.
Accompanying drawing 11 is SDRAM memory module circuit diagram of the present invention.
Accompanying drawing 12 is power input interface circuit diagram of the present invention.
Accompanying drawing 13 is first order control system workflow diagram of the present invention.
Accompanying drawing 14 is the second level of the present invention control system workflow diagram.
Embodiment
Embodiment.
The present invention is described further by following examples in connection with accompanying drawing.
Accompanying drawing 1 is two stage control system structural representation of the present invention.Mainly formed by first order control system, second level control system and SPI communication.Wherein first order control system is take ARM as main, and second level control system is take FPGA as main, and first order control system is connected with the SPI communication with second level control system, thereby makes two stage control system become as a whole.The operating system of first order control system is embedded Windows CE 5.0.
Accompanying drawing 2 is ARM first order control system functional interface schematic diagram of the present invention.Mainly formed by ARM microprocessor, human-computer interaction interface module, outside SD card memory module, LPT external printer module, VGA interface module, SPI communication module, power supply interface module, RS232 interface module, USB2.0 interface module, RG45 Network Interface Module.Wherein realize man-machine dialog interface with the built-in LCD driver module of ARM; Realize data access and management with the built-in SD card of ARM storing driver module; With the external printer LPT interface of standard or the USB 2.0 Interface realization printer driver of standard; Communication with SPI Interface realization and first order control system; Realize system power supply with power supply interface module; Simultaneously, system provides 1 standard VGA interface, 4 standard USB 2.0 interfaces, 3 standard RS232 interfaces, 1 LPT interface, 1 RG45 network interface; Wherein the ARM primary processor is SAMSUNG S3C2442B; The LCD module is LQ104V1DG52; The SD card is Kingston 2G, 4G, 8G or 16G; The RS232 baud rate is 115200, position of rest 1bit, data bit 8 bits, no parity check position; The power interface standard as shown in Figure 5; The SPI interface standard as shown in Figure 4.All the other standard interfaces all can connect corresponding common apparatus.
Accompanying drawing 3 is FPGA of the present invention second level control system functional interface schematic diagram.Mainly formed by FPGA, power interface, SPI communication module, signal acquisition module, state detection module, switching value control module, Power Entry Module, I/O expansion module, motor drive module, solenoid valve ON/OFF module, SDRAM memory module.It is take FPGA as main formation second level control system.Communication with SPI Interface realization and first order control system; Realize power supply to first order control system by power interface; Realize signals collecting by SPI control A/D converter, can carry out parallel acquisition and processing to 8 road signals simultaneously; Realize the state-detection of whole system by the control of SPI control A/D converter and MUX, can detect 8 kinds of different status signals of system; Can realize that by switching value control 5 LED light-emitting diode switchs are controlled and a buzzer warning is controlled; Realize No. 4 motor parallel drive and controls by motor drive module; Realize the parallel ON/OFF of 24 way solenoid valves and control by solenoid valve ON/OFF module; Realize 2 road SDRAM parallel control by the SDRAM control module; The power supply input directly connects external power source, realizes the whole system power supply; I/O expands interface and uses as later stage system's expansion.Wherein FPGA is the EP2C20F484C8 in the CycloneII of the altera corp series; The interface standard of SPI interface and second level control system as shown in Figure 4; The power interface standard as shown in Figure 5; SPI realizes A/D control and signal acquisition circuit figure as shown in Figure 6; SPI control A/D and traffic pilot are realized state detection circuit figure as shown in Figure 7; The switching value control circuit as shown in Figure 8; Motor driving controling circuit as shown in Figure 9; Solenoid valve control circuit as shown in figure 10; SDRAM control module circuit diagram as shown in figure 11; Power input interface as shown in figure 12.
Accompanying drawing 4 is the SPI communication interface schematic diagram of two stage control system of the present invention.Mainly formed by FPGA SPI interface and ARM SPI interface.The SPI communication interface has been realized message exchange and the data transmission between the two stage control system, connects two stage control system as a whole.Wherein the CS of first order control system, CLK, MISO, MOSI link to each other with second level control system CS, CLK, MOSI, MISO end respectively.
Accompanying drawing 5 supplies electrical schematic for two stage control system FPGA of the present invention second level control system to ARM first order control system.Mainly formed by second level control system power interface and first order control system power interface.Realized the power supply supply of first order control system by power interface, made the normal operation of first order control system.The power interface standard is: 1 pin is GND for+12VDC, 3 pin for-12VDC, 4 pin for+5VDC, 2 pin; Wherein 1 of second level control system power interface, 2,3,4 pin link to each other with 1,2,3,4 pin of first order control system power interface respectively.
Accompanying drawing 6 is signal acquisition module circuit diagram of the present invention.Mainly formed by DAD5, RAD5, UAD5.Wherein signal is input as signal input part to be collected, and the signal input requirements is 0-5VDC; DAD5 is the pressure limiting diode, and voltage limiting value is 5VDC, and with protection UAD5, DAD5 one end links to each other other end ground connection with the common port of signal input part and RAD5; RAD5 is build-out resistor, and with the stable signal that is input to UAD5, RAD5 one end links to each other with signal input part and DAD5 common port, 3 pin of another termination UAD5; UAD5 is A/D converter, realizes simulating signal to the conversion of digital signal, and 1 pin of UAD5 connects+the 5V power supply, 2 pin ground connection, and 3 pin connect RAD5 one pin, and 4,5,6 pin link to each other with AD_CLK5, AD_DATA5, the AD_CS5 of FPGA respectively; CAD9 and CAD10 realize+the 5V power filter jointly, for UAD5 provides stable working power.Wherein the signal input requirements is the 0-5VDC signal; DAD5 is 5V crest stabilivolt, and model is LL60; The RAD5 resistance is 100; The UAD5 model is ADS7883; CAD9 is 100nF; CAD10 is 10uF.
Accompanying drawing 7 is state detection module circuit diagram of the present invention.Mainly formed by U9, DAD3, RAD3, UAD3.Wherein U9 is multichannel quick closing valve selector switch, realize that the signal that different conditions detects switches, 1 pin of U9 links to each other with the PRINTER of printer test side, 2 pin link to each other with temperature sensor output terminal TEMP, 3 pin and RAD3, the common port of DAD3 links to each other, 4 pin link to each other with the output terminal VOL1 that aperture voltage 1 detects, 5 pin link to each other with the output terminal VOL2 that aperture voltage 2 detects, 6,7,8 pin ground connection, 9,10,11 pin respectively with the A_CD4051 of FPGA, B_CD4051, C_CD4051 links to each other, 12 pin link to each other with the output terminal PRESS of pressure transducer, 13 pin link to each other with cleaning fluid testing circuit output terminal DET, 14 pin link to each other with dilution testing circuit output terminal DIL, and 15 pin link to each other with the output terminal LYSE of hemolysin testing circuit, and 16 pin connect+the 5V power supply.DAD3 is the pressure limiting diode, and voltage limiting value is 5VDC, and with protection UAD3, DAD3 one end links to each other other end ground connection with 3 pin of U9 and the common port of RAD3; RAD3 is build-out resistor, and with the stable signal that is input to UAD3, RAD3 one end links to each other 3 pin of another termination UAD3 with 3 pin and the DAD3 common port of U9; UAD3 is A/D converter, realizes simulating signal to the conversion of digital signal, and 1 pin of UAD3 connects+the 5V power supply, 2 pin ground connection, and 3 pin connect RAD3 one pin, and 4,5,6 pin link to each other with AD_CLK3, AD_DATA3, the AD_CS3 of FPGA respectively; CAD5 and CAD6 realize+the 5V power filter jointly, for UAD3 provides stable working power.Wherein the U9 model is CD4051; DAD3 is 5V crest stabilivolt, and model is LL60; The RAD3 resistance is 100; The UAD3 model is ADS7883; CAD5 is 100nF; CAD6 is 10uF.
Accompanying drawing 8 is switching value control module circuit diagram of the present invention.Mainly formed by U27, U50, J6.Wherein U27 is the level latch, improve the driving force of FPGA output signal, LED_Yellow0, LED_Red0, LED_Green0, LED_Green1, LED_Yellow1, Buzzer0 end that 1,3,4,5,6,7 pin of U27 meet respectively FPGA link to each other, 2,8 pin ground connection, 9 pin link to each other with 2 pin of U50,10 pin link to each other with 1 pin of U50, and 11,12,13,14,16 pin link to each other with 2,4,6,8,10 pin of J6 respectively; U50 is buzzer interface; J6 is LED light-emitting diodes interface tube, and 1,3,5,7,9 pin of J6 link to each other with+24V power supply by R78, R79, R80, R81, R82 respectively.R85 is impedance matching resistance, and its two ends link to each other with 1,2 pin of U50 respectively; R78, R79, R80, R81, R82 are current-limiting resistance.Wherein the U27 model is ULN2003D; U50 is the 2Pin buzzer interface; J6 is 10Pin LED light-emitting diodes interface tube; The R85 resistance is 100K; R78, R79, R80, R81, R82 resistance are 4.7K.
Accompanying drawing 9 is motor drive module circuit diagram of the present invention.Mainly formed by U8 and J19.Wherein U8 is motor drive ic, realize motor-driven, 33 of U8,45,47 pin respectively with the DIRECTION of FPGA, CLK, the ENABLE end links to each other, 35,42,48 pass through respectively R32, R33, R34 links to each other with the 3.3V power supply, 30,31 pin link to each other with+5V power supply, 26,26,55,56 pin link to each other with+24V_MOTOR power supply, 6,7 pin link to each other with 2 pin of J19,10,11 pin link to each other 19 with 3 pin of J19,20 pin link to each other 61 with 4 pin of J19,62 pin link to each other with 1 pin of J19,2,4 pin are by R44 ground connection, 13,14 pin are by R43 ground connection, 16,35,38,39,43,50,51,64 pin ground connection, 53 pin are by C24 ground connection; J19 is the motor wire base; R32, R33, R34 are current-limiting resistance; C16, C17 form filtering circuit jointly, the interference of filtering+5V; C18, C19 form the undesired signal of filtering circuit filtering+24V_MOTOR jointly; R43, R44 are current-limiting resistance.Wherein U8 is TB6560AFG; R32, R33, R34 resistance are 10K; C16, C19 are the electric capacity of 10uF; C17, C18 are the electric capacity of 100nF; C24 is the electric capacity of 300PF; R43, R44 resistance are 0.33 Ω.
Accompanying drawing 10 is solenoid control modular circuit of the present invention.Mainly formed by R15, Q1, J1.Wherein R15 is current-limiting resistance, and an end links to each other with the control end of the Valve1 of FPGA, and the other end links to each other with 2 pin of Q1; Q1 is the CMOS triode, the 1 pin ground connection of Q1, and 2 pin link to each other with R15 one end, and 3 pin link to each other with 1 pin of J1; J1 is the solenoid valve wire base, and 1 pin of J1 links to each other with 3 pin of Q1, and 2 pin link to each other with+24V_VALVE power supply.Wherein the R15 resistance is 180 Ω; The Q1 model is 2N5551.
Accompanying drawing 11 is SDRAM memory module circuit diagram of the present invention.Mainly formed by US1, thereby realize data storage and read.1 of US1,14,27,3,9,43,49 pin link to each other with the 3.3V power supply, 16,17,18,19 SDRAM_WE respectively at FPGA, SDRAM_CAS, SDRAM_RAS, SDRAM_CE links to each other, 20,21 pin are respectively at the SDRAM_BA0 of FPGA, SDRAM_BA1 links to each other, 23,24,25,26,27,28,29,30,31,32,33,34,35,36 pin are respectively at the SDRAM_A0 of FPGA, SDRAM_A1, SDRAM_A2, SDRAM_A3, SDRAM_A4, SDRAM_A5, SDRAM_A6, SDRAM_A7, SDRAM_A8, SDRAM_A9, SDRAM_A10, SDRAM_A11, SDRAM_A12 links to each other, 2,4,5,7,10,11,13,42,44,45,47,48,50,51,53 pin are respectively at the SDRAM_DQ0 of FPGA, SDRAM_DQ1, SDRAM_DQ2, SDRAM_DQ3, SDRAM_DQ4, SDRAM_DQ5, SDRAM_DQ6, SDRAM_DQ7, SDRAM_DQ8, SDRAM_DQ9, SDRAM_DQ10, SDRAM_DQ11, SDRAM_DQ12, SDRAM_DQ13, SDRAM_DQ14, SDRAM_DQ15 links to each other, 15,39 pin are respectively at the SDRAM_DQM0 of FPGA, SDRAM_DQM1 links to each other, 28,41,54,6,12,46,52 pin ground connection, 37,38 pin respectively with the SDRAM_CKE of FPGA, SDRAM_CLK links to each other.
Accompanying drawing 12 is power supply interface module circuit diagram of the present invention.J1-1 connects outside input power, and outside input power is+12VDC.
During instrument work, send order by ARM to FPGA, FPGA resolves after receiving the order that ARM sends, according to command context, control blood analyser actuator is finished corresponding actions, simultaneously cell signal etc. is gathered, collection signal is temporary in the SDRAM module after treatment, after sampling finishes result temporary among the SDRAM is uploaded to ARM by the SPI communication module, carry out unified management by ARM, FPGA was uploaded to ARM by SPI with release symbol after action was finished, and represented that this action finishes, and can carry out lower set.
The specific works flow process of two stage control system of the present invention is.
1, first order control system workflow as shown in figure 13.
After S1, system powered on, instrument carried out initialization to embedded OS and user's setup parameter.Comprise: the initialization of motor action step number, each parametric calibration factor initialization etc.
S2, enter human-computer interaction interface, the user can carry out various operations to instrument by human-computer interaction interface, switching by each interface and click different buttons can be finished different operations, comprises and selects various auxiliary movement operations, selection analysis motion action, system management operation.
If S3 user selection analysis action then jumps to step S4; If the user selection auxiliary movement then jumps to step S8; If use the selective system bookkeeping, then jump to step S9.
S4, ARM send to FPGA by the SPI communication module and analyze action directive.
S5, ARM receive the sampled data that FPGA uploads by the SPI communication module.
After S6, ARM receive the data that FPGA uploads, by human-computer interaction interface or VGA interface analysis result is shown on the LCDs, simultaneously the result is stored in the database of outside SD card memory module and by LPT external printer module and carries out reporting printing, also data communication device can be crossed RS232 and be sent to the LIS system.
After S7, the release, jump to step S2 and carry out next operation for the user.
S8, ARM send the auxiliary movement control command by the SPI communication module to FPGA.Jump to step 7 and wait for release.
S9, user manage system, comprise historical data review, the modification of user's setup parameter, reporting printing, carry out data transmission and undertaken and the operation such as extraneous communication by network interface or USB interface by RS232, jump to step S2 behind this EO and carry out next operation for the user.
2, the workflow of second level control system as shown in figure 14.
S1, system power on and rear user's setup parameter are carried out initialization.Comprise each solenoid valve, reset motor, SDRAM initialization etc.
S2, system wait for the control command that ARM sends at the SPI communication module, and when detecting ARM and have control command to send to FPGA, FPGA starts the SPI data reception module, receives the control command that ARM sends, and order is resolved.
If the order that S3 ARM sends then jumps to step S4 for analyzing action command; If it is the auxiliary movement control command that ARM sends to order, then jump to step S8.
S4, analyze action by motor drive module, solenoid valve ON/OFF control module, carry out pilot lamp by switching value control module breakdown action, and and by state detection module system state is monitored.
S5, carry out data acquisition by signal acquisition module, data are temporary in the SDRAM memory module after treatment.
After S6, sampling finish by the SPI communication module with the data upload of storing among the SDRAM to ARM.
Pass through the SPI communication module after S7, the release to ARM sending action end mark, jump to step S2 wait and receive next time control command.
S8, finish corresponding actions by motor drive module, solenoid valve ON/OFF control module, and jump to step S7 and wait for release.
3, carry out message exchange by the SPI communication module between the two-stage system, line is few, and is simple in structure, so antijamming capability is strong, and the transmission of signal is more stable, reliable.
In the instrument course of work, by the first order control system instrument is managed as a whole, the two-stage system division of labor is clear and definite, and Each performs its own functions, thereby improved real-time, dirigibility and the reliability of system.

Claims (2)

1. the microprocessor of a blood analyser/field programmable gate array two stage control system is characterized in that being comprised of two stage control system, wherein:
First order control system is take microprocessor as core, also comprise alternating interface between man and computer module, LPT external printer driver module, outside SD card data memory module, the USB2.0 interface module of standard, standard RG45 Network Interface Module, standard VGA interface module, standard RS232 interface module, SPI communication module and power supply interface module, described module is connected with ARM respectively;
Second level control system is take field programmable gate array as core, comprise that also SPI communication module, power supply interface module, motor drive module, solenoid valve ON/OFF module, SDRAM memory module, I/O expand module, Power Entry Module, switching value control module, state detection module, signal acquisition module, described module is connected with FPGA respectively;
Be connected by the SPI communication module between microprocessor and the field programmable gate array.
2. the control method of two stage control system claimed in claim 1 is characterized in that being realized by the following step:
First order control system:
S1, system initialization: after system powered on, instrument carried out initialization to embedded OS and user's setup parameter;
S2, enter human-computer interaction interface: the user can carry out various operations to instrument by human-computer interaction interface, comprises selecting various auxiliary movements operations, the operation of selection analysis sampling action, system management operation;
If S3 user selection analysis action then jumps to step S4; If the user selection auxiliary movement then jumps to step S8; If use the selective system bookkeeping, then jump to step S9;
S4, ARM send to FPGA by the SPI communication module and analyze action directive;
S5, ARM receive the sampled data that FPGA uploads by the SPI communication module;
After S6, ARM receive the data that FPGA uploads, by human-computer interaction interface or VGA interface the data that receive are shown on the LCDs, simultaneously the result are stored in the database of outside SD card memory module and carry out analysis report by LPT external printer module and print;
After S7, the release, jump to step S2 and carry out next operation for the user;
S8, ARM send the auxiliary movement control command by the SPI communication module to FPGA, jump to step 7 and wait for release;
S9, user manage system, comprise historical results review, the modification of user's setup parameter, reporting printing, carry out data transmission and carry out the operations such as communication by network interface or USB mouth and the external world by RS232, jump to step S2 behind this EO and carry out next operation for the user;
Second level control system:
S1, system power on and rear user's setup parameter are carried out initialization;
S2, system wait for the control command that ARM sends at the SPI communication module, order are resolved after receiving order;
If the order that S3 ARM sends then jumps to step S4 for analyzing action command; If the order that ARM sends is the auxiliary movement order, then jump to step S8;
S4, analyze action by pieces such as motor drive module, solenoid valve ON/OFF control moulds, and by state detection module system state is monitored;
S5, carry out data acquisition by signal acquisition module, the data that collect were temporary in the SDRAM memory module after passing and processing;
After S6, sampling finish by the SPI communication module with the data upload of storing among the SDRAM to ARM;
Pass through the SPI communication module after S7, the release to ARM sending action end mark, jump to step S2 and wait for next time order;
S8, finish corresponding auxiliary movement by pieces such as motor drive module, solenoid valve ON/OFF control moulds, and jump to step S7 and wait for release.
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