CN103324116A - Endat signal acquisition card based on three-connection mode - Google Patents
Endat signal acquisition card based on three-connection mode Download PDFInfo
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- CN103324116A CN103324116A CN2013101933482A CN201310193348A CN103324116A CN 103324116 A CN103324116 A CN 103324116A CN 2013101933482 A CN2013101933482 A CN 2013101933482A CN 201310193348 A CN201310193348 A CN 201310193348A CN 103324116 A CN103324116 A CN 103324116A
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Abstract
The invention discloses an Endat signal acquisition card based on a three-connection mode. The Endat signal acquisition card comprises a differential signal processing unit, a programmable logic device, a single chip microcomputer, an expansion interface circuit, a data-caching unit, a communication interface circuit and a power switching and voltage stabilizing circuit. The acquisition card is in data communication with a computer through a USB 2.0 interface. The Endat signal acquisition card achieves the purpose of Endat signal acquisition in the three-connection mode, provides a independent signal input interface with two channels and can be used in the field of industrial measurement and control. The Endat signal acquisition card has the advantages of being high in sampling accuracy, high in data accuracy, wide in sampling frequency range, continuous and adjustable, convenient to install, easy to use and the like.
Description
Technical field
The present invention relates to the industrial measurement and control field, particularly adopt the threeway mode to be used for obtaining the capture card of Endat signal in the industrial measurement and control field.
Background technology
Along with the development of Numeric Control Technology, absolute optical encoder and grating be because the advantage such as its acquisition of information is convenient, transmission range is long, operating noise is little, so that it more and more is used in monitoring machine bed motion in the digital control system.In the face of this development trend, a lot of companies of the same trade have all developed towards the interface protocol of absolute type measuring sensor both at home and abroad, the wherein low favor that obtains each large numerical control manufacturer of the whole world of the Endat interface released of German Heidenhain company, cost high because of its quality is widely used in high precision, the high performance numerical control field.
The Endat interface is digital, the full duplex synchronous serial interface that Heidenhain aims at encoder design.It can not only transmit the positional value of absolute type or incremental encoder, also can transmit or upgrade the information that is kept in the scrambler.Owing to having adopted the serial transmission mode, so only need 4 signal line, under the clock drive of follow-up electronic equipment, data message is by synchronous transmission.Wherein, the Endat2.2 interface clock is up to 8M, and this will shorten the time of reading positional value greatly, can satisfy the application that this class high dynamic performance of direct driving requires, and these advantages all make it use more and more wider in high-grade machine tool field.
At present, because digital control system is fully not open, can not be directly from the servo port acquired information.But can signal be drawn by the threeway mode, then follow-up electronic equipment is processed signal, obtains the lathe corresponding information.For the Endat interface signal, because data message is encoded by certain format, so need to decode in strict accordance with the Endat sequential, this has strengthened the acquisition of information difficulty undoubtedly.In the document of reporting at present, do not obtain capture card or the equipment of Endat signal by the threeway mode, so the capture card of exploitation this type will have important scientific research value and engineering significance.
Summary of the invention
The object of the present invention is to provide a kind of Endat data acquisition card based on the threeway mode, this data acquisition card can gather numerically-controlled machine Endat format signal.
For achieving the above object, the present invention has adopted following technical scheme:
This capture card comprises differential signal processing unit, programmable logic device (PLD), single-chip microcomputer, expansion interface circuit, data buffer storage unit, communication interface circuit and power supply switch voltage-stabilizing circuit; Described differential signal processing unit comprises that the differential signal that links to each other with the exit of three messengers turns the single-ended signal circuit and turns the signal filtering treatment circuit that the single-ended signal circuit links to each other with differential signal; Programmable logic device (PLD) links to each other with signal filtering treatment circuit, data buffer storage unit, expansion interface circuit and single-chip microcomputer respectively; One end of communication interface circuit links to each other with single-chip microcomputer, and the other end is provided with for the USB interface that connects computing machine; The power supply switch voltage-stabilizing circuit links to each other with differential signal processing unit, programmable logic device (PLD), single-chip microcomputer, expansion interface circuit, data buffer storage unit and communication interface circuit respectively.
Described programmable logic device (PLD) internal configurations generates inner decoding module, inner sampling clock generation module and three modules of single chip communication interface; The inner decoding module according to the time ordered pair Endat signal decode, and store decoded data into data buffer storage unit; Inner sampling clock generation module is according to the sample frequency of computer installation, carry out frequency division by the work clock to programmable logic device (PLD) and obtain required inner sampling clock, at the sampling clock rising edge, deliver to the single chip communication interface after latest data in the data buffer storage unit read, then send interruption to single-chip microcomputer, wait for that single-chip microcomputer reads data in the computing machine.
In decode phase, the length that the inner decoding module at first configures for the receiving mode instruction is the shift register of 6Bit, then judges the Endat version according to the mode instruction that receives; Then receive initialization, configured length is the register of 56Bit, front 48Bit storage Endat positional value, and rear 8Bit storage CRC check value, at decode phase, the displacement receive data stores in the data buffer storage unit after CRC check is correct.
Described expansion interface circuit intercoms mutually with programmable logic device (PLD), and the inner sampling clock that produces of programmable logic device (PLD) is drawn, and expansion interface circuit also provides the external clock input port simultaneously.
What described single-chip microcomputer adopted is the C8051F340 single-chip microcomputer, computing machine by communication interface circuit with parameter read-in in single-chip microcomputer, single-chip microcomputer arranges work according to start and stop, the transmission of data and the parameter of write parameters type completion system; In the transmission of data stage, the USB interface that data communication device is crossed in the communication interface circuit sends in the computing machine, usb communication cycle by computing machine send control information, single-chip microcomputer sends data and the computer receiving data three phases is finished.
Described differential signal turns the single-ended signal circuit and comprises the AM26LS32 chip, the Endat signal that the differential signal processing unit utilizes the AM26LS32 chip that the exit by three messengers is introduced capture card converts single-ended signal to by differential signal, then utilize the signal filtering treatment circuit successively single-ended signal to be carried out RC low-pass filtering treatment and waveform arrangement, make single-ended signal convert the LVTTL form to.
Beneficial effect of the present invention is embodied in: the present invention at first passes through Signal Pretreatment, filtering external interference signals; Then by corresponding signal decoding module, finish complicated Endat sequential decoding, and data carried out CRC check, got access to accurately and effectively the Endat signal, successfully solved in digital control system in open type not, the Endat signal obtain a difficult problem.
The present invention has advantages of:
1. sampling precision is high.The present invention carries out corresponding Signal Pretreatment to input signal, has effectively avoided the impact of external noise on system, has greatly improved the sampling precision of capture card.
2. the data precision is high.The present invention carries out the CRC redundancy check to data, has effectively got rid of the mistake that produces in the signals transmission, thereby described capture card has higher the data precision.
3. the sample frequency wide ranges is adjustable continuously.Sample frequency of the present invention can be regulated continuously at 200Hz～5KHz, has overcome the shortcoming that part capture card frequency can not be regulated continuously.
4. easy for installation, be easy to use.The present invention only need to be linked into three messengers on the capture card, can not exert an influence to original system, can transfer data in the computing machine by the usb data line.
5. integrated level is high.The present invention adopts FPGA to realize signal decoding, generation sampling clock, data processing, has very high integrated level and dirigibility.
Description of drawings
Fig. 1 is threeway acquisition principle figure of the present invention;
Fig. 2 is hardware elementary diagram of the present invention;
Fig. 3 is signal pre-processing circuit figure of the present invention; U11 represents the element sequence number of AM26LS32, and U7 represents the element sequence number of 74LVC14A;
Fig. 4 is Endat signal decoding sequential chart of the present invention; DATA represents the Endat data, and CLOCK represents Endat clock, t
STExpression III release time, t
CalRepresent computing time, t
mExpression I release time, t
RExpression II release time, S represents the data reference position, and F1 represents the rub-out signal I, and F2 represents the rub-out signal II, and L represents the data lowest byte, M represents the data highest byte;
Fig. 5 is that sampling clock of the present invention is selected schematic diagram; The AND2 presentation logic represents and the computing module name with, inst, and the NOT presentation logic is non-, and inst2 represents the inverse module name, and inst1 represents and the computing module name, the OR presentation logic or, inst3 represents the exclusive disjunction module name;
Fig. 6 is usb communication sequential chart of the present invention;
Fig. 7 is supply voltage switch voltage-stabilizing circuit schematic diagram of the present invention; D3 represents the element sequence number of LT1086CM-3.3, and P4 represents the element sequence number of Header2;
Fig. 8 is the as a result figure that capture card of the present invention is tested.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
Referring to Fig. 1, what the present invention adopted is built-in sensors signal sampling principle, obtain feedback signal between commercial unit and the control system by the threeway mode, under the prerequisite that can not exert an influence to industrial control system, with the road signal leading told in acquisition system, reach the purpose of obtaining signal, comprise computing machine and capture card in the acquisition system.
Referring to Fig. 2, capture card of the present invention is based on the Endat data acquisition card of threeway mode, have the two paths of signals input interface, capture card major function unit comprises: differential signal processing unit, programmable logic device (PLD) (FPGA), single-chip microcomputer (MCU), expansion interface circuit (extended interface unit), data buffer storage unit, communication interface circuit and power supply switch voltage-stabilizing circuit.
The exit of the input termination threeway signal of described differential signal processing unit, this element comprise that differential signal turns single-ended signal circuit, signal filtering treatment circuit, and differential signal processing unit output signal is connected to programmable logic device (PLD) (FPGA) input end.
Described programmable logic device (PLD) (FPGA) is mainly finished the work of Endat signal decoding, and decoded data are stored in the data buffer storage unit.
Described single-chip microcomputer (MCU) is as system CPU, main completion system control work, communicate by letter with programmable logic device (PLD), communication interface circuit, receive on the one hand the control parameter from computing machine, on the other hand the data communication device that collects is crossed communication interface circuit and be transferred in the computing machine.
Described expansion interface circuit intercoms mutually with programmable logic device (PLD), the inner sampling clock that produces of programmable logic device (PLD) is drawn, can be used as the external trigger clock of other capture card, also provide the external clock input port simultaneously, instruct the work of this capture card.
Described communication interface circuit is connected with computing machine by USB interface.
Described power supply switch voltage-stabilizing circuit is responsible for the conversion of supply voltage, and system's 5V direct supply is converted to the 3.3V direct supply and carries out voltage stabilizing, is above-mentioned each the unit power supply of system.
Referring to Fig. 3, in the signal pre-processing circuit of the present invention, PA1+, PA1-are connected to the 1A that difference turns single-ended chip AM26LS32, are output as 1Y; On the 1B port, PB1+, PB1-are connected to the 2A that difference turns single-ended chip, on the 2B port, are output as 2Y; PA2+, PA2-are connected to the 3A that difference turns single-ended chip, on the 3B port, are output as 3Y; PB2+, PB2-are connected to the 4A that difference turns single-ended chip, on the 4B port, are output as 4Y.1Y is output as PA1 through the filtering circuit that R15, C12 form; 2Y is output as PA2 through the filtering circuit that R13, C11 form; 3Y is output as PA3 through the filtering circuit that R25, C20 form; 4Y is output as PA4 through the filtering circuit that R26, C21 form.PA1 is connected to phase inverter 1A end, is output as 1PA; PA2 is connected to phase inverter 2A end, is output as 1PB; PA3 is connected to phase inverter 3A end, is output as 2PA; PA4 is connected to phase inverter 4A end, is output as 2PB.R14 is auxiliary resistance, and C28, C9 are auxiliary capacitor.Signal Pretreatment flow process of the present invention is: after the Endat signal is drawn by the threeway port, be connected on the differential signal processing unit input interface of the present invention, this element converts differential signal to the single-ended signal that is suitable for follow-up system work, and what difference turned single-ended chip employing is the AM26LS32 chip of TI company.Then the single-ended signal after the conversion is carried out the RC low-pass filtering treatment, the filtering noise signal, and adopt phase inverter that signal is carried out the waveform arrangement, and signal is converted to the LVTTL format signal of 3.3V, then output in the programmable logic device (PLD) (FPGA).What phase inverter adopted is the 74LVC14A chip of Philips company, and it can export the LVTTL format signal of 3.3V.
Programmable logic device (PLD) (FPGA) is by software configuration integrate inner decoding module, inner sampling clock generation module and three modules of single chip communication interface, inner decoding module ordered pair Endat signal according to as shown in Figure 4 the time is decoded, and stores decoded data into data buffer storage unit.
In decode phase, at first detect Endat signal clock line high level, obtain the system communication frequency, reusing system 100M clock is counted between Endat signal clock high period, gate time surpasses 10us(system communication frequency less than 1Mhz) or 1.25us(system communication frequency greater than 1Mhz), then get access to the communication starting point; Then configured length is the shift register of 6Bit, is used for the receiving mode instruction, according to the mode instruction that receives, judges the Endat version, then receives initialization.Configured length is the register of 56Bit, front 48Bit storage Endat positional value, rear 8Bit storage CRC check value, at decode phase, the displacement receive data stores in the buffer memory after CRC check is correct, at the sampling clock rising edge, send data cached into the single chip communication interface, and send interruption, wait for that host computer reads.
Referring to Fig. 5, inner sampling clock generation module is according to the sample frequency of computer installation, by being carried out frequency division, FPGA work clock (100M) obtains required inner sampling clock, when needs use the external sampling clock, can on computers trigger mode be made as external trigger, then MCU can write triggering selection code 0X01 among the FPGA, selects external clock as sampling clock, otherwise be defaulted as the internal trigger pattern, the triggering selection code is 0X00.At the sampling clock rising edge, latest data in the data buffer storage unit is read, deliver to the single chip communication interface, send interrupt INT 0 to single-chip microcomputer, wait for that single-chip microcomputer reads data in the computing machine, what programmable logic device (PLD) adopted is the EPM1270T144C3 chip of the MAXII of altera corp series.
Referring to Fig. 6, in single-chip microcomputer (MCU) unit, CPU as acquisition system, computing machine by communication interface circuit with parameter read-in in single-chip microcomputer, single-chip microcomputer arranges work according to start and stop, the transmission of data, the parameter of write parameters type completion system, and what single-chip microcomputer adopted is the C8051F340 single-chip microcomputer of Silicon Labs.In the transmission of data stage, the USB2.0 interface that data communication device is crossed in the communication interface circuit unit sends to data in the computing machine, usb communication cycle by host computer send control information, slave computer sends data, host computer receive data three phases is finished.
Extended interface unit of the present invention also provides external trigger clock introducing interface and internal clocking to draw interface except carrying out the work expansion capture card, has greatly strengthened the function of system.
Because the present invention need to change the signal level form, as adopt phase inverter 74LVC14A signal to be converted to the LVTTL level signal of 3.3V, this chip needs the power supply of 3.3V, because what the present invention adopted is the independent DC power supply power supply of 5V, so need to change supply voltage, voltage stabilizing, circuit theory as shown in Figure 7, Header2 is outlet, + 5V power supply is connected to the input port VIN of voltage stabilizing chip LT1086CM-3.3, VOUT outputs to vdd terminal by output port, output voltage 3.3V; Voltage stabilizing chip bottom line end GND is connected on the ground wire, and CD1, CD2, CD3, CD4, CD5, CD6 are the voltage stabilizing auxiliary capacitor.
Referring to Fig. 8, utilize capture card of the present invention to test on a certain model grinding machine at home, allow Y-axis (adopting the Endat signal) go to 5mm from 30mm, carry out in this course data acquisition, collection result is consistent with the lathe actual motion, has finished accurately and effectively signals collecting.
Capture card of the present invention provides two passages, signal input interface independently, can be used for the industrial measurement and control field, has more than described ultimate principle of the present invention, principal character and advantage.The technician of the industry should understand; the present invention is not subjected to the impact of above-described embodiment, and that describes in above-described embodiment and the instructions just illustrates principle of the present invention, without departing from the inventive concept of the premise; simply deduce and conversion, all should be considered as protection scope of the present invention.
Claims (6)
1. Endat data acquisition card based on the threeway mode, it is characterized in that: this capture card comprises differential signal processing unit, programmable logic device (PLD), single-chip microcomputer, expansion interface circuit, data buffer storage unit, communication interface circuit and power supply switch voltage-stabilizing circuit; Described differential signal processing unit comprises that differential signal turns the single-ended signal circuit and turns the signal filtering treatment circuit that the single-ended signal circuit links to each other with differential signal; Programmable logic device (PLD) links to each other with signal filtering treatment circuit, data buffer storage unit, expansion interface circuit and single-chip microcomputer respectively; One end of communication interface circuit links to each other with single-chip microcomputer, and the other end is provided with for the USB interface that connects computing machine; The power supply switch voltage-stabilizing circuit links to each other with differential signal processing unit, programmable logic device (PLD), single-chip microcomputer, expansion interface circuit, data buffer storage unit and communication interface circuit respectively.
2. a kind of Endat data acquisition card based on the threeway mode as claimed in claim 1, it is characterized in that: described programmable logic device (PLD) internal configurations generates inner decoding module, inner sampling clock generation module and three modules of single chip communication interface; The inner decoding module according to the time ordered pair Endat signal decode, and store decoded data into data buffer storage unit; Inner sampling clock generation module is according to the sample frequency of computer installation, carry out frequency division by the work clock to programmable logic device (PLD) and obtain required inner sampling clock, at the sampling clock rising edge, deliver to the single chip communication interface after latest data in the data buffer storage unit read, then send interruption to single-chip microcomputer, wait for that single-chip microcomputer reads data in the computing machine.
3. a kind of Endat data acquisition card based on the threeway mode as claimed in claim 2, it is characterized in that: in decode phase, the length that the inner decoding module at first configures for the receiving mode instruction is the shift register of 6Bit, then judges the Endat version according to the mode instruction that receives; Then receive initialization, configured length is the register of 56Bit, front 48Bit storage Endat positional value, and rear 8Bit storage CRC check value, at decode phase, the displacement receive data stores in the data buffer storage unit after CRC check is correct.
4. a kind of Endat data acquisition card based on the threeway mode as claimed in claim 1, it is characterized in that: described expansion interface circuit intercoms mutually with programmable logic device (PLD), the inner sampling clock that produces of programmable logic device (PLD) is drawn, and expansion interface circuit also provides the external clock input port simultaneously.
5. a kind of Endat data acquisition card based on the threeway mode as claimed in claim 1, it is characterized in that: what described single-chip microcomputer adopted is the C8051F340 single-chip microcomputer, computing machine by communication interface circuit with parameter read-in in single-chip microcomputer, single-chip microcomputer arranges work according to start and stop, the transmission of data and the parameter of write parameters type completion system; In the transmission of data stage, the USB interface that data communication device is crossed in the communication interface circuit sends in the computing machine, usb communication cycle by computing machine send control information, single-chip microcomputer sends data and the computer receiving data three phases is finished.
6. a kind of Endat data acquisition card based on the threeway mode as claimed in claim 1, it is characterized in that: described differential signal turns the single-ended signal circuit and comprises the AM26LS32 chip, the Endat signal that the differential signal processing unit utilizes the AM26LS32 chip that the exit by three messengers is introduced capture card converts single-ended signal to by differential signal, then utilize the signal filtering treatment circuit successively single-ended signal to be carried out RC low-pass filtering treatment and waveform arrangement, make single-ended signal convert the LVTTL form to.
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Cited By (4)
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| CN104361299A (en) * | 2014-09-23 | 2015-02-18 | 广州日滨科技发展有限公司 | Security system, multilevel security controlling system and location information reading method thereof |
| CN105607570A (en) * | 2015-12-25 | 2016-05-25 | 清华大学 | Multi-channel signal acquisition system compatible with multiple protocols |
| CN109738907A (en) * | 2019-03-13 | 2019-05-10 | 武汉海达数云技术有限公司 | Laser waveform data acquisition device and method |
| CN111551376A (en) * | 2020-06-02 | 2020-08-18 | 中车青岛四方车辆研究所有限公司 | Data acquisition control unit based on rail transit test bench |
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| CN2757220Y (en) * | 2004-10-15 | 2006-02-08 | 重庆大学 | Multi path grating data transducer based on programmable logic device and USB interface |
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