CN103313099A - Data reception circuit, data reception apparatus and method, and information processing system - Google Patents
Data reception circuit, data reception apparatus and method, and information processing system Download PDFInfo
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- CN103313099A CN103313099A CN2013100659885A CN201310065988A CN103313099A CN 103313099 A CN103313099 A CN 103313099A CN 2013100659885 A CN2013100659885 A CN 2013100659885A CN 201310065988 A CN201310065988 A CN 201310065988A CN 103313099 A CN103313099 A CN 103313099A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
- G09G5/008—Clock recovery
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Abstract
Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.
Description
Technical field
The present invention relates to a kind of data receiver circuit.With particularly, the present invention relates to a kind of data receiver circuit, data sink, information processing system and data receive method that generates about clock.
Background technology
In recent years, developed the device that is used for voice data and video data are carried out multiplexed (becoming a kind of multiplex stream), in order to reduce the quantity that is used between a plurality of equipment, sending voice data and the necessary route of video data (transmit path).For example, will develop some according to the HDMI(high-definition media interface) standard (HDMI is registered trade mark, referring to " the high-definition media interface specification version 1.3a " in November 10 in 2006) sends the device of voice data and video data.
Send to relate to video data clock (video clock) according to the data of HDMI standard and synchronously send multiplex stream.The equipment (source device) that sends multiplex stream with audio data clock (audio clock) divided by predetermined value (N value) in order to obtain to be divided ratio (CTS value) between clock and the video clock, send afterwards the equipment (sink device) that these values (N value and CTS value) arrive the described multiplex stream of reception.
Sink device with video clock divided by received CTS value, thereby and the clock that is divided be multiply by N generate audio clock.
Summary of the invention
According to the correlation technique of summarizing above, can generate (regeneration) audio clock based on the video clock that is sent to sink device, N value and CTS value.
But, the PLL(phase-locked loop that N processes is multiply by in a kind of execution of specification requirement of summarizing of the above) circuit.The use of this PLL circuit can cause the increase of circuit scale and cause higher manufacturing cost.When generating audio clock, the scale that importantly reduces the circuit that is used for the audio clock generation also is convenient to the generation of clock thus.
The present invention be directed to that top situation is made and help can generation.
According to one embodiment of present invention, a kind of data receiver circuit and data receiving method are provided, described data receiver circuit comprises that clock generates piece, it is configured to divide the first clock based on clock information, described the first clock is the clock as the transmission stream of the target that sends video data between a plurality of devices, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of tentation data, and described clock generates piece and also exports the clock that is divided as described second clock.Acting as by dividing the first clock based on described clock information of this embodiment generates second clock.
A kind of version as top general introduction embodiment, described transmission stream has at this by multiplexed described video data, described tentation data and described clock information, be sent out, described the first clock generates by amplifying the predetermined ratio factor for the clock that transmits described video data in for the device that sends described transmission stream described transmission stream and described the first clock synchronous.Described data receiver circuit also comprises multiplexed, and it is configured to carry out multiplexed to being sent to the transmission stream in the described video data, described tentation data and described clock information.Described clock generates piece by being divided described the first clock by multiplexed clock information and generate described second clock based on described.This version act as based on be used for transmitting the clock of the transmission stream that the clock synchronous ground of video data is sent out and from described transmission is flowed, to be generated second clock by the clock information of demultiplexing at described device.
As the another kind of version of above-described embodiment, described the first clock is for using than the clock that sends described transmission stream at the path transmit path still less that transmits described video data for the described device that sends described transmission stream.The acting as based on described clock information and use the clock of the described transmission stream that sends than the path transmit path still less that transmits described video data at the described device that is used for sending described transmission stream and generate second clock of this version.
As the another kind of version of above-described embodiment, described the first clock is to use single transmit path to send the clock of described transmission stream.The clock that act as the described transmission stream that sends based on described clock information and with single transmit path of this version and generate second clock.
As the another kind of version of above-described embodiment, the described predetermined ratio factor be for so that the amount of jitter that in described second clock, comprises less than as with reference to the scheduled volume of value.Acting as based on described clock information and with so that the clock of the transmission stream that amount of jitter sends less than the clock of predetermined reference amount and generate second clock of this version.
Another kind of version as above-described embodiment, described clock information comprises CTS value and N value, the clock quantity of described the first clock that described CTS value indication is corresponding with a clock cycle of the described second clock that is divided into predetermined space, the described predetermined space of described N value indication.Described clock generates piece and generates described second clock by dividing described the first clock based on the ratio between described CTS value and the described N value.Acting as by dividing tranmitting data register based on the ratio between described CTS value and the described N value of this version generates second clock.
As the another kind of version of above-described embodiment, described tentation data is voice data; And described second clock is the master clock of described voice data.This version act as the master clock that becomes voice data by dividing tranmitting data register next life.
As the another kind of version of above-described embodiment, the frequency of described the first clock is at least 20 times of frequency of the described master clock of described audio frequency.This version act as the audio stream that generation can be replicated.
According to one embodiment of present invention, a kind of data sink is provided, comprise: the first clock generates piece, be configured to generate the first clock as the clock of the transmission stream that is sent out via the single-pathway from the dispensing device that is used for sending video data to described data sink, described the first clock is based on the described transmission stream that has been sent out and generate; Multiplexed, be configured to carry out multiplexedly to being sent to described transmission stream, tentation data and clock information in the described video data, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of described tentation data; And clock generation piece, being configured to based on described the first clock that is generated of being divided by multiplexed clock information, the clock that afterwards output is divided is as described second clock.Acting as by dividing the first clock based on described clock information of this embodiment generates second clock.
According to one embodiment of present invention, a kind of information processing system is provided, comprise: data sending device, be configured to generated clock information before transmission has by the transmission of multiplexed video data, tentation data and clock information stream, this clock information has been indicated the period-luminosity relation between the first clock and the second clock, this first clock is that second clock is as the clock of tentation data as the clock of the transmission stream of the target that sends video data between a plurality of devices; And data sink, being configured to receive the described transmission stream that has been sent out and demultiplexing is flowed in received transmission is described video data, described tentation data and described clock information, and described data sink is also divided described the first clock in order to generate described second clock based on described clock information.Acting as by dividing the first clock based on described clock information of this embodiment generates second clock.
Another kind of version as the embodiment above tight, described data sending device calculate scale factor so that so that the amount of jitter that in the described second clock that is generated by described data sink, comprises less than as the scheduled volume with reference to value, described data sending device also generate described the first clock by the clock amplification predetermined ratio factor that will be used for the described video data of transmission in described data sending device.This embodiment act as so that data sink generates the second clock that comprises the amount of jitter less than predetermined reference amount.
As the another kind of version of the embodiment above tight, the mode of proportional rising generates described transmission stream to described data sending device along with the increase in the described scale factor with the ratio (rate) of the blanking interval that comprises in described transmission stream.This embodiment act as so that the first clock rises and descends according to increase and the reduction of the size (size) of the blanking interval that comprises in described transmission stream.
Therefore the invention provides the main effect that makes things convenient for generated clock by what top general introduction was implemented.
Description of drawings
Fig. 1 is that demonstration is as the schematic diagram of the exemplary functions structure of the data Transmission system of the first embodiment of the present invention;
Fig. 2 shows that the audio clock of the first embodiment generates the schematic diagram of the exemplary functions structure of piece;
Fig. 3 is that the audio clock that schematically shows the first embodiment generates the sequential chart how piece generates audio clock;
Fig. 4 A and 4B show that respectively the audio clock of another sink device generates the schematic diagram of the exemplary audio clock generation piece of piece (audio clock generative circuit) and the first embodiment;
Fig. 5 is that the audio clock that shows the first embodiment generates the flow chart that piece generates the canonical process of audio clock;
Fig. 6 is that demonstration is as the schematic diagram of the exemplary functions structure of the data Transmission system of second embodiment of the invention;
Fig. 7 A and 7B are respectively the exemplary data structure that shows the transmission stream of the second embodiment use;
Fig. 8 shows that the source device of the second embodiment sends the flow chart of the canonical process of described transmission stream; And
Fig. 9 is the flow chart that the tranmitting data register speed of demonstration the second embodiment is determined the canonical process of the tranmitting data register set handling that piece is carried out.
Embodiment
The following describes be used to implementing several preferred embodiment of the present invention (following suitably referred to as embodiment).This specification will describe under several titles below:
1. the first embodiment (data transfer control: wherein do not adopt PLL to generate the example of audio clock)
2. the second embodiment (data transfer control: the example of the shake of control in the audio clock)
＜1. the first embodiment 〉
[the exemplary functions structure of data Transmission system]
Fig. 1 is that demonstration is as the schematic diagram of the exemplary functions structure of the data Transmission system 10 of the first embodiment of the present invention.
In the data transmitting equipment (source device 100) and data receiver (sink device 200) of data Transmission system 10, in Fig. 1, only shown the structure of the function that is used for the transmission data, and from this figure, omitted remaining structure.
Source device 100 is multiplexed as voice data and video data data flow (multiplex stream) and these data is sent to sink device 200.Source device 100 comprise the N value determine piece 110, tranmitting data register generate piece (PLL: phase-locked loop) 120 and N divide (division) piece 130.Source device 100 also comprises CTS(cycle (cycle) timestamp) value generates piece 140, stream multiplexed 150 and differential (differential) driver 160.
The value (N value) that the audio clock that the definite piece 110 of N value generates for source device 100 is identified for dividing master clock.In order to explain, the master clock that the first embodiment hypothesis is used for audio clock is 128 times (128 * fs) of sample frequency (fs).The N value determines that piece 110 usually can be take according to the HDMI(high-definition media interface) standard determines the identical mode of N value as the division of audio clock and determines this N value.For example, the N value determines that piece 110 selects based on concerning that predetermined value is as the N value between audio clock speed and the tranmitting data register speed.The N value determines that the N value that piece 110 will be determined like this is supplied to N divided block 130 and flows multiplexed 150.
N divided block 130 is based on determining that from the N value N value that piece 110 supplies come will be for the master clock (being designated hereinafter simply as audio clock) of audio clock divided by described N value.N divided block 130 will be supplied to the CTS value to generate piece 140 by the clock (that is, the 1/N clock of audio clock) that this division generates.
Tranmitting data register generates piece (PLL) 120 and generates for flowing the clock (tranmitting data register) that sends to sink device 200 from source device 100 based on video clock.For example, tranmitting data register generation piece 120 can adopt common PLL to realize.Tranmitting data register generates piece 120 can be with the speed generated clock of 30 times high of the speed of for example video clock, and the clock (tranmitting data register) that generates is fed to CTS value generates piece 140 and flow multiplexed 150.
The CTS value generates piece 140 based on generating the CTS value from the clock (1/N audio clock) of 130 feedings of N divided block and from the tranmitting data register that tranmitting data register generates piece (PLL) 120.In context, the CTS value is by using video clock to be counted the value that obtains the cycle of 1/N audio clock.
That is, the relation between audio clock (S), tranmitting data register (T) and the CTS value (CTS) limits by expression (1):
S=T×N/CTS（1）
The N value of the first embodiment is assumed to be with the CTS value that those values with the HDMI standard are identical basically.The CTS value generates piece 140 the CTS value that generates is supplied to multiplexed 150 of stream.
Flow to generate to send by the data that will send to sink device 200 are aligned (align) for multiplexed 150 and flow.For convenience of explanation, the first embodiment supposes that video flowing (video data stream), audio stream (audio data stream), blanking (blank) data, N value and the CTS value via holding wire 159 feedings of supplying via holding wire 158 are multiplexed as transmission stream.
Although the data structure of multiplexed data (sending stream) can imagine it is diversified, any this data structure can be applied to the first embodiment in practice.For example, but typical application data structure for a kind of like this, wherein every frame is provided for admitting the blanking interval (interval) of (accommodate) interpolation data, as at HDMI standard or SDI(serial digital interface) in substandard data structure.Adopt this mode, flow multiplexed 150 (packetized) voice data, N value, the CTS value with subpackage and be multiplexed to the blanking interval that sends stream.Flow and use for multiplexed 150 tranmitting data register as carrier the transmission stream that generates to be fed to differential drive 160.
Although explained in conjunction with the first embodiment that at this so that the example that the single transmit path of data between equipment sends, this is not limitation of the invention.Sending stream only must synchronously be sent out with the high speed tranmitting data register.That is to say, use than being used for and transmit the transmit path (transmit path of the first embodiment) that the path of video data lacks when being sent out at described device when sending stream, aspect the speed of described transmission also so that tranmitting data register higher.For example, process if video flowing adopted the 24-bit parallel to transmit (adopting 24 paths) in source device 100, the speed that then is used for the tranmitting data register that a paths sends is at least 24 times of speed of video clock.Send in the situation that set up the 4-path, the speed of tranmitting data register is up at least 6 times of transmission speed.
Sink device 200 is designed to receive from the next transmission stream of source device 100 supplies.Therefore, sink device 200 comprises that differential receiver 210, tranmitting data register reconstituting piece (PLL) 220, stream demultiplexing piece 230 and video clock generate piece (PLL) 240.Sink device 200 comprises that also video flowing generates piece 250, audio stream generates piece 270 and audio clock generates piece 400.
Based on the transmission stream that comes from differential receiver 210 supplies, tranmitting data register reconstituting piece (PLL) 220 regeneration are supplied the clock (tranmitting data register) of the transmission stream that comes.That is to say, the frequency of the clock of tranmitting data register reconstituting piece (PLL) 220 regeneration is identical with the frequency of the clock (tranmitting data register) that is generated by tranmitting data register generation piece (PLL) 120.For example, tranmitting data register reconstituting piece (PLL) 220 can adopt common PLL to realize.Tranmitting data register reconstituting piece (PLL) 220 is fed to the tranmitting data register of regenerating stream demultiplexing piece 230, is fed to video clock generation piece (PLL) 240 and is fed to audio clock via holding wire 221 and generates piece 400.Along band, tranmitting data register reconstituting piece (PLL) 220 is the example that the first clock described in attached claims generates piece.
It is initial data (video data, voice data, N value and CTS value) that stream demultiplexing piece 230 will send the stream demultiplexing.Stream demultiplexing piece 230 will demultiplexing goes out from send stream video data be fed to video flowing and generate piece 250 and voice data that will demultiplexing goes out from send stream and be fed to audio stream and generate piece 270.And N value and CTS value that stream demultiplexing piece 230 will demultiplexing goes out from send stream are fed to audio clock generation piece 400 via holding wire 490.
Video clock generates piece (PLL) 240 based on the tranmitting data register generating video clock that comes from tranmitting data register reconstituting piece (PLL) 220 supplies.For example, video clock generation piece (PLL) 240 can adopt common PLL to realize.Video clock generates that piece (PLL) 240 is fed to the video clock that generates that video flowing generates piece 250 and at the circuit (not shown) of sink device 200 interior use video clocks.
Video flowing generates piece 250 based on supply the video data that comes and the video clock generating video stream that generates piece (PLL) 240 feedings from video clock from stream demultiplexing piece 230.The video flowing that video flowing generates piece 250 generations is supplied to the circuit that uses video flowing in sink device 200.
Audio clock generates piece 400 and generates audio clock based on the tranmitting data register that comes from tranmitting data register reconstituting piece (PLL) 220 supplies with from N value and the CTS value that flows 230 feedings of demultiplexing piece.Audio clock generates piece 400 by generating audio clock based on N value and CTS value division tranmitting data register.It should be noted, audio clock generates piece 400 and does not use PLL to realize.Audio clock further is not discussed now immediately to be generated piece 400 but is explained in detail with reference to Fig. 2 subsequently.Audio clock generates piece 400 audio clock that generates is fed to the circuit that audio stream generates piece 270 and use audio clock in sink device 200.Along band, it is examples that the clock described in attached claims generates piece that audio clock generates piece 400.
Audio stream generation piece 270 is based on supply the audio stream that comes and the audio clock generation audio stream that generates piece 400 feedings from audio clock from stream demultiplexing piece 230.The audio stream that audio stream generates piece 270 generations is supplied to the circuit that uses audio stream in sink device 200.
Generate piece 400 below with reference to Fig. 2 interpret audio clock
[audio clock generates the exemplary functions structure of piece]
Fig. 2 shows that the audio clock of first embodiment of the invention generates the schematic diagram of the exemplary functions structure of piece 400.
Audio clock generates piece 400 and is designed to generate audio clock.Therefore, audio clock generation piece 400 comprises division calculating section 500 and divides part 420.
Divide calculating section 500 based on via the holding wire 491 of holding wire 490(via the part that consists of holding wire 490) the CTS value come from 230 supplies of stream demultiplexing piece and equally via the holding wire 492 of holding wire 490(via the part that consists of holding wire 490) indicate the information (this information below will be referred to as clock interval) of the tranmitting data register quantity corresponding with a clock cycle of audio clock from the N value calculating of piece 230 feedings.For example be according to the pulse of the clock quantity indicative audio clock of the tranmitting data register value regularly that rises by dividing clock interval that calculating section 500 calculates gained.At this example that calculates this clock interval will be discussed, but explain this example with reference to Fig. 3 in the back.Dividing calculating section 500 will indicate the information (clock interval information) of the clock interval that calculates to be supplied to division part 420.
Divide part 420 based on dividing from the clock interval information of dividing calculating section 500 feedings from the next tranmitting data register of tranmitting data register reconstituting piece (PLL) 220 supplies.Dividing part 420 promotes the audio clock pulse by the interval with the clock quantity of the indicated tranmitting data register of clock interval information and becomes audio clock next life.
The division of normally how being undertaken by division calculating section 500 and division part 420 below with reference to Fig. 3 interpret audio clock generates, and supposes and will carry out this division with non-integer.
[using non-integral common division]
Fig. 3 is that the audio clock that schematically shows first embodiment of the invention generates the sequential chart how piece 400 generates audio clock.
Fig. 3 has shown the audio clock that three signals (tranmitting data register, N value and CTS value) that are supplied to audio clock and generate piece 400, the clock interval information of dividing calculating section 500 generations and division part 420 generate.In description subsequently, send out in connection with constantly " 0 " and arrive " 22 " explanation tranmitting data register.
Or in Fig. 3, for task of explanation, default " 3 " is set to described N value.For task of explanation, also suppose in the moment " 1 " supply CTS value " 10 " and in constantly " 11 " feeding " CTS value ".
When being supplied in " 1 " stylish CTS value constantly when dividing calculating section 500, divide calculating section 500 based on described N value and the next described clock interval of CTS value calculating of new supply.For example, dividing calculating section 500 can use following expression formula (2) to calculate described clock interval:
A/N=q remainder r (2)
Wherein reference character A representative will be by adding the value that the CTS value obtains from the remainder of last calculating clock interval; Reference character N represents the N value; Reference character q represents the merchant (quotient) of left side division, and reference character r represents the remainder of left side division.Merchant q is the value that is fed to the clock interval information of dividing part 420 from dividing calculating section 500.
Explain now above-mentioned expression formula (2).That dividing the calculating section 500 CTS value value of being set to A(remainders is 0 when being supplied new CTS value) and use expression formula (2) to calculate clock interval.That is to say, in constantly " 1 ", calculate the merchant for " 3 " remainder be " 1 " (10/3=3remainder1).And divide calculating section 500 and determine that merchant q " 3 " is clock interval and the clock interval information that is spaced apart " 3 " to division part 420 supply telltable clocks.Divide calculating section 500 and wait for that subsequently the audio frequency clock pulse rises.
In constantly " 3 " afterwards, the audio clock pulse is risen.This has generated a clock cycle of audio clock.
In the moment " 4 ", divide calculating section 500 at inferior calculating clock interval subsequently.For this calculating, value A is set to by being added to from the remainder in the moment " 1 " the upper value " 11 " that obtains of CTS value " 10 ".As a result, locate in the moment " 4 ", merchant q is calculated as " 3 " and remainder r is " 2 ".Divide calculating section 500 and supply the clock interval information that telltable clocks are spaced apart " 3 " to dividing part 420
In the moment " 6 ", another audio clock pulse is risen subsequently.
Then in the moment " 7 ", divide calculating section 500 and again calculate clock interval.For current calculating, value A is set to by being added to from the remainder in the moment " 4 " the upper value " 11 " that obtains of CTS value " 10 ".As a result, in constantly " 7 ", merchant q is calculated as " 4 " and remainder is " 0 ".Divide calculating section 500 and supply the clock interval information that telltable clocks are spaced apart " 4 " to dividing part 420.
In the moment " 10 ", another audio clock pulse is risen in dividing part 420 afterwards.
Then in the moment " 11 ", divide calculating section 500 and again calculate clock interval.Because remainder r becomes " 0 " in the calculating in the moment " 7 ", therefore divide calculating section 500 and upgrade the CTS values to be used for updating value A.In the sequential chart of Fig. 3, be presented at the moment " 1 " CTS value and be updated to " 11 ", will be worth " 11 " value of being set to A so that divide calculating section 500.As a result, constantly " 11 " locate to calculate merchant q for " 3 " remainder r be " 2 " (11/3=3remainder2), and clock interval is set to " 3 ".
In the moment " 13 ", another audio clock pulse is risen subsequently.
Then in constantly " 14 ", calculate intermediate value " the 13(11+2) " value of being set to A at clock interval.Merchant q be calculated as " 4 " and remainder r for " 1 " (13/3=4remainder1), and clock interval is set to " 4 ".
In the moment " 17 ", another audio clock pulse is risen subsequently.
Then in constantly " 18 ", calculate intermediate value " the 12(11+1) " value of being set to A at clock interval.Merchant q be calculated as " 4 " and remainder r for " 0 " (12/3=4remainder0), and clock interval is set to " 4 ".
When CTS value and N value are used to calculate clock interval as to corresponding to the tranmitting data register quantity of clock cycle of the audio clock of explaining above the time, can not need to generate (regeneration) audio clock with PLL.
For the situation among Fig. 3, suppose that division ratio is non-integer.If division ratio is non-integer, then clock interval can fluctuate (for example from " 3 " to " 4 ") and have this to produce shake the clock that generates.On the other hand, if division ratio is integer, then can not produce shake (jitter).
The below generates piece 400 audio clock that generates and the explanation of shaking Relations Among to audio clock.Generate piece 140 divided by N(referring to the N divided block 130 among Fig. 1 and CTS value at audio clock) the interval generate the CTS value, and the CTS value changes to another from a clock cycle.When therefore the CTS value changes to another from a clock cycle, during the audio clock that is generated piece 400 generations by audio clock, be difficult to division ratio is fixed as an integer.Because division ratio is non-integer, inevitable when in audio clock, including shake.But, all unite can be by relating to clock source clock (tranmitting data register) and the division of the frequency ratio that is raised between the clock (audio clock) that generates minimized.
The below is to the frequency of clock source and the explanation by the relation between the shake of the clock that divide to generate.
If suppose to generate according to the clock source of 100MHz the clock (division by about 1/10) of 10MHz, because the variation of the frequency that the displacement of a clock cycle in the clock interval causes is as follows:
When clock was spaced apart " 9 ", frequency change was 11.111...MHz(100/9);
When clock was spaced apart " 10 ", frequency change was 10.000MHz(100/10); And
When clock was spaced apart " 11 ", frequency change was 9.090...MHz(100/11).As mentioned above, if generate the clock of 10MHz according to the clock source of 100MHz since the frequency that the displacement of a clock cycle in the clock interval causes be changed to about 1MHz.That is to say, when the clock source according to 100MHz generates the clock of 10MHz, because the resolution (precision) that non-integer is divided is approximately 1MHz.
In another example, if generate the clock of 10MHz according to the clock source of 1000MHz, because the variation of the frequency that the displacement of a clock cycle in the clock interval causes is as follows:
When clock was spaced apart " 99 ", frequency change was 10.101...MHz(1000/99);
When clock was spaced apart " 100 ", frequency change was 10.000MHz(1000/100); And
When clock was spaced apart " 101 ", frequency change was 9.901...MHz(000/101).As mentioned above, if generate the clock of 10MHz according to the clock source of 1000MHz since the frequency that the displacement of a clock cycle in the clock interval causes be changed to about 0.1MHz.That is to say, when generating the clock of 10MHz according to the clock source of 1000MHz, because the resolution (precision) that non-integer is divided is approximately 0.1MH, this is that clock source is 10 times high of precision of 100MHz.
By top apparent, the frequency ratio between the clock of clock source (tranmitting data register) and the clock (audio clock) that generates is higher, and it is less that amount of jitter just becomes.
For example, be based on 1Gbps(1GHz if frequency is 128 times of high clocks of the sample frequency of 96kHz) the hypothesis that is sent out of speed and will generate, frequency ratio is 1,000 so, 000kHz:12,288(96 * 128) kHz.That is to say, use about 83 to 1 frequency ratio to carry out described division.Suppose that the shake of audio clock tolerance is up to 5 percentages (that is, clock has the frequency in positive and negative 5 percentages of target frequency).(5 percentage is the permissible limit of shake under SPDIF standard (IEC60958-1)).Because up to the frequency ratio of the shake of 5 percentages 20 to 1, so very narrow just having dropped in the described permissible limit of division of using 83 to 1 frequency ratio.
In the data Transmission system 10 as the first embodiment of the present invention, use differential wave to transmit data at single-pathway, so that data are finished under being sent at a high speed.That is to say, in the data Transmission system 10 of the first embodiment of the present invention, provide high-frequency as the tranmitting data register of clock source so that audio clock generate piece 400 can be in the situation that do not use PLL to generate attainable audio clock
[typical effect]
Fig. 4 A and 4B show that the exemplary audio clock of the first embodiment of the present invention generates the schematic diagram of the audio clock generation piece (audio clock generative circuit 800) of piece 400 and another sink device;
Fig. 4 A has shown the exemplary audio clock forming circuit 800 of another sink device.This audio clock generative circuit 800 comprises that CTS divides device 810, phase comparator 820, low pass filter 830, switch 840, the first voltage controlled oscillator 851 to the 3rd voltage controlled oscillators 853 and N and divides device 860.
To further not discuss in detail and consist of the PLL circuit functional structure of (comprising that phase comparator 820, low pass filter 830, switch 840, the first voltage controlled oscillator to the three voltage controlled oscillator 851-853 and N divide device 860).
If adopt the PLL circuit evolving audio clock shown in Fig. 4 A, need multiple pressure controlled oscillator (VCO).This requirement causes enlarging the scale of circuit.Also be necessary to regulate voltage controlled oscillator in the circuit fabrication stage.These factors probably combine and are lifted at cost in the situation of using the PLL circuit to consist of audio clock generative circuit 800.
Fig. 4 B has shown that the audio clock of first embodiment of the invention generates piece 400.It is identical with among Fig. 2 that audio clock among Fig. 4 B generates piece 400, so will no longer set forth.
Shown in Fig. 4 B, the first embodiment of the present invention is not in the situation that use PLL to generate audio clock.Compare with the situation of using the PLL circuit, the first embodiment is so that the circuit scale reduction.Because circuit scale reduces, therefore can reduce power consumption.And owing to not needing to regulate voltage controlled oscillator (VCO), therefore can produce described circuit with lower cost.Because do not need to carry out the work to this adjusting of each product, so cost is further reduced and is also reduced the variable of aspect of performance
[audio clock generates the typical operation of piece]
Explain what how the audio clock generation piece 400 of the first embodiment normally moved referring to accompanying drawing.
Fig. 5 shows that the audio clock of the first embodiment generates the flow chart of the canonical process of piece 400 regeneration (generation) audio clocks;
At first, determine whether to begin audio clock regeneration (step S901).If determine not begin the reproducing audio clock, the process that audio clock generates is in standby (hold).For example, be included in the received transmission stream if receive to send stream and detect voice data, the controll block (not shown) of sink device 200 is determined the regeneration of beginning audio clock.
If determine beginning audio clock regeneration (step S901), audio clock generates piece 400 and obtains by the stream demultiplexing piece 230 N value (step S902) that demultiplexing goes out from send stream.Go out the CTS value from sending the stream demultiplexing subsequently, and this CTS value is supplied to audio clock generation piece 400.Audio clock generates piece 400 and obtains by this way described CTS value (step S903).
Based on the clock interval that calculates according to N value and CTS value, audio clock generates piece 400 and divides tranmitting data registers so that reproducing audio clock (step S904).Along band, step S904 is the example that the clock described in attached claims generates step.
Then audio clock generation piece 400 determines whether the regeneration of (step S905) audio clocks stops within the period (this period is corresponding to a clock cycle of 1/N audio clock) indicated by the CTS value that is used for the calculating clock interval in step S904.Within the period indicated by CTS value, still will not be terminated (step S905) if determine the regeneration of audio clock, and just again arrive step S904 and continue the regeneration of audio clock.
On the other hand, if within by the period of CTS value indication, stop the regeneration (step S905) of audio clock, then determine whether to stop audio clock regeneration (step S906).If determine to stop the regeneration (for example, when the transmission that sends stream reaches the end) of audio clock, then so that audio clock regeneration processing end.
According to the first embodiment, as explained above, can generate audio clock by using N value and CTS value to divide the high frequency tranmitting data register.
＜2. the second embodiment 〉
For the first embodiment, the tranmitting data register of supposing tranmitting data register generation piece (PLL) 120 generations is that 30 times of video clock are fast.This can provide blanking interval, its size for every frame of the data structure in sending stream with the view data in the same size of every frame.
But, because determine tranmitting data register when considering the speed of video clock, so the relation between video clock speed and the audio clock speed has been determined to be generated by audio clock the precision of the clock of piece 400 generations.That is to say, if video clock is slow, that the tranmitting data register that generates is also slow.Explain with reference to Fig. 3 as top, this can be so that deterioration in accuracy when generating audio clock.
For example, in the situation that frame (image) size is smaller or frame rate is lower, the amount of the video data in the time per unit is just smaller.This causes slower video clock.Simultaneously because the increase of voice data and video data and reduce uncorrelated, therefore, though video clock become slower in voice data also keep very fast.This causes the ratio of the reduction between tranmitting data register (video clock 30 times) and the voice data.Therefore, the deterioration in accuracy when generating audio clock.Therefore, adopt the first embodiment of the present invention, do not have the video data volume of unit interval less, the precision when generating audio clock just becomes lower.
Consider above-mentioned situation, second embodiment of the invention is for the size of adjusting the blanking interval in the transmission stream that is generated by source device in order to strengthen the precision of the audio clock that will be generated by sink device.The below explains the example of how to wake up with a start this adjustment with reference to Fig. 6-9.
[the exemplary functions structure of data Transmission system]
Fig. 6 is that demonstration is as the schematic diagram of the exemplary functions structure of the data Transmission system 600 of second embodiment of the invention.
The N value determines that piece 110, N divided block 130, CTS value generate piece 140, stream multiplexed 150 and differential drive 160 structure substantially the same with having of the counterpart shown in Fig. 1, therefore will not be further expalined.And it is identical with tranmitting data register generation piece (PLL) 120 shown in Fig. 1 that tranmitting data register generates piece (PLL) 620, therefore will not set forth at this, and difference is that piece 620 can change the scale factor of the relative video clock of tranmitting data register.
Tolerable wobble information supply piece 640 determines that to tranmitting data register speed piece 630 supply indications will be generated by sink device 650 information (tolerable wobble information) of the upper limit (tolerance limit) of the shake that comprises in the audio clock of (regeneration).Adopt various ways to express although can imagine the degree of shake, the second embodiment hypothesis employing percentage (%) of all uniting is expressed shake, and is the same with situation in the first embodiment of the invention.For the second embodiment of the present invention, the same with the situation of the first embodiment for task of explanation, suppose the admissible limits of 5 percentages for all uniting, and the value of 5 percentages is set to wobble information.
Although second embodiment of the invention hypothesis tolerable wobble information is fixed value, but this information can arrange for the input of for example audio quality changeably based on the user, it will also be appreciated that, the tolerable wobble information is according to arranging about himself information (for example performance of the audio-frequency function of sink device 650) of coming from sink device 650 supply.
Tranmitting data register speed determines that piece 630 is designed to determine based on tolerable wobble information, video clock and audio clock the speed of tranmitting data register.Tranmitting data register speed determines that piece 630 generates the mode that the shake (jigger) in the audio clock that piece 400 generated drops in the indicated limit of tolerable wobble information (5%) with the audio clock of sink device 650 and determines tranmitting data register speed.
Explained later is determined piece 630 determined tranmitting data register speed by tranmitting data register speed.Suppose that related blanking interval has normal size (that is, minimum blanking interval).Also suppose the size of the blanking interval that this standard blanking interval size (normal size) provides for first embodiment of the invention.That is to say, the clock of the transmission stream that generates when the blanking interval of normal size is provided is that 30 times of video clock are fast.
Tranmitting data register speed determines that piece 630 at first calculates the speed by the tranmitting data register that video clock 30 times of factors of amplification (the standard proportional factor) are generated.Based on speed and the audio clock of the tranmitting data register that calculates, tranmitting data register speed is determined the amount (estimation amount of jitter) of the shake that piece 630 estimations generate when audio clock generates piece 400 reproducing audio clock.If estimate amount of jitter and be equal to or less than described tolerable amount of jitter by the described estimation amount of jitter of relatively demonstration between the indicated amount of jitter of tolerable wobble information (tolerable amount of jitter), then determine by 30 times of factors of video clock amplification are generated tranmitting data register.Another aspect is if described estimation amount of jitter is greater than described tolerable amount of jitter, then to estimate that amount of jitter falls into the speed that mode within the tolerable amount of jitter is calculated tranmitting data register.Then determine the scale factor that when generating tranmitting data register, uses, so that the tranmitting data register speed that can obtain to calculate at least.Then tranmitting data register speed determines that piece 630 will generate piece (PLL) 620 to tranmitting data register about the information supply of determined scale factor, so that piece 620 can be determined this scale factor, in order to amplify clock by this scale factor.
Determined scale factor is supplied to multiplexed 150 of stream, and this scale factor is multiplexed into and sends stream and be fed to sink device 650 thus.In sink device 650, determined scale factor is forwarded to video clock from stream demultiplexing piece 230 via holding wire 669 and generates piece (PLL) 660.Scale factor is used as the information (that is, the ratio of video clock and tranmitting data register) for the regeneration video clock.
Tranmitting data register speed determines that piece 630 is to multiplexed 150 information (tranmitting data register speed) of supplying about the blanking interval size of setting by determined scale factor of stream.Comprise the transmission stream with this big or small blanking interval and flow to generate for multiplexed 150.
[sending the exemplary data structure of stream]
Fig. 7 A and 7B are the schematic diagrames of the exemplary data structure of the transmission stream that shows that second embodiment of the invention is used.
In fact Fig. 7 A has shown in tranmitting data register speed and has determined that piece 630 determines that described estimation amount of jitter are equal to or less than described tolerable amount of jitter in order to send the data structure of the single frames in flowing when being generated as the tranmitting data register of 30 times fast (standard proportional factors) of video clock.Shown in Fig. 7 A, a frame sends stream and is made of blanking interval (horizontal blanking interval 681 and vertical blanking interval 682) and single frames video data (effective video zone 683).
Fig. 7 A has schematically shown the size (data volume) of single frames, and wherein amount of jitter drops within the tolerable amount of jitter when generating audio clock according to tranmitting data register.If the summation in horizontal blanking interval 681, vertical blanking interval 682 and effective video zone 683 estimates then that less than the represented size of arrow 684 amount of jitter is greater than described tolerable amount of jitter.
In fact Fig. 7 B has shown in tranmitting data register speed and has determined that piece 630 is determined described estimation amount of jitter greater than described tolerable amount of jitter and so that amount of jitter drops on the data structure that sends the single frames in the stream when mode within the tolerable amount of jitter arranges the scale factor of tranmitting data register.In Fig. 7 B, with the same at Fig. 7 A, blanking interval (horizontal blanking interval 691 and vertical blanking interval 692) and single frames video data (effective video zone 693) have been shown.The size (data volume) of arrow 694 expression single frames, the amount of jitter that wherein produces when generating audio clock according to tranmitting data register drops within the tolerable amount of jitter.The represented size of arrow 694 is greater than the represented size of the arrow 684 among (being wider than) Fig. 7 A.In the situation that Fig. 7 B, if the summation in horizontal blanking interval 681, vertical blanking interval 682 and effective video zone 683 estimates then that less than the represented data volume of arrow 694 amount of jitter is greater than the tolerable amount of jitter.
For example, if determining piece 630, tranmitting data register speed determines to estimate amount of jitter greater than the tolerable amount of jitter, then so that the estimation amount of jitter is equal to or less than the scale factor that the mode of tolerable amount of jitter is calculated tranmitting data register.Then adjust the size of blanking interval of every frame in order to use the tranmitting data register calculate to send data, shown in Fig. 7 B.That is to say, if determine to estimate amount of jitter greater than the tolerable amount of jitter, then form data structure so that the size of the blanking interval of every frame greater than the size when the application standard scale factor in fact.
As explained above, when tranmitting data register speed is determined piece 630 described estimation amount of jitter greater than described tolerable amount of jitter, then synchronously generate the size that the mode that sends stream is regulated blanking interval to fall into tranmitting data register within the tolerable amount of jitter with its estimation amount of jitter.Because the size in effective video zone remains unchanged, so tranmitting data register faster (scale factor that is used for amplification is larger), the ratio of the blanking interval of every frame (rate) is just higher.
[typical operation of source device when sending the transmission of stream]
How the source device 610 of explaining with reference to the accompanying drawings second embodiment of the invention operates when the transmission that sends stream usually.
Fig. 8 shows that the source device 610 of second embodiment of the invention sends the flow chart of the canonical process of described transmission stream.
At first, determine whether to begin to send the transmission (step S911) of stream.If determine not begin to send the transmission of stream, the then transmission that begins to send stream to be determined such as source device 610.
If determine to begin to send the transmission (step S911) of stream, then tranmitting data register speed is determined piece 630 enforcement tranmitting data register set handlings (step S920), wherein determines the speed (scale factor of video clock) of tranmitting data register.Tranmitting data register set handling (step S920) will be set forth referring to Fig. 9 in the back, therefore not explain at this.
When the speed of tranmitting data register was set, tranmitting data register generated piece (PLL) 620 and generates tranmitting data register (step S912) with set speed.Send stream and synchronously be sent out (step S913) with the tranmitting data register that generates like this.
Then determine whether to stop sending the transmission (step S914) of stream.If determine to stop send the transmission (for example, when no longer including data and need to send) of stream, the processing of the transmission of the transmission stream that then is finishes.
If determine not stop sending the transmission (step S914) of stream, then tranmitting data register speed determines that piece 630 determines whether to change tranmitting data register speed (step S915).If determine to need to change tranmitting data register speed (that is, when audio clock or video clock need to change its speed at least) at step S915, then again arrive step S920 and tranmitting data register speed is set again.
If determine not need to change tranmitting data register speed (for example audio clock or video clock do not need to change its speed) at step S915, then again reach step S912.
Fig. 9 is the flow chart that the tranmitting data register speed of demonstration second embodiment of the invention is determined the canonical process of the tranmitting data register set handling (step S920) that piece 630 is carried out.
Tranmitting data register speed determines that piece 630 at first obtains the tolerable wobble information (step S921) of coming from 640 supplies of tolerable wobble information supply piece.Then obtain afterwards video clock speed (step S923) in the speed (step S922) that obtains audio clock.Afterwards, calculate when increasing the blanking interval of normal size the in fact speed of tranmitting data register (default speed) (30 times tranmitting data register of video clock) (step S924).
Based on the default speed of calculating and audio clock speed, tranmitting data register speed determines that piece 630 calculates in fact amount of jitter (estimation amount of jitter) when the audio clock of sink device 650 generates piece 400 regeneration (generation) audio clock (step S925).Determine then whether this estimation amount of jitter falls within the represented amount of jitter of tolerable wobble information (tolerable amount of jitter) (step S926).
If determine to estimate that amount of jitter is less than tolerable amount of jitter (step S926), then tranmitting data register speed is determined piece 630 with this standard proportional factor Set scale factor, and tranmitting data register generates piece (PLL) 620 and adopts this scale factor to amplify described clock (step S927).Then, tranmitting data register speed determines that piece 630 will arrive about the information supply of set scale factor multiplexed 150(step S931 of stream).This step has been finished described tranmitting data register set handling.
On the other hand, if determine to estimate amount of jitter greater than tolerable amount of jitter (step S926), tranmitting data register speed is determined piece 630 and calculate tranmitting data register speed (scale factor calculation speed) (step S928) so that the amount of jitter that produces is equal to or less than the mode of tolerable amount of jitter when the regeneration of audio clock.Based on the scale factor calculation speed of such calculating, tranmitting data register speed determines that piece 630 calculates tranmitting data register and generates piece (PLL) 620 employed scale factors (calculated scale factor) (step S929).Then tranmitting data register speed determines that the scale factor that piece 630 calculates is set to scale factor, and tranmitting data register generates piece (PLL) 620 and amplifies described clock (step S930) by this scale factor.Afterwards, arrive step S931.
According to the invention described above the second embodiment, the audio clock of regenerating by the division of being undertaken by sink device improves by the size of suitably regulating the blanking interval in the transmission stream that is generated by source device.
Adopt aforesaid way, can generate described clock according to embodiments of the invention easily.
Although by dividing the reproducing audio clock, that regenerates is not limited to audio clock to the above embodiment of the present invention hypothesis.Replacedly, the present invention also can be applied on a kind of clock, and this clock is different from tranmitting data register in the cycle and also can be reproduced according to this tranmitting data register based on the information that represents the frequency relation between these two clocks.
Above-mentioned for the present invention is embodiment, shows and has calculated the CTS value according to the relation between tranmitting data register and the 1/N audio clock.Replacedly, can calculate the CTS value according to the relation between video clock and the 1/N audio clock.Under latter event, in fact the scale factor between video clock and tranmitting data register (the first embodiment is 30) can be used for calculate the multiplication of CTS value, so that when above-mentioned expression formula (2) is calculated the as a result CTS value of gained is placed above-mentioned expression formula.
In above-mentioned explanation of the present invention and embodiment, show that tranmitting data register generates based on sending stream.But this is not limitation of the present invention.When sending tranmitting data register, source device also can use the present invention.
Above preferred embodiment only is wherein to have realized example of the present invention.These embodiment with and the detailed part of version correspond essentially to attached right will book in disclosed theme required for protection.Equally, the disclosed theme of naming in attached claims corresponds essentially to the identical title in the description of preferred embodiment.But, these embodiment and its version and other examples of the present invention are not limitation ot it, and it will be recognized by those of skill in the art that, can make various modifications, combination, sub-portfolio or variation according to designing requirement or other factors, as long as they are within the scope or its equivalency range of attached claims.
And above-mentioned series of steps and process also can be considered to a kind of method of carrying out such step and process, a kind of for so that computer is carried out program or a kind of recording medium that calculates this program of this method as the part of these embodiment.As a kind of recording medium that calculates this program, can adopt hard disk, CD(compact disk), the MD(mini-disk), the DVD(digital universal disc), storage card or BD(Blu-ray disc, registered trade mark).
The present invention is also configurable as follows:
(1) a kind of data receiver circuit, comprise: clock generates piece, be configured to divide the first clock based on clock information, described the first clock is the clock as the transmission stream of the target that sends video data between a plurality of devices, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of tentation data, and described clock generates piece and also exports the clock that is divided as described second clock.
(1) according to aforementioned section (1) described data receiver circuit, wherein said transmission stream has at this by multiplexed described video data, described tentation data and described clock information, be sent out, described the first clock generates by amplifying the predetermined ratio factor for the clock that transmits described video data in for the device that sends described transmission stream described transmission stream and described the first clock synchronous;
Described data receiver circuit also comprises: multiplexed, be configured to carry out multiplexed to being sent to the transmission stream in the described video data, described tentation data and described clock information;
Described clock generates piece by being divided described the first clock by multiplexed clock information and generate described second clock based on described.
(3) according to aforementioned section (2) described data receiver circuit, wherein, described the first clock is for using than the clock that sends described transmission stream at the path transmit path still less that transmits described video data for the described device that sends described transmission stream.
(4) according to aforementioned section (3) described data receiver circuit, wherein, described the first clock is to use single transmit path to send the clock of described transmission stream.
(5) according to aforementioned section (2) described data receiver circuit, wherein, the described predetermined ratio factor be for so that the amount of jitter that in described second clock, comprises less than as with reference to the scheduled volume of value.
(6) according to the described data receiver circuit in aforementioned section (1)-(5), wherein,
Described clock information comprises CTS value and N value, the clock quantity of described the first clock that described CTS value indication is corresponding with a clock cycle of the described second clock that is divided into predetermined space, and the described predetermined space of described N value indication, and
Described clock generates piece and generates described second clock by dividing described the first clock based on the ratio between described CTS value and the described N value.
(6) according to the described data receiver circuit in aforementioned section (1)-(6), wherein,
Described tentation data is voice data; And
Described second clock is the master clock of described voice data.
(8) according to aforementioned section (7) described data receiver circuit, wherein, the frequency of described the first clock is at least 20 times of frequency of the described master clock of described audio frequency.
(9) a kind of data sink comprises:
The first clock generates piece, be configured to generate the first clock as the clock of the transmission stream that is sent out via the single-pathway from the dispensing device that is used for sending video data to described data sink, described the first clock is based on the described transmission stream that has been sent out and generate;
Multiplexed, be configured to carry out multiplexedly to being sent to described transmission stream, tentation data and clock information in the described video data, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of described tentation data; And
Clock generates piece, is configured to before clock that output is divided is as described second clock based on described the first clock that is generated of being divided by multiplexed clock information.
(10) a kind of information processing system comprises:
Data sending device, be configured to generated clock information before transmission has by the transmission of multiplexed video data, tentation data and clock information stream, this clock information has been indicated the period-luminosity relation between the first clock and the second clock, this first clock is that second clock is as the clock of tentation data as the clock of the transmission stream of the target that sends video data between a plurality of devices; And
Data sink, being configured to receive the described transmission stream that has been sent out and demultiplexing is flowed in received transmission is described video data, described tentation data and described clock information, and described data sink is also divided described the first clock in order to generate described second clock based on described clock information.
(11) according to above-mentioned section (10) described information processing system, wherein, described data sending device calculate scale factor so that so that the amount of jitter that in the described second clock that is generated by described data sink, comprises less than as the scheduled volume with reference to value, described data sending device also generate described the first clock by the clock amplification predetermined ratio factor that will be used for the described video data of transmission in described data sending device.
(12) according to above-mentioned section (11) described information processing system, wherein, described data sending device generates described transmission in the mode of the speed of the blanking interval that comprises and the proportional rising of increase in the described scale factor and flows in described transmission stream.
(13) a kind of data receive method, comprise: divide the first clock based on clock information, described the first clock is the clock as the transmission stream of the target that sends video data between a plurality of devices, and described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of tentation data; And the clock that output is divided is as described second clock.
The present invention comprise with the Japanese priority patent JP2012-051121 that submitted to Japan Office on 03 08th, 2012 in the theme of the Topic relative that discloses, it comprises in this application as a whole by reference.
Claims (13)
1. data receiver circuit comprises:
Clock generates piece, be configured to divide the first clock based on clock information, described the first clock is the clock as the transmission stream of the target that sends video data between a plurality of devices, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of tentation data, and described clock generates piece and also exports the clock that is divided as described second clock.
2. data receiver circuit according to claim 1, wherein said transmission stream has at this by multiplexed described video data, described tentation data and described clock information, be sent out, described the first clock generates by amplifying the predetermined ratio factor for the clock that transmits described video data in for the device that sends described transmission stream described transmission stream and described the first clock synchronous;
Described data receiver circuit also comprises:
Multiplexed, be configured to carry out multiplexed to being sent to the transmission stream in the described video data, described tentation data and described clock information;
Described clock generates piece by being divided described the first clock by multiplexed clock information and generate described second clock based on described.
3. data receiver circuit according to claim 2, wherein, described the first clock is the clock that sends described transmission stream than the path transmit path still less that transmits described video data at the described device that is used for sending described transmission stream for using.
4. data receiver circuit according to claim 3, wherein, described the first clock is to use single transmit path to send the clock of described transmission stream.
5. data receiver circuit according to claim 2, wherein, the described predetermined ratio factor be for so that the amount of jitter that in described second clock, comprises less than as the scheduled volume with reference to value.
6. data receiver circuit according to claim 1, wherein,
Described clock information comprises CTS value and N value, the clock quantity of described the first clock that described CTS value indication is corresponding with a clock cycle of the described second clock that is divided into predetermined space, and the described predetermined space of described N value indication, and
Described clock generates piece and generates described second clock by dividing described the first clock based on the ratio between described CTS value and the described N value.
7. data receiver circuit according to claim 1, wherein,
Described tentation data is voice data; And
Described second clock is the master clock of described voice data.
8. data receiver circuit according to claim 7, wherein, the frequency of described the first clock is at least 20 times of frequency of the described master clock of described audio frequency.
9. data sink comprises:
The first clock generates piece, be configured to generate the first clock as the clock of the transmission stream that is sent out via the single-pathway from the dispensing device that is used for sending video data to described data sink, described the first clock is based on the described transmission stream that has been sent out and generate;
Multiplexed, be configured to carry out multiplexedly to being sent to described transmission stream, tentation data and clock information in the described video data, described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of described tentation data; And
Clock generates piece, is configured to before clock that output is divided is as described second clock based on described the first clock that is generated of being divided by multiplexed clock information.
10. information processing system comprises:
Data sending device, be configured to generated clock information before transmission has by the transmission of multiplexed video data, tentation data and clock information stream, this clock information has been indicated the period-luminosity relation between the first clock and the second clock, this first clock is that second clock is as the clock of tentation data as the clock of the transmission stream of the target that sends video data between a plurality of devices; And
Data sink, being configured to receive the described transmission stream that has been sent out and demultiplexing is flowed in received transmission is described video data, described tentation data and described clock information, and described data sink is also divided described the first clock in order to generate described second clock based on described clock information.
11. information processing system according to claim 10, wherein, described data sending device calculate scale factor so that so that the amount of jitter that in the described second clock that is generated by described data sink, comprises less than as the scheduled volume with reference to value, described data sending device also generate described the first clock by the clock amplification predetermined ratio factor that will be used for the described video data of transmission in described data sending device.
12. information processing system according to claim 11, wherein, described data sending device generates described transmission in the mode of the speed of the blanking interval that comprises and the proportional rising of increase in the described scale factor and flows in described transmission stream.
13. a data receive method comprises:
Divide the first clock based on clock information, described the first clock is the clock as the transmission stream of the target that sends video data between a plurality of devices, and described clock information is indicated described the first clock and as the period-luminosity relation between the second clock of the clock of tentation data; And
The clock that output is divided is as described second clock.
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| JP2012-051121 | 2012-03-08 | ||
| JP2012051121A JP2013187724A (en) | 2012-03-08 | 2012-03-08 | Data reception circuit, data reception apparatus, information processing system, and data reception method |
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| US20130235269A1 (en) | 2013-09-12 |
| US8949490B2 (en) | 2015-02-03 |
| CN103313099B (en) | 2017-12-15 |
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