CN103311117A - Method for corroding Si substrate of sample by wet method - Google Patents
Method for corroding Si substrate of sample by wet method Download PDFInfo
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- CN103311117A CN103311117A CN2013101724415A CN201310172441A CN103311117A CN 103311117 A CN103311117 A CN 103311117A CN 2013101724415 A CN2013101724415 A CN 2013101724415A CN 201310172441 A CN201310172441 A CN 201310172441A CN 103311117 A CN103311117 A CN 103311117A
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Abstract
The invention provides a method for corroding a Si substrate of a sample by a wet method. The method comprises the following steps that a photoresist layer is coated on a function layer at one side opposite to the Si substrate and is dried; 2, an epoxy resin covering layer is formed on the outer periphery of the function layer and the Si substrate; 3, an opening is formed in the covering layer at the Si substrate side, and the Si substrate is exposed; 4) etching agents are utilized for corroding the exposed Si substrate; 5) the photoresist layer coated on the function layer is exposed so that the photoresist layer is dissolved; and 6) the epoxy resin covering layer falls off.
Description
Technical field
The present invention relates to a kind of method of Si substrate of wet etching sample, relate in particular to a kind of in the method for the back side of SOI wafer wet etching Si with the formation opening.
Background technology
The single-chip of silicon (Silicon Wafer) is the semi-conductor industry most important material, is the motherboard of making integrated circuit (IC, Integrated Circuit) chip.Silicon single crystal flake can be processed to the wafer (Engineered Wafer) of layer structure, to obtain special electricity/optical property.In all stratiform silicon wafers, foremost is exactly Silicon-On-Insulator wafer (SOI, Silicon On Insulator).It is by the monocrystalline silicon (the hundreds of nanometer is to several microns) of top layer, and the substrate monocrystal silicon (hundreds of micron) of the insulator oxide silicon in intermediate layer (2-4 micron) and bottom is formed.Utilize the electrical couplings between insulating layer of silicon oxide partition top layer and the substrate, based on the integrated circuit of Silicon-On-Insulator wafer have that leakage current is little, low in energy consumption, driving voltage is low, parasitic capacitance is little, response speed is fast, puncture voltage is high, series of advantages such as high temperature resistant, radioresistance, be the mainstream technology of integrated circuit (IC) chip of new generation.
Another important application of Silicon-On-Insulator wafer is to make integrated optical circuit (PIC, Photonic Integrated Circuit) chip.The fiber waveguide of utilizing top layer high refractive index medium and intermediate layer low refractive index dielectric to form, people can produce and the similar integrated optical circuit chip of integrated circuit.Integrated optical circuit light wave beared information can overcome in the integrated circuit electronic bottleneck effect to the restriction of conversion speed, is the important technology that following high speed integrated information is handled.Silicon-On-Insulator wafer greatly reduces the cost of integrated optical circuit chip realization of industrialization with the semiconductor CMOS technology based on silicon is compatible fully at present.Therefore, Silicon-On-Insulator wafer is attract most attention in all integrated optics techniques a kind of.
The manufacture method of Silicon-On-Insulator wafer roughly has following three kinds:
(1) annotates oxygen isolation method (SIMOX, Separation by Implantation of Oxygen), as shown in Figure 1, the oxonium ion of high energy is directly injected certain depth under the silicon wafer surface, form silicon oxide layer, through high annealing the oxonium ion that injects is evenly distributed.Annotating the oxygen isolation method is the most ripe at present silicon-on-insulator manufacture method.
(2) bonding and back side etch (BESOI, Bonding-Etchback SOI), as shown in Figure 2, surface at a monocrystalline silicon piece forms silica, with itself and another piece monocrystalline silicon high temperature bonding, carry out reverse side corrosion and polishing then, consume two silicon chips and generate a Silicon-On-Insulator wafer.
(3) smart peeling method (Smart Cut), as shown in Figure 3, surface at a monocrystalline silicon forms oxide-film, the high energy hydrogen ion is injected oxide-film below certain depth, this piece silicon chip and another piece aimed single crystal wafer bonding are got up, utilizing thermal effect to form in hydrogen ion injection place peels off, peel off the Silicon-On-Insulator wafer of the part process polishing formation stratiform of getting off, another part is then proceeded " oxidation-hydrogen ion injection-bonding-peel off " and is handled, and makes next piece Silicon-On-Insulator wafer.
As from the foregoing, all Silicon-On-Insulator wafer all comprise the silica of several micron thickness of one deck and the monocrystalline substrate of its below hundreds of micron thickness.In the design of integrated optical circuit, silicon substrate is inoperative, does not constitute any part of fiber waveguide., for silicon base CMOS technology, this layer substrate guaranteed that Silicon-On-Insulator wafer can be by existing industrial standard compatibility.And substrate provides chip required mechanical strength.The thickest insulating layer of silicon oxide has only 4 microns at present, and the compactness of oxide layer materials neither be very good, depends insulating layer of silicon oxide alone and can't provide mechanical support for optical waveguide loop.
Yet in the integrated optical circuit of some particular design, people wish to remove substrate in some zone of chip, in order to avoid stop the device radiation downwards in the light waveguide-layer, and as shown in Figure 4.Such process " window " Silicon-On-Insulator wafer handled for three-dimensional integrated optical circuit layout provides may, thereby may break the restriction that existing integrated optics technique is confined to two dimensional surface, for the design of high density integrated optical circuit chip provides new thinking.Simultaneously, wish that also the material of main part of chip after treatment remains silicon, like this, can with existing CMOS industrial standard compatibility.
In order to remove silicon substrate, method commonly used has dry etching and wet etching.The shortcoming of dry etching is to need to use expensive little process equipment, etching selection ratio little (less than 150), and processing procedure produces a large amount of pernicious gas (Cl
2, HBr, HCl etc.), etching process can't be monitored in real time.
Wet etching has greater advantage at aspects such as equipment and time costs than dry etching.The about 2-4 micron of the etching speed of wet etching/minute (along monocrystalline silicon＜100〉direction, namely perpendicular to the direction of Silicon-On-Insulator wafer), the corrosion of silicon and silica is selected than being 1000:1, and corrosion process does not produce pernicious gas, and can monitor in real time.Highly basic commonly used is as the corrosive agent of silicon thin film material in the conventional semiconductor technology.Because the thickness of the thickness of the silicon substrate of SOI chip back surface silicon thin film commonly used in the semiconductor technology, therefore the temperature that needs to improve corrosive agent is accelerated corrosion rate to reduce time cost, but the anticorrosive additive material of using always during corrosion silicon, as photoresist etc., be difficult to withstand the highly basic under the high temperature, so wet corrosion technique commonly used is difficult to use in the corrosion to the SOI wafer in the conventional semiconductor technology.And after the Si substrate of Silicon-On-Insulator wafer was corroded, " silicon-silica " on wafer top formed extremely thin film (a few micron thickness), very easily damaged.
Summary of the invention
The present invention proposes a kind of caustic solution, can be used for corroding the silicon substrate at the Silicon-On-Insulator wafer back side, can utilize highly basic under the high temperature as corrosive agent improving corrosion rate, and can avoid the damage to " silicon-silica " layer on wafer top simultaneously.
The invention provides a kind of method of wet etching Si substrate, comprising:
1) functional layer in an opposite side with the Si substrate applies photoresist layer, and makes its drying;
2) form the epoxy resin integument at Si substrate and functional layer periphery;
3) in the integument of Si substrate side, form opening, expose silicon substrate;
4) utilize etching agent that the silicon substrate that exposes is corroded;
5) expose the photoresist layer that is coated on the functional layer, make this photoresist layer dissolving;
6) described epoxy resin integument is come off.
According to method provided by the invention, wherein said photoresist is PMMA.
According to method provided by the invention, the dried thermal coefficient of expansion of wherein said photoresist is less than 10 * 10
-5/ ℃.
According to method provided by the invention, wherein said photoresist is S1813 type photoresist.
According to method provided by the invention, wherein adopt mechanical means in the integument of Si substrate side, to form opening.
According to method provided by the invention, wherein the degree of depth of the described opening in described integument arrives in the Si substrate.
According to method provided by the invention, wherein step 2) in, comprise that also Si substrate and the functional layer that will be enclosed with the epoxy resin integument stick on the carrier, and make functional layer one side towards this carrier.
According to method provided by the invention, wherein in the step 5), expose described photoresist layer by at least a portion of removing described integument.
According to method provided by the invention, wherein the object of this method corrosion is silica-based layered wafer.
According to method provided by the invention, wherein the object of this method corrosion is silicon nitride or silicon-on-insulator on carborundum, the insulator on germanium on insulator, the insulator.
The method of the Si substrate of wet etching sample provided by the invention, can utilize highly basic under the high temperature as corrosive agent improving corrosion rate, and can avoid the damage to " silicon-silica " layer on wafer top simultaneously.
SOI wafer after method provided by the invention is processed has more excellent photonic propulsion performance, can and make the sub-loop of high density integrated electro for design new possibility is provided.
Description of drawings
It is following that embodiments of the present invention is further illustrated with reference to accompanying drawing, wherein:
Fig. 1 is for annotating the process flow diagram of oxygen isolation method;
Fig. 2 is the process flow diagram of bonding and back side etch;
Fig. 3 is the process flow diagram of smart peeling method;
Fig. 4 is the structural representation of integrated optical circuit;
The process flow diagram of the method that provides according to embodiments of the invention is provided Fig. 5;
Fig. 6 a-6c is respectively optical photograph, transmission and the reflection micro-image of SOI wafer.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, the present invention is described in more detail.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
Present embodiment provides a kind of method of Si substrate of wet etching SOI chip back surface, this SOI wafer comprise silicon substrate and on " silicon-silica " layer, its flow process comprises as shown in Figure 5:
1) cleans silicon-on-insulator (SOI) wafer surface successively with acetone, ethanol, deionized water, dry up with nitrogen then;
2) apply the PMMA electron beam resist of one deck 1 micron thickness in SOI wafer top surface (one side nearer apart from silicon oxide layer I), about 2000 rev/mins of the rotating speed of sol evenning machine, 20 seconds time, SOI wafer behind the gluing is dried at the heat dish, 180 degrees centigrade of temperature, 60 seconds time, remove residual solvent in the photoresist, shown in left figure among Fig. 5-a;
3) shown in right figure among Fig. 5-a, apply epoxide-resin glue 2 at a slide 1, the SOI wafer is placed on the epoxide-resin glue 2, and make the end face of SOI crystalline substance in the face of slide 1, continue then to apply epoxy resin at the back side of SOI wafer, the SOI wafer is wrapped in the epoxy resin, after 5 to 10 minutes, epoxy resin cure forms tight translucent epoxy resin integument 3, shown in Fig. 5-b;
4) with power auger drilling bore hole 4 in the epoxy resin integument 3 of SOI chip back surface (apart from silicon oxide layer I one side far away), this hole 4 is passed epoxy resin integument 3 and is reached in the silicon substrate of SOI chip back surface, shown in Fig. 5-c;
5) sample that step 4) is obtained is put into the potassium hydroxide aqueous solution of 80 degrees centigrade of mass concentrations 26%, corrode silicon substrate along＜100〉crystal orientation (being vertical direction) in the hole 4 that this strong base solution passes in the integument 3, reaction produces a large amount of hydrogen, constantly stir solution to promote that exhaust (also can add isopropyl alcohol in this strong base solution, reduce the size of hydrogen gas bubbles, so that the discharge of gas), after about 2-3 hour, silicon substrate is corroded, insulating layer of silicon oxide I becomes etch stop layer, expose translucent " silicon-silica " film, shown in Fig. 5-d;
6) cut the epoxy resin of SOI chip back surface with cutter along the A1 direction, cut a part of epoxy resin around the SOI wafer with cutter along the A2 direction again, expose from epoxy resin integument 3 so that be coated in the PMMA of SOI wafer top surface before, shown in Fig. 5-e;
7) sample that step 6) is obtained immerses acetone soln, and PMMA is formed one deck space, shown in Fig. 5-f by complete molten going after about 2-3 hour between the end face of SOI wafer and the epoxy resin integument 3;
8) sample that step 7) is obtained immerses in the epoxy resin agents for defoliating, make epoxy resin integument 3 by powdered, thereby make the SOI wafer from epoxy resin integument 3, peel off out, shown in Fig. 5-g, get final product after cleaning up the figuratum SOI wafer that is corroded to the back side.
The optical photograph of the SOI sample wafer that the method for present embodiment obtains is shown in Fig. 6 a, and the bright spot of central authorities is and erodes translucent " silicon-silica " thin layer that exposes behind the silicon substrate.Fig. 6 b and 6c are the transmission of sample under light microscope and reflection photo.Shown in Fig. 6 b, the silicon substrate of sample is thoroughly removed in 1 * 1 square millimeter zone, and " silicon-silica " thin layer of 2-3 micron thickness is without any damage on the end face.
In the method that present embodiment provides, substitute photoresist of the prior art etc. by using epoxy resin, serve as the resist of wet etching, thereby can utilize highly basic under the high temperature as corrosive agent, and then improve corrosion rate.In addition, utilize epoxy resin as resist, and in conjunction with the mechanical strength humidification of slide, can also prevent from " silicon-silica " thin layer on the end face is caused damage.This is the cure shrinkage low (0.1-0.3%) owing to epoxy resin, and thermal coefficient of expansion is little by (6.0 * 10
-5/ ℃), after variations in temperature, not only can closely wrap up with the SOI sample wafer, do not stay the slit, can also make the stress that is applied to " silicon-silica " thin layer littler.In addition, the epoxy resin shape that is translucent, the operator can see through integument and monitor in real time the corrosion process of sample, be easy to judge whether silicon substrate has been removed totally, and whether " silicon-silica " film of SOI wafer top layer is damaged.
Remove integument in order to finish back safety in corrosion, silicon wafer top " silicon-silica " film (a few micron thickness) has as thin as a wafer needed protection.As previously mentioned, be subjected to the restriction of Silicon-On-Insulator wafer manufacture method, the mechanical strength of this layer film is also bad.Lost the protection of silicon substrate, it may be attached superincumbent epoxy resin and directly glue, and the swelling heat air that also may be sealed up for safekeeping trace in integument crushes.For this reason, can not allow epoxy resin directly contact with the end face of Silicon-On-Insulator wafer, can not allow every the packing material generation thermal expansion between epoxy resin integument and silicon wafer, this packing material also must be removed than being easier to simultaneously.In the method that present embodiment provides, utilize and removed the electron beam resist PMMA(polymethyl methacrylate behind the solvent) as the packing material between epoxy resin integument and the silicon wafer end face.The thermal coefficient of expansion of having removed the photoresist behind the solvent (thermal coefficient of expansion of the PMMA after the oven dry about 8.5 * 10 that declines to a great extent
-5/ ℃), add the very thin thickness (being generally less than 1 micron) of filler, in the temperature back (to 90 ° of C) that raises, can not produce the bulbs of pressure in the integument, thereby avoid the breakage of " silicon-silica " film of Silicon-On-Insulator wafer top layer.On the other hand, PMMA is easy to by acetone solution.After corrosion finished, this layer photoetching glue can form one deck space between epoxy resin integument and silicon wafer end face, create conditions for safety divests the epoxy resin integument.
According to one embodiment of present invention, wherein the packing material between epoxy resin integument and the silicon wafer end face is not limited to PMMA, for example can also be S1813 type photoresist, and the thermal coefficient of expansion of dried S1813 type photoresist is about 3-7.6 * 10
-6/ ℃, also can be the photoresist of other models, make its thermal coefficient of expansion lower by drying, thereby prevent the breakage of " silicon-silica " film.In the method provided by the invention, the preferred dry back thermal coefficient of expansion that uses is less than 10 * 10
-5/ ℃ photoresist.In addition, the solvent that is used for the packing material between dissolved epoxy integument and the silicon wafer end face is not limited to acetone, all can be used for the present invention so long as can dissolve the solvent of this packing material.
According to one embodiment of present invention, wherein the concrete technological parameter at SOI wafer coating photoresist is general knowledge known in this field, and those skilled in the art can select the combination of various technological parameters neatly according to the parameters such as concrete thickness that apply photoresist.
According to one embodiment of present invention, wherein above-mentioned slide also can replace with other carrier, is subjected to along bad to prevent " silicon-silica " thin layer, and this carrier preferably is made of material transparent and that have certain mechanical strength.
According to one embodiment of present invention, above-mentioned steps 4) in, the hole 4 that gets out with power auger penetrates epoxy resin integument 3 at least, and under the prerequisite that does not arrive " silicon-silica " thin layer, be preferably dark as much as possible, thereby shorten time of wet etching.In addition, in other embodiments, in the SOI wafer, form the shape that opening is not limited to above-mentioned hole 4, can design multiple patterning opening according to actual needs, wire etc. for example, and utilize the method for machinery in epoxy resin integument 3, to form the opening of respective shapes, and then in silicon substrate, form the opening of respective shapes by wet etching.
According to one embodiment of present invention, wherein the opening that utilizes mechanical method to form different shape in epoxy resin integument 3 is general knowledge known in this field, for example can be by the SOI wafer be fixed on the removable sample platform, and depict the opening of arbitrary shape at the back side of SOI wafer by rig.
According to one embodiment of present invention, the method that wherein forms opening in epoxy resin integument 3 is not limited to the method for machinery, also can be other method physics or chemistry etc.
In the method provided by the invention, dry etching with the cheapness alternative use of wet etching fast expensive device, greatly reduce Silicon-On-Insulator wafer is carried out the cost that substrate is removed processing, the Silicon-On-Insulator wafer that has the special optical performance for mass production provides feasible program.And only remove substrate in the subregion of Silicon-On-Insulator wafer, entire chip has still kept silicon base, thus can with CMOS industrial standard coupling, this with the quartz body that entire substrate is replaced into other materials on silicon technology different fully.
Method provided by the invention can also be applied in other the silica-based layered wafer and go, such as germanium on insulator (GeOI, Germanium On Insulator), carborundum (SiCOI on the insulator, Silicon Carbide On Insulator), silicon nitride (Si on the insulator
3N
4) etc., be used for eroding the Si substrate from the back side and expose the functional layer of Si substrate end face.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention has been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. the method for a wet etching Si substrate comprises:
1) functional layer in an opposite side with the Si substrate applies photoresist layer, and makes its drying;
2) form the epoxy resin integument at Si substrate and functional layer periphery;
3) in the integument of Si substrate side, form opening, expose silicon substrate;
4) utilize etching agent that the silicon substrate that exposes is corroded;
5) expose the photoresist layer that is coated on the functional layer, make this photoresist layer dissolving;
6) described epoxy resin integument is come off.
2. method according to claim 1, wherein said photoresist is PMMA.
3. method according to claim 1, the dried thermal coefficient of expansion of wherein said photoresist is less than 10 * 10
-5/ ℃.
4. method according to claim 1, wherein said photoresist is S1813 type photoresist.
5. method according to claim 1 wherein adopts mechanical means to form opening in the integument of Si substrate side.
6. method according to claim 1, wherein the degree of depth of the described opening in described integument arrives in the Si substrate.
7. method according to claim 1, wherein step 2) in, comprise that also Si substrate and the functional layer that will be enclosed with the epoxy resin integument stick on the carrier, and make functional layer one side towards this carrier.
8. method according to claim 1 wherein in the step 5), exposes described photoresist layer by at least a portion of removing described integument.
9. method according to claim 1, wherein the object of this method corrosion is silica-based layered wafer.
10. method according to claim 1, wherein the object of this method corrosion is silicon nitride or silicon-on-insulator on carborundum, the insulator on germanium on insulator, the insulator.
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| CN201310172441.5A CN103311117B (en) | 2013-05-10 | 2013-05-10 | A kind of method of Si substrate of wet etching sample |
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| CN201310172441.5A CN103311117B (en) | 2013-05-10 | 2013-05-10 | A kind of method of Si substrate of wet etching sample |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106848809A (en) * | 2017-03-06 | 2017-06-13 | 李志远 | A kind of generation is visible to infrared band pole broadband, the device of super continuous laser |
| CN110988768A (en) * | 2019-10-25 | 2020-04-10 | 浙江铖昌科技有限公司 | On-wafer calibration piece based on diaphragm and heterogeneous integration process and manufacturing method thereof |
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|---|---|---|---|---|
| US4589952A (en) * | 1982-07-03 | 1986-05-20 | International Business Machines Corporation | Method of making trenches with substantially vertical sidewalls in silicon through reactive ion etching |
| US5899750A (en) * | 1996-03-12 | 1999-05-04 | Denso Corporation | Fine processing method |
| JP2004109296A (en) * | 2002-09-17 | 2004-04-08 | Toppan Printing Co Ltd | Photosensitive hot melt resist and etching method using same |
| CN1828422A (en) * | 2005-03-04 | 2006-09-06 | 中芯国际集成电路制造(上海)有限公司 | Minute pattern photoetching method |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4589952A (en) * | 1982-07-03 | 1986-05-20 | International Business Machines Corporation | Method of making trenches with substantially vertical sidewalls in silicon through reactive ion etching |
| US5899750A (en) * | 1996-03-12 | 1999-05-04 | Denso Corporation | Fine processing method |
| JP2004109296A (en) * | 2002-09-17 | 2004-04-08 | Toppan Printing Co Ltd | Photosensitive hot melt resist and etching method using same |
| CN1828422A (en) * | 2005-03-04 | 2006-09-06 | 中芯国际集成电路制造(上海)有限公司 | Minute pattern photoetching method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106848809A (en) * | 2017-03-06 | 2017-06-13 | 李志远 | A kind of generation is visible to infrared band pole broadband, the device of super continuous laser |
| CN110988768A (en) * | 2019-10-25 | 2020-04-10 | 浙江铖昌科技有限公司 | On-wafer calibration piece based on diaphragm and heterogeneous integration process and manufacturing method thereof |
| CN110988768B (en) * | 2019-10-25 | 2022-04-22 | 浙江铖昌科技股份有限公司 | On-wafer calibration piece based on diaphragm and heterogeneous integration process and manufacturing method thereof |
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| CN103311117B (en) | 2016-03-30 |
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