CN103311117A - Method for corroding Si substrate of sample by wet method - Google Patents

Method for corroding Si substrate of sample by wet method Download PDF

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CN103311117A
CN103311117A CN2013101724415A CN201310172441A CN103311117A CN 103311117 A CN103311117 A CN 103311117A CN 2013101724415 A CN2013101724415 A CN 2013101724415A CN 201310172441 A CN201310172441 A CN 201310172441A CN 103311117 A CN103311117 A CN 103311117A
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si substrate
method
silicon
method according
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CN103311117B (en
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丁伟
郭红莲
甘霖
李志远
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中国科学院物理研究所
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Abstract

The invention provides a method for corroding a Si substrate of a sample by a wet method. The method comprises the following steps that a photoresist layer is coated on a function layer at one side opposite to the Si substrate and is dried; 2, an epoxy resin covering layer is formed on the outer periphery of the function layer and the Si substrate; 3, an opening is formed in the covering layer at the Si substrate side, and the Si substrate is exposed; 4) etching agents are utilized for corroding the exposed Si substrate; 5) the photoresist layer coated on the function layer is exposed so that the photoresist layer is dissolved; and 6) the epoxy resin covering layer falls off.

Description

一种湿法腐蚀样品的Si衬底的方法 A method of wet etching a Si substrate sample

技术领域 FIELD

[0001] 本发明涉及一种湿法腐蚀样品的Si衬底的方法,尤其涉及一种在SOI晶片的背面湿法腐蚀Si以形成开口的方法。 [0001] The present invention relates to a sample of the wet etching process of the Si substrate, particularly to a rear surface of the SOI wafer wet etching method to form an opening Si.

背景技术 Background technique

[0002] 硅的单晶片(Silicon Wafer)是半导体工业最重要的原料,是制作集成电路(IC, Integrated Circuit)芯片的母板。 [0002] Single wafer silicon (Silicon Wafer) is the most important raw material of semiconductor industry, it is to produce an integrated circuit (IC, Integrated Circuit) chip motherboard. 娃单晶片可以被加工成层状结构的晶片(Engineered Wafer),以获得特殊的电学/光学性能。 Baby single wafer can be processed into a layered structure of the wafer (Engineered Wafer), in order to obtain particular electrical / optical properties. 在所有的层状硅晶片中,最著名的就是绝缘体上娃晶片(SOI, Silicon On Insulator)。 In all layered silicon wafer, it is the most famous baby-on-insulator wafer (SOI, Silicon On Insulator). 它由顶层的单晶娃(几百纳米至几微米),中间层的绝缘体氧化硅(2-4微米)和底层的衬底单晶硅(几百微米)组成。 It consists of a single crystal top layer Wa (hundreds of nanometers to several micrometers), the intermediate layer is a silicon oxide insulator (2-4 microns) single crystal silicon substrate and the bottom (several hundred microns) composition. 利用氧化硅绝缘层隔断顶层与衬底之间的电气耦合,基于绝缘体上硅晶片的集成电路具有漏电流小、 功耗低、驱动电压低、寄生电容小、响应速度快、击穿电压高、耐高温、抗辐射等一系列优点, 是新一代集成电路芯片的主流技术。 Blocking silicon oxide insulating layer and electrically coupled between the top substrate, a silicon on insulator wafer based on an integrated circuit having low leakage current, low power consumption, low driving voltage, small parasitic capacitance, high response speed, high breakdown voltage, high temperature, anti-radiation and a series of advantages, is a new generation integrated circuit chip mainstream technology.

[0003] 绝缘体上硅晶片的另一项重要应用是制作集成光路(PIC,Photonic Integrated Circuit)芯片。 [0003] Another important application is the silicon on insulator wafer made photonic integrated circuit (PIC, Photonic Integrated Circuit) chip. 利用顶层高折射率介质与中间层低折射率介质形成的光波导,人们可以制作出与集成电路类似的集成光路芯片。 Using a high refractive index dielectric top layer and the intermediate layer of low refractive index optical medium formed, one can create an integrated circuit similar to the integrated optics chip. 集成光路用光波承载信息,能够克服集成电路中电子瓶颈效应对信号处理速度的限制,是未来高速集成信息处理的重要技术。 Integrated optical path carries information light, an integrated circuit capable of overcoming electronic bottleneck effect on the signal processing speed, high-speed integrated information technology is an important process in the future. 绝缘体上硅晶片与目前以硅为基础的半导体CMOS工艺完全兼容,大大降低了集成光路芯片工业化实现的成本。 Silicon-on-insulator wafer is fully compatible with current silicon-based semiconductor (CMOS) process, greatly reducing the cost of the integrated optics chip industrial implementation. 因此,绝缘体上硅晶片是所有集成光路技术中最受瞩目的一种。 Thus, all the silicon on insulator wafer integrated optics technology one most attention.

[0004] 绝缘体上硅晶片的制作方法大致有如下三种: [0004] The manufacturing method of an insulator on a silicon wafer generally has the following three:

[0005] (1)注氧隔离法(SIM0X, Separation by Implantation of Oxygen),如图1 所不, 将高能的氧离子直接注入硅晶片表面下一定深度,形成氧化硅层,经过高温退火将注入的氧离子分布均匀。 [0005] (1) separation by implanted oxygen method (SIM0X, Separation by Implantation of Oxygen), not shown in FIG 1, the high-energy oxygen ions are injected directly into a certain depth below the surface of a silicon wafer, a silicon oxide layer, a high temperature annealing after injection oxygen ion distribution. 注氧隔离法是目前最为成熟的绝缘体上硅制作方法。 Separation by implanted oxygen method is the most mature SOI on the manufacturing method.

[0006] (2)键合和背面腐蚀法(BES0I,Bonding_Etchback S0I),如图2所示,在一块单晶硅片的表面形成氧化硅,将其与另一块单晶硅高温键合,然后进行反面腐蚀和抛光,消耗两块硅片生成一块绝缘体上硅晶片。 [0006] (2) is bonded and a back etching (BES0I, Bonding_Etchback S0I), shown in Figure 2, a silicon oxide on the surface of a silicon wafer, which is a single crystal silicon with another bonding temperature, and then for polishing and etching back, generating a consumption two wafers silicon on insulator wafer.

[0007] (3)智能剥离法(Smart Cut),如图3所示,在一块单晶硅的表面形成氧化膜,将高能氢离子注入氧化膜下方一定深度,将这块硅片与另一块目标单晶硅片键合起来,利用热效应在氢离子注入处形成剥落,剥落下来的部分经过抛光形成层状的绝缘体上硅晶片,而另一部分则继续进行“氧化_氢离子注入_键合-剥落”处理,制作下一块绝缘体上硅晶片。 [0007] (3) Smart Cut method (Smart Cut), as shown in FIG 3 is formed on a surface of a silicon single crystal of the oxide film, the high-energy hydrogen ion implantation depth below oxide film, silicon and the other one piece certain silicon wafer bonded together, is formed by thermal spalling effect on hydrogen ion implantation, the peeling off portion is formed on the polished silicon wafer insulator layer, and the other part continues "oxidation _ _ bonded hydrogen ion implantation - peeling "process, the production of a silicon on insulator wafer.

[0008] 由上可知,所有的绝缘体上硅晶片都包含一层几微米厚的氧化硅和其下方几百微米厚的单晶硅衬底。 [0008] From the above, all the silicon-insulator wafer comprising a single crystal silicon substrate are a silicon oxide layer of a thickness of several microns and several hundred microns thick below. 在集成光路的设计中,硅衬底是不起作用的,不构成光波导的任何部分。 In the design of integrated optical circuits, a silicon substrate is inactive, it does not form any part of the optical waveguide. 可是,对硅基CMOS工艺而言,这层衬底保证了绝缘体上硅晶片可以被现有的工业标准兼容。 However, for silicon-based CMOS process, which ensures that the substrate layer is a silicon on insulator wafer may be compatible with current industry standards. 而且,衬底提供了芯片所需的机械强度。 Further, the substrate provides the mechanical strength required for the chip. 目前最厚的氧化硅绝缘层只有4微米,氧化层材料的致密性也不是太好,光靠氧化硅绝缘层是无法为光波导回路提供机械支撑的。 Most thick silicon oxide insulating layer is only 4 microns, dense oxide layer material is not very good, a silicon oxide insulating layer alone is unable to provide mechanical support for the optical waveguide circuit. [0009] 然而,在某些特殊设计的集成光路中,人们希望在芯片的某些区域除掉衬底,以免阻挡光波导层中的器件向下方辐射,如图4中所示。 [0009] However, in some special optical integrated circuit design, it is desirable in certain areas of the chip to get rid of the substrate, the optical waveguide layer so as to avoid blocking the radiation device downwardly, as shown in FIG. 这样一个经过“开窗”处理的绝缘体上硅晶片为立体式的集成光路布局提供了可能,从而可能打破现有集成光路技术局限于二维平面的限制,为高密度集成光路芯片设计提供了新的思路。 After such a "window" on-insulator treated silicon wafer to provide a three-dimensional layout of the integrated optical circuit may possibly break the existing integrated optics techniques are limited to limit the two-dimensional plane, the integrated optics chip is designed to provide a new high-density ideas. 同时,还希望经过处理后的芯片的主体材料仍然是硅,这样,可以与现有CMOS工业标准兼容。 At the same time, we hope after treatment of the subject material is still chip of silicon, so that is compatible with existing CMOS industry standards.

[0010] 为了除去硅衬底,常用的方法有干法刻蚀和湿法腐蚀。 [0010] For a silicon substrate, a common method of removing dry etching and wet etching. 干法刻蚀的缺点是需要使用价格昂贵的微加工设备,刻蚀选择比小(小于150),处理过程产生大量有害气体(Cl2, HBr, HC1等),刻蚀过程无法实时监控。 Disadvantage of dry etching is required to use expensive micro-machining apparatus, an etching selection ratio is small (less than 150), the process is a large amount of harmful gases (Cl2, HBr, HC1, etc.), the etching process can not be real-time monitoring.

[0011] 湿法腐蚀在设备和时间成本等方面较干法刻蚀有较大优势。 [0011] Wet etching time in equipment cost and relatively dry etching has a large advantage. 湿法腐蚀的刻蚀速度约2-4微米/分钟(沿单晶硅〈100〉方向,即垂直于绝缘体上硅晶片的方向),对硅和氧化硅的腐蚀选择比为1000:1,腐蚀过程不产生有害气体,而且可以进行实时监控。 Wet etching the etching speed of about 2-4 m / min (in the single-crystal Si <100> direction, i.e. the direction perpendicular to the silicon on insulator wafer), the etching selectivity ratio of the silicon and silicon oxide is 1000: 1, corrosion process does not produce harmful gases, but also real-time monitoring. 现有的半导体工艺中常用强碱作为硅薄膜材料的腐蚀剂。 Conventional semiconductor process as a strong base etchants used in silicon thin film material. 由于SOI晶片背面的硅衬底的厚度远大于半导体工艺中常用的硅薄膜的厚度,因此需要提高腐蚀剂的温度来加快腐蚀速度以降低时间成本,但腐蚀硅时常用的抗蚀剂材料,如光刻胶等,难以耐得住高温下的强碱,因此现有的半导体工艺中常用的湿法腐蚀工艺难以用到对SOI晶片的腐蚀中。 Since the thickness of the silicon substrate is an SOI wafer back surface is much larger than the thickness of the conventional silicon thin film semiconductor process, it is necessary to increase the temperature to accelerate the corrosion rate of the etchant to reduce the time cost, but conventional silicon etching resist materials, optical plastic moment, it is difficult to endure a strong base at a high temperature, and therefore a conventional commonly used in semiconductor processes difficult to use wet etching process etching the SOI wafer. 而且当绝缘体上硅晶片的Si衬底被腐蚀掉以后,晶片顶端的“硅_氧化硅”形成非常薄的薄膜(几微米厚),极易损坏。 And later when the silicon on insulator wafer of the Si substrate is etched, the top wafer "Silicon silica _" a very thin film (a few microns thick), are easily damaged.

发明内容 SUMMARY

[0012] 本发明提出一种腐蚀方法,可用于腐蚀绝缘体上硅晶片背面的硅衬底,可利用高温下的强碱作为腐蚀剂以提高腐蚀速度,且同时能够避免对晶片顶端的“硅-氧化硅”层的损坏。 [0012] The present invention proposes a method of etching, etching may be used a silicon substrate, a silicon on insulator wafer backside, a strong base may be utilized as an etchant at a high temperature to increase the etching rate, while the top of the wafer can be avoided "silicon - oxide silicon "damaged layer.

[0013] 本发明提供一种湿法腐蚀Si衬底的方法,包括: [0013] The present invention provides a method of wet etching a Si substrate, comprising:

[0014] 1)在与Si衬底相反一侧的功能层上涂覆光刻胶层,并使其干燥; [0014] 1) in the Si substrate coated with a photoresist layer on the opposite side of the functional layer, and drying;

[0015] 2)在Si衬底及功能层外周形成环氧树脂包裹层; [0015] 2) on the outer circumference of the Si substrate and the functional layer is formed package epoxy layer;

[0016] 3)在Si衬底侧的包裹层中形成开口,暴露娃衬底; [0016] 3) an opening is formed in the Si substrate side wrapping layer, the exposed substrate baby;

[0017] 4)利用刻蚀剂对暴露的硅衬底进行腐蚀; [0017] 4) on the exposed silicon substrate is etched using an etchant;

[0018] 5)暴露出涂覆在功能层上的光刻胶层,使该光刻胶层溶解; [0018] 5) exposing the photoresist coating layer on the functional layer, so that the resist layer is dissolved;

[0019] 6)使所述环氧树脂包裹层脱落。 [0019] 6) reacting the epoxy resin layer off wrapping.

[0020] 根据本发明提供的方法,其中所述光刻胶为PMMA。 [0020] The present invention provides a method, wherein the photoresist is PMMA.

[0021] 根据本发明提供的方法,其中所述光刻胶干燥后的热膨胀系数小于10X10_5/°C。 [0021] The present invention provides a method, wherein the thermal expansion coefficient is less than the dried photoresist 10X10_5 / ° C.

[0022] 根据本发明提供的方法,其中所述光刻胶为S1813型光刻胶。 [0022] The present invention provides a method, wherein the photoresist is a photoresist S1813.

[0023] 根据本发明提供的方法,其中采用机械方法在Si衬底侧的包裹层中形成开口。 [0023] The method provided by the invention, wherein an opening is formed by mechanical means during the wrapping layer of the Si substrate side.

[0024] 根据本发明提供的方法,其中在所述包裹层中的所述开口的深度到达Si衬底中。 [0024] The present invention provides a method, wherein the depth of said wrapping layer in the opening reaching the Si substrate.

[0025] 根据本发明提供的方法,其中步骤2)中,还包括将包裹有环氧树脂包裹层的Si衬底和功能层粘附在载体上,且使功能层一侧朝向该载体。 [0025] The present invention provides a method, wherein in step 2), the package further comprising a Si substrate and the functional layer package epoxy layer adhered to the carrier, and that the functional layer side towards the carrier.

[0026] 根据本发明提供的方法,其中步骤5)中,通过去掉所述包裹层的至少一部分而暴露出所述光刻胶层。 [0026] The present invention provides a method, wherein step 5), by removing at least a portion of the wrap layer to expose the photoresist layer.

[0027] 根据本发明提供的方法,其中该方法腐蚀的对象为硅基层状晶片。 [0027] The present invention provides a method, wherein the method of etching a silicon layer of the object wafer. [0028] 根据本发明提供的方法,其中该方法腐蚀的对象为绝缘体上锗、绝缘体上碳化硅、 绝缘体上氮化娃或绝缘体上娃。 [0028] The present invention provides a method, wherein the object is a method of etching the insulator germanium, silicon carbide on insulator, upper insulator or an insulator nitride baby doll.

[0029] 本发明提供的湿法腐蚀样品的Si衬底的方法,可利用高温下的强碱作为腐蚀剂以提高腐蚀速度,且同时能够避免对晶片顶端的“硅-氧化硅”层的损坏。 [0029] The wet etch method of the Si substrate of the present invention to provide a sample may be utilized as an etchant strong base at an elevated temperature to increase the corrosion rate, while the top of the wafer can be avoided - damage "Silicon silicon oxide" layer.

[0030] 本发明提供的方法所加工后的SOI晶片,具有更为优异的光子学性能,可以为设计和制造高密度集成光电子回路提供新的可能。 SOI wafer after the [0030] method of the present invention provides a process, a photon having more excellent properties can provide new possibilities for the design and manufacture of high density integrated optoelectronic circuits.

附图说明 BRIEF DESCRIPTION

[0031] 以下参照附图对本发明实施例作进一步说明,其中: [0031] described further below with reference to the drawings as embodiments of the present invention, wherein:

[0032] 图1为注氧隔离法的工艺流程示意图; [0032] FIG. 1 is a schematic process flow diagram of the method of separation by implanted oxygen;

[0033] 图2为键合和背面腐蚀法的工艺流程示意图; [0033] FIG. 2 is a schematic process flow diagram bonding and etching the back surface;

[0034] 图3为智能剥离法的工艺流程示意图; [0034] FIG. 3 is a process flow schematic smartcut method;

[0035] 图4为集成光路的结构示意图; [0035] FIG. 4 is a schematic structural diagram of an integrated optical path;

[0036] 图5为根据本发明的实施例提供的方法的工艺流程示意图; [0036] FIG. 5 is a schematic process flow diagram a method according to an embodiment of the present invention provides;

图6a_6c分别为SOI晶片的光学照片、透射和反射显微图像。 FIG 6a_6c are optical photograph of an SOI wafer, transmission and reflection microscopy images.

具体实施方式 Detailed ways

[0037] 为了使本发明的目的、技术方案及优点更加清楚明白,以下结合具体实施例,对本发明进一步详细说明。 [0037] To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter with reference to specific embodiments, the present invention is further described in detail. 应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention.

[0038] 本实施例提供一种湿法腐蚀SOI晶片背面的Si衬底的方法,该SOI晶片包括硅衬底及其上的“硅-氧化硅”层,其流程如图5所示,包括: The method of the Si substrate [0038] The present embodiment provides a backside wet etch SOI wafer, the SOI wafer comprising a silicon substrate and on the "silicon - silicon oxide" layer, the process shown in Figure 5, comprising :

[0039] 1)用丙酮、乙醇、去离子水依次清洗绝缘体上硅(SOI)晶片表面,然后用氮气吹干; [0039] 1) with acetone, ethanol, deionized water, washed sequentially silicon on insulator (SOI) wafer surface, and then blown dry with nitrogen gas;

[0040] 2)在S0I晶片顶面(距离氧化硅层I较近的一面)涂覆一层1微米厚的PMMA电子束光刻胶,匀胶机的转速约2000转/分钟,时间20秒,将涂胶后的S0I晶片在热盘上烘干, 温度180摄氏度,时间60秒,去除光刻胶中残留的溶剂,如图5-a中左图所示; [0040] 2) S0I beam resist in a top surface of the wafer (a silicon oxide layer from the side closer I) coated with a 1 micron thick PMMA electrons spin coater speed of about 2000 rev / min, 20 seconds the glue S0I wafer baking on a hot plate, a temperature of 180 ° C, 60 seconds, removing the solvent remaining in the photoresist, as shown in the left half shown in FIG. 5-a;

[0041] 3)如图5-a中右图所示,在一块载玻片1上涂覆环氧树脂胶2,将S0I晶片放在环氧树脂胶2上,且使S0I晶的顶面面对载玻片1,然后继续在S0I晶片的背面涂覆环氧树脂, 使S0I晶片包裹在环氧树脂中,5到10分钟后,环氧树脂固化,形成严密的半透明状的环氧树脂包裹层3,如图5-b所示; [0041] 3) shown in FIG. 5-a shown in the right, a slide 1 is coated on the epoxy resin adhesive 2, the wafer is placed epoxy S0I 2, and that the top surface of the crystal S0I a slide face, then continue on the back surface of the epoxy coated wafer S0I the wafer S0I wrapped in an epoxy resin, 5 to 10 minutes later, the epoxy resin cured to form a tight translucent epoxy wrapping the resin layer 3, as shown in FIG. 5-b;

[0042] 4)用机械钻在S0I晶片背面(距离氧化硅层I较远的一面)的环氧树脂包裹层3中钻出孔4,该孔4穿过环氧树脂包裹层3并达到S0I晶片背面的硅衬底中,如图5-c所示; [0042] 4) Mechanical drill S0I wafer back surface (the silicon oxide layer from the side farther I) an epoxy resin layer 3 wrapping drilled hole 4, through the aperture 4 wrap layer 3 and reaches the epoxy S0I wafer back surface of the silicon substrate, as shown in 5-c;

[0043] 5)将步骤4)得到的样品放入80摄氏度质量浓度26%的氢氧化钾水溶液中,该强碱溶液穿过包裹层3中的孔4沿着〈100〉晶向(即垂直方向)对硅衬底进行腐蚀,反应产生大量氢气,不断搅动溶液以促进排气(也可以在该强碱溶液中加入异丙醇,减小氢气气泡的大小,以便于气体的排出),约2-3个小时后,硅衬底被腐蚀掉,氧化硅绝缘层I成为腐蚀停止层,露出半透明的“硅_氧化硅”薄膜,如图5-d所示; [0043] 5) The Step 4) The obtained samples were placed in 80 ° C aqueous solution of 26% potassium hydroxide concentration in the alkali solution through the wrapping layer 3 hole 4 along the <100> crystal orientation (i.e., vertical direction) of the silicon substrate is etched, the reaction produce large amounts of hydrogen, the solution was agitated constantly to facilitate the exhaust gas (isopropyl alcohol may also be added to the alkaline solution, reducing the size of the hydrogen bubbles, so that the exhaust gas), approximately after 2-3 hours, the silicon substrate is etched, the silicon oxide insulating layer I of the etch stop layer to expose a translucent "_ silicon oxide silicon" film, as shown in FIG. 5-d;

[0044] 6)用刀沿A1方向切去S0I晶片背面的环氧树脂,再用刀沿A2方向切去SOI晶片MSSOI PMMA 3 [0044] 6) an epoxy resin S0I knife cut wafer back surface in the direction A1, A2 and then a knife cut in the direction SOI wafer MSSOI PMMA 3

5-epjf^ ; 5-epjf ^;

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3 ¿ 3 ¿ ilWfiï-m^ïê^m 5-fp/î^ ; ilWfiï-m ^ ïê ^ m 5-fp / î ^;

[0046] 8) mPM 7) Î#ilJW#Bnn^AïfÜM«^[J^, 3 WÒMI, [0046] 8) mPM 7) Î # ilJW # Bnn ^ AïfÜM «^ [J ^, 3 WÒMI,

ïïMfè soi 3 5-gpfi^,ìmxìf^mm3mmÄtMSHWsoi 0aH>to ïïMfè soi 3 5-gpfi ^, ìmxìf ^ mm3mmÄtMSHWsoi 0aH> to

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[0048] [0048]

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(6.0X IO5/ C), » Xiil % SOI 00 J4Í¥m!ít®'Ëlllb X^ÜÉliê» (6.0X IO5 / C), »Xiil% SOI 00 J4Í ¥ m! Ít®'Ëlllb X ^ ÜÉliê»

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Mo Mo

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[0050] m ig ^ 'R m âtJ ■—^ $ MM, Ä ^ ïf ü MIh& MB % iS >t T® ffl ¿ [0050] m ig ^ 'R m âtJ ■ - ^ $ MM, Ä ^ ïf ü MIh & MB% iS> t T® ffl ¿ Íh] âtJ ±1 ^5 14 Íh] âtJ ± 1 ^ 5 14

XKXPMMA,M^®nT^Ä S1813 Mt^Ä, IÜ5 fój S1813 Mt^ÄÄ 3-7.6X IO“6/“C, til ni L^ÂÂÎtkM^ , iÀMfô XKXPMMA, M ^ ®nT ^ Ä S1813 Mt ^ Ä, IÜ5 fój S1813 Mt ^ ÄÄ 3-7.6X IO "6 /" C, til ni L ^ ÂÂÎtkM ^, iÀMfô

10x io~5/°CfàJtMl5° »fflTí#IWüMlH^^M%5Í0a0>tT®ffl¿ 10x io ~ 5 / ° CfàJtMl5 ° »fflTí # IWüMlH ^^ M% 5Í0a0> tT®ffl¿ Í0]W±l^tì$4 Wí# Í0] W ± l ^ tì $ 4 Wí #

[0051] soi参数的组合。 [0051] parameter combinations soi.

[0052] 根据本发明的一个实施例,其中上述载玻片也可以替换为其他的载体,以防止“硅_氧化硅”薄膜层受到顺坏,该载体优选由透明且具有一定机械强度的材料构成。 [0052] a material embodiment of the present invention, wherein said slide may be replaced with another carrier, in order to prevent "_ a silicon oxide silicon" by the thin film layer will destroy, the support is preferably transparent and has a certain mechanical strength in accordance with constitution.

[0053] 根据本发明的一个实施例,上述步骤4)中,用机械钻钻出的孔4至少穿透环氧树脂包裹层3,并且在不到达“硅-氧化硅”薄膜层的前提下,优选为尽可能的深,从而缩短湿法腐蚀的时间。 [0053] According to one embodiment of the present invention) in the above step 4, with 4 holes drilled mechanically drilled epoxy wrap layer penetrates at least 3, and does not reach - the premise "the silicon oxide silicon" thin film layer preferably deep as possible, thereby shortening the time of wet etching. 另外,在其他实施例中,在SOI晶片中形成开口不限于上述孔4的形状,可根据实际需要设计多种图案化开口,例如线状等,并利用机械的方法在环氧树脂包裹层3中形成相应形状的开口,进而通过湿法腐蚀在硅衬底中形成相应形状的开口。 Further, in other embodiments, the method is not limited to the shape of the opening of the hole 4, the opening may be designed according to actual needs of various patterns, such as linear, etc., and the epoxy resin using a mechanical wrapping layer 3 is formed in the SOI wafer correspondingly shaped opening is formed, thereby forming a correspondingly shaped opening in the silicon substrate by wet etching.

[0054] 根据本发明的一个实施例,其中利用机械的方法在环氧树脂包裹层3中形成各种形状的开口是本领域公知常识,例如可通过将SOI晶片固定到可移动样品台上,并借助钻机在SOI晶片的背面刻画出任意形状的开口。 [0054] According to one embodiment of the present invention, wherein using a mechanical method of forming the various shapes of the opening 3 in the epoxy encapsulation layer is common knowledge in the art, for example by the SOI wafer is fixed to a movable sample stage, and with the back surface of the SOI wafer rig depicts the opening of any shape.

[0055] 根据本发明的一个实施例,其中在环氧树脂包裹层3中形成开口的方法不限于机械的方法,也可以为其他的物理的或化学的方法等。 [0055] According to an embodiment of the present invention, a method wherein the method is not limited to an opening formed in the mechanical layer 3 of epoxy resin package, and the like may also be other physical or chemical method.

[0056] 本发明提供的方法中,用廉价快速的湿法腐蚀替代使用昂贵设备的干法刻蚀,大大降低了对绝缘体上硅晶片进行衬底去除处理的成本,为批量化生产具有特殊光学性能的绝缘体上硅晶片提供了可行方案。 [0056] The method of the present invention provides, instead of the use of expensive equipment with an inexpensive wet etching quick dry etching, greatly reducing the cost of the silicon on insulator wafer substrate removal process, having a specific mass production of optical performance silicon on insulator wafer provide a viable solution. 且只在绝缘体上硅晶片的部分区域去除衬底,整个芯片仍旧保留了硅基底,因而可以与CMOS工业标准匹配,这与将整个衬底置换为其他材料的石英体上硅技术完全不同。 And removing only a partial region of the silicon on insulator wafer substrate, still retained the entire chip silicon substrate, it is possible to match the industry standard CMOS on silicon technology which will be replaced with other substrate materials throughout the silica body is completely different.

[0057] 本发明提供的方法还可以应用到其他的硅基层状晶片中去,比如绝缘体上错(GeOI, Germanium On Insulator),绝缘体上碳化娃(SiCOI, Silicon Carbide On Insulator),绝缘体上氮化硅(Si3N4)等等,用于从背面腐蚀掉Si衬底而露出Si衬底顶面的功能层。 [0057] The present invention provides a method may also be applied to other silicon wafer to a layer, such as wrong insulator (GeOI, Germanium On Insulator), baby carbide on insulator (SiCOI, Silicon Carbide On Insulator), the nitride insulator silicon (Si3N4) etc., for the functional layer to expose the top surface of the substrate Si etching away from the back surface of the Si substrate.

[0058] 最后所应说明的是,以上实施例仅用以说明本发明的技术方案而非限制。 [0058] Finally, it should be noted that the above embodiments are intended to illustrate and not limit the present invention. 尽管参照实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,对本发明的技术方案进行修改或者等同替换,都不脱离本发明技术方案的精神和范围,其均应涵盖在本发明的权利要求范围当中。 While the reference to the present invention, a detailed description of the embodiments, those of ordinary skill will appreciate, modifications to the technical solutions of the present invention, or equivalent replacements without departing from the spirit and scope of the technical solutions of the present invention, which should be encompassed by the present invention, among the scope of the claims.

Claims (10)

1.一种湿法腐蚀Si衬底的方法,包括:1)在与Si衬底相反一侧的功能层上涂覆光刻胶层,并使其干燥;2)在Si衬底及功能层外周形成环氧树脂包裹层;3)在Si衬底侧的包裹层中形成开口,暴露娃衬底;4)利用刻蚀剂对暴露的硅衬底进行腐蚀;5)暴露出涂覆在功能层上的光刻胶层,使该光刻胶层溶解;6)使所述环氧树脂包裹层脱落。 A method of wet etching a Si substrate, comprising: 1) in the Si substrate coated with a photoresist layer on the opposite side of the functional layer, and drying; 2) in the Si substrate and the functional layer wrapping the outer periphery of the epoxy layer is formed; 3) forming an opening in the side of the Si substrate layer wrapping, the baby is exposed substrate; 4) by using an etchant for etching the exposed silicon substrate; 5) in the functional coating is exposed photoresist layer on the layer so that the resist layer is dissolved; 6) wrapping the epoxy layer off.
2.根据权利要求1所述的方法,其中所述光刻胶为PMMA。 2. The method according to claim 1, wherein the photoresist is PMMA.
3.根据权利要求1所述的方法,其中所述光刻胶干燥后的热膨胀系数小于10X10_5/°C。 3. The method according to claim 1, wherein the thermal expansion coefficient of the photoresist after drying is less than 10X10_5 / ° C.
4.根据权利要求1所述的方法,其中所述光刻胶为S1813型光刻胶。 4. The method according to claim 1, wherein the photoresist is a photoresist S1813.
5.根据权利要求1所述的方法,其中采用机械方法在Si衬底侧的包裹层中形成开口。 5. The method according to claim 1, wherein the mechanical means forming an opening in the side wrapping layer of the substrate and Si.
6.根据权利要求1所述的方法,其中在所述包裹层中的所述开口的深度到达Si衬底中。 6. The method according to claim 1, wherein the depth of said wrapping layer in the opening reaching the Si substrate.
7.根据权利要求1所述的方法,其中步骤2)中,还包括将包裹有环氧树脂包裹层的Si 衬底和功能层粘附在载体上,且使功能层一侧朝向该载体。 7. The method according to claim 1, wherein in step 2), the package further comprising a Si substrate and the functional layer package epoxy layer adhered to the carrier, and that the functional layer side towards the carrier.
8.根据权利要求1所述的方法,其中步骤5)中,通过去掉所述包裹层的至少一部分而暴露出所述光刻胶层。 8. The method according to claim 1, wherein step 5), by removing at least a portion of said wrapping layer to expose the photoresist layer.
9.根据权利要求1所述的方法,其中该方法腐蚀的对象为硅基层状晶片。 9. The method according to claim 1, wherein the object is a method of etching a silicon wafer layer.
10.根据权利要求1所述的方法,其中该方法腐蚀的对象为绝缘体上锗、绝缘体上碳化娃、绝缘体上氮化娃或绝缘体上娃。 10. The method according to claim 1, wherein the method of etching an object germanium on insulator, insulator carbide baby, the baby doll nitride insulator or an insulator.
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CN106848809A (en) * 2017-03-06 2017-06-13 李志远 A kind of generation is visible to infrared band pole broadband, the device of super continuous laser

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CN1828422A (en) * 2005-03-04 2006-09-06 中芯国际集成电路制造(上海)有限公司 Minute pattern photoetching method

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US5899750A (en) * 1996-03-12 1999-05-04 Denso Corporation Fine processing method
JP2004109296A (en) * 2002-09-17 2004-04-08 Toppan Printing Co Ltd Photosensitive hot melt resist and etching method using same
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Publication number Priority date Publication date Assignee Title
CN106848809A (en) * 2017-03-06 2017-06-13 李志远 A kind of generation is visible to infrared band pole broadband, the device of super continuous laser

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