CN103390539B - Preparation of thin silicon - Google Patents

Preparation of thin silicon Download PDF

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CN103390539B
CN103390539B CN 201210145549 CN201210145549A CN103390539B CN 103390539 B CN103390539 B CN 103390539B CN 201210145549 CN201210145549 CN 201210145549 CN 201210145549 A CN201210145549 A CN 201210145549A CN 103390539 B CN103390539 B CN 103390539B
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silicon
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thickness
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CN103390539A (en )
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孟鸿林
郭晓波
刘尧
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上海华虹宏力半导体制造有限公司
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Abstract

本发明公开了一种薄硅片的制备方法,包括步骤:1)在传统厚度的硅片上生长氮化硅或氮氧化硅;2)在硅片背面涂光刻胶,硅片周边曝光、显影,使光刻胶只保留在硅片背面的周边;3)在硅片背面无光刻胶的地方刻蚀沟槽;4)在沟槽内填充导电导热材料;5)在导电导热材料上再封一层绝缘材料,后续按照传统工艺流程完成薄硅片的制备。 The present invention discloses a method for producing a thin silicon wafer, comprising the steps of: 1) growing a silicon nitride or silicon oxynitride on silicon wafers of a conventional thickness; 2) at the wafer backside resist coating, exposing the wafer periphery, developing the photoresist remains only the peripheral rear surface of the silicon wafer; 3) at the wafer backside where no etching resist trenches; 4) filled with electrically and thermally conductive material in the trench; 5) on the electrically and thermally conductive material, resealable layer of insulating material, the thin silicon prepared according to conventional processes to complete the follow-up. 本发明通过在硅片背面挖沟槽填充金属材料或者绝缘材料,有效降低了硅片减薄后带来的大翘曲度问题,使硅片的厚度得以降低到20~500μm;另外,本发明以现有工艺为基础,可以充分利用现有生产线,从而减少了设备开支,降低了生产成本。 The present invention, by digging a trench in the wafer backside filler metal material or an insulating material, effectively reduces the problem of large warpage after wafer thinning caused by the thickness of the wafer is reduced to 20 ~ 500μm; Further, the present invention in the conventional technology as the basis, we can make full use of existing production lines, reducing equipment costs, reducing production costs.

Description

薄硅片的制备方法 Preparation of thin silicon

技术领域 FIELD

[0001]本发明涉及半导体集成电路制造领域,特别是涉及一种薄硅片的制备方法。 [0001] The present invention relates to a semiconductor integrated circuit manufacturing, and more particularly relates to a method for producing a thin silicon wafer.

背景技术 Background technique

[0002]硅片上电路层的有效厚度一般为5〜ΙΟμπι,为了保证其功能,有一定的支撑厚度是必要的,因此,娃片上电路层的厚度极限为20〜30μηι。 [0002] The effective thickness of the circuit layer on the silicon wafer is generally 5~ΙΟμπι, in order to ensure its function, a certain thickness of the support is necessary, therefore, limits the thickness of the circuit layer sheet Wa is 20~30μηι. 而20〜30μηι只占娃片总厚度的一小部分,占总厚度90%左右的是衬底材料,是为了保证硅片在制造、测试和运送过程中有足够的强度。 20~30μηι while only a small portion of the total thickness of the sheet baby, about 90% of the total thickness of the substrate material, a silicon wafer is to ensure sufficient strength in the manufacture, testing and delivery process. 因此,在电路层制作完成后,需要对娃片进行背面减薄(backside thinning),使其达到所需的厚度,然后再对硅片进行划片(Dicing)加工,形成一个个减薄的裸芯片。 Thus, after the circuit layer is finished, the baby needs to be backside thinned sheet (backside thinning), to reach the desired thickness, then the silicon wafer is diced (Dicing) processing, forming a thinned bare chip.

[0003]减薄后的芯片有如下优点: [0003] the thinned chip has the following advantages:

[0004] (I)提高热扩散效率。 [0004] (I) improve the efficiency of the thermal diffusion. 随着半导体结构越来越复杂,集成度越来越高,晶体管体积不断减小,散热已逐渐成为影响芯片性能和寿命的关键因素,薄的芯片更有利于散热。 As semiconductor structure more complex, more integrated, transistor sizes continue to decrease, heat dissipation has become a key factor affecting the performance and life of the chip, a thin chip is more conducive to heat.

[0005] (2)减小芯片封装体积。 [0005] (2) reducing the volume of the chip package. 微电子产品日益向轻薄短小的方向发展,减小芯片封装体积是适应这一发展趋势的必由之路。 Microelectronic products to increasingly slim and light direction, the only way to reduce the volume of the chip package is to adapt to this trend.

[0006] (3)提高机械性能。 [0006] (3) improve mechanical properties. 减薄后的芯片机械性能显著提高,硅片越薄,其柔韧性越好,受外力冲击引起的应力也越小。 Mechanical properties of the thinned chip significantly increased, thinner wafers, the better its flexibility, shock caused by the external stress is also smaller.

[0007] (4)提高电气性能。 [0007] (4) improving electrical performance. 晶片的厚度越薄,元件之间的连线将越短,元件导通电阻将越低,信号延迟时间越短,从而实现更高的性能。 The thinner the thickness of the wafer, the connection between the elements will be the shorter, the element will lower the ON resistance, the shorter signal delay time, in order to achieve higher performance.

[0008] (5)减轻划片加工量。 [0008] (5) reduce the amount of processing dicing. 减薄以后再切割,可以减小划片(Dicing)时的加工量,降低芯片崩边的发生率。 After the re-cut thinning can reduce the processing amount during dicing (Dicing), reducing the incidence of chipping of the chip.

[0009]目前,硅片的背面减薄技术主要有磨削、研磨、化学机械抛光(CMP)、干式抛光(drypolishing)、电化学腐蚀(electro chemical etching)、湿法腐蚀(wet etching)、等离子辅助化学腐蚀(PACE)、常压等离子腐蚀(atmospheric downstream plasma etching,ADPE)等,其中最常用的背面减薄技术有磨削、CMP、湿法腐蚀、ADPE和干式抛光五种。 [0009] Currently, the back of the wafer thinning technologies include grinding, polishing, chemical mechanical polishing (the CMP), dry polishing (drypolishing), electrochemical etching (electro chemical etching), wet etching (wet etching), plasma-assisted chemical etching (the PACE), atmospheric pressure plasma etching (atmospheric downstream plasma etching, ADPE) and the like, the most commonly used techniques are thinning the back surface grinding, CMP, wet etching, dry polishing, and five kinds of ADPE.

[0010] CMP工艺能极大地提高硅片的强度,减小翘曲,其缺点是需对硅片的正面进行保护,对磨削条纹的校正能力弱,不适合加工有凸起的娃片(bumped wafer),腐蚀速度快(去除率为5〜40mm/min)且不均匀(为腐蚀量的5 %〜10 % ),存在环境污染问题。 [0010] CMP process can greatly improve the strength of the silicon wafer, warpage is reduced, the drawback is the need to protect the wafer front side correction capability weak grinding stripes, are not suitable for processing with a raised piece baby ( bumped wafer), fast etching rate (removal rate of 5~40mm / min) and inhomogeneous (5% ~ 10% of the amount of corrosion), there is a problem of environmental pollution.

[0011]常压等离子腐蚀是新近发展起来的、利用磁力控制的在大气压力下工作的一种纯化学作用的干式腐蚀技术,在氩气环境下ADP系统将四氟化碳气体引入等离子区,使之100%分解,F(氟)与硅片表面的材料发生化学反应生成SiF4,达到去除材料的目的;加工时,利用Bernoulli效应产生的压力将硅片悬置于等离子区上方,硅片的正面不必像湿式腐蚀那样需用胶带保护,因此,适合加工较薄的硅片,也适合加工有凸起的硅片。 Dry etching techniques [0011] atmospheric-pressure plasma etching is a newly developed, using a purely chemical action of the magnetic force control operating at atmospheric pressure, under argon atmosphere system ADP carbon tetrafluoride gas into plasma to make 100% decomposed, SiF4 material F (fluorine) and the chemical reaction of the surface of the wafer, the purpose of removing material; ion over the processing zone by the pressure generated by the Bernoulli effect and the like suspended in the silicon wafer, the silicon wafer not like the front tape wet etching protection as required, therefore, suitable for processing thin wafers, but also silicon wafer suitable for processing with raised.

[0012] ADPE能够去除硅片背面由于磨削引起的损伤层,加工速度为I〜4mm/min,背面去除量可达50〜ΙΟΟμπι,加工后的表面平整性比湿式腐蚀好。 [0012] ADPE possible to remove the damage layer due to the back surface of the silicon wafer caused by grinding, machining speed was I~4mm / min, up to the back of removal 50~ΙΟΟμπι, after working surface flatness better than wet etching.

[0013]干式抛光是新出现的去除硅片应力的技术,其加工原理类似于硅片磨削,与磨削不同之处是用纤维和金属氧化物制成的抛光轮取代了金刚石砂轮。 [0013] Dry polishing technique for removing a silicon wafer stress is emerging, the processing principle is similar to a silicon wafer grinding, buff grinding differs from the fiber is made of a metal oxide and a substituted diamond wheel. 干式抛光能有效地去除硅片背面磨削引起的残余应力,成本低,但加工效率低,加工速度仅为lmm/min,只适合去除较浅的损伤层。 Dry polishing can effectively remove the residual stress caused by the wafer back grinding, low cost, low processing efficiency, the processing speed is only lmm / min, only for the removal of the damaged layer shallow.

[0014]硅片的原始厚度一般为675〜775μπι,最终要减薄到100〜200μπι,有时甚至要减薄到50μπι。 [0014] the original thickness of the silicon wafer is generally 675~775μπι, eventually thinned to 100~200μπι, sometimes even to the thinning 50μπι. 在硅片减薄工艺中一般不能将硅片磨削到很薄的尺寸,因为如果将硅片直接磨削到芯片封装所需的厚度,由于机械损伤层的存在,在运输和后序工艺中碎片率非常高。 Wafer thinning process in general can not be ground to a thin wafer size, because if the wafer is directly ground to the desired thickness of the chip package, due to mechanical damage layer, transport and subsequent processes fragmentation rate is very high. 因此,实际应用中,对于200μπι的硅片,如果需要ΙΟΟμπι的薄硅片,首先先用磨削的方式去除绝大部分余量,背面减薄到180μπι左右,然后用CMP、湿法腐蚀、ADPE和干式抛光中的一种或两种消除磨削引起的损伤层和残余应力,得到无损伤的片表面。 Thus, the practical application, for 200μπι the wafer, a thin silicon ΙΟΟμπι if necessary, first to remove most of the remaining amount by grinding manner, the back thinned to about 180μπι, and then the CMP, wet etching, ADPE and dry polishing of one or both of the damaged layer and eliminating residual stresses caused by grinding, to obtain the sheet surface without damage.

发明内容 SUMMARY

[0015]本发明要解决的技术问题是提供一种薄硅片的制备方法,它可以避免减薄后的硅片出现大翘曲度问题,并可以降低硅片的厚度和生产成本。 [0015] The present invention is to solve the technical problem is to provide a method for preparing a thin silicon wafer, the wafer warpage of the big problems that can be avoided after the thinning, and wafer thickness can be reduced and production costs.

[0016]为解决上述技术问题,本发明的厚度为20〜500μπι的薄硅片的制备方法,包括以下步骤: [0016] To solve the above problems, the present invention is the thickness of the thin silicon 20~500μπι preparation, comprising the steps of:

[0017] I)在厚度为675〜775μπι的硅片上生长一层氮化硅或氮氧化硅; [0017] I) in thickness grown on the silicon nitride layer or silicon oxynitride 675~775μπι;

[0018] 2)在硅片背面涂上一层光刻胶,然后在硅片周边曝光、显影,使光刻胶只保留在硅片背面的周边; [0018] 2) coated with a layer of photoresist on wafer backside, then exposed to the surrounding silicon, developing, the photoresist remains only the peripheral rear surface of the silicon wafer;

[0019] 3)在硅片背面无光刻胶的地方刻蚀沟槽,沟槽的深度为步骤I)中的硅片厚度减去所述薄硅片的厚度; [0019] 3) etching the silicon wafer without photoresist on the back surface where the groove depth of the trench to step I) of the wafer thickness minus the thickness of the thin silicon wafer;

[0020] 4)在沟槽内填充导电导热材料; [0020] 4) filled with electrically and thermally conductive material within the trench;

[0021] 5)在所述导电导热材料上再封一层绝缘材料,然后生长氮氧化物,完成薄硅片的制备。 [0021] 5) recloseable layer of insulating material on the electrically and thermally conductive material, and then the nitrogen oxide growth, thin silicon preparation is completed.

[0022]本发明通过在硅片背面挖沟槽填充金属材料和绝缘材料,有效降低了硅片减薄后带来的大翘曲度问题,使硅片的厚度得以降低到20〜500μπι;另外,本发明以现有工艺为基础,可以充分利用现有的生产线,从而减少了庞大的设备开支,降低了产品的生产成本。 [0022] The present invention has been reduced by the thickness of the wafer backside trenches dug in the filler metal material and an insulating material, effectively reduces the problem of large warpage after wafer thinning brought to a silicon wafer 20~500μπι; Further the present invention is based on existing technology can make full use of existing production lines, thereby reducing the bulky equipment costs, reducing the production cost.

附图说明 BRIEF DESCRIPTION

[0023]图1是本发明实施例的工艺流程示意图。 [0023] FIG. 1 is a process flow diagram of an embodiment of the present invention.

具体实施方式 detailed description

[0024]为对本发明的技术内容、特点与功效有更具体的了解,现结合图示的实施方式,详述如下: [0024] The more specific understanding of the technical details, features and effects of the present invention are combined with the illustrated embodiment, as detailed below:

[0025]本实施例的薄硅片的制备方法,包括以下工艺步骤: [0025] The production method of the present embodiment of the thin silicon, comprising the following process steps:

[0026] 步骤I,在厚度为725μπι、直径为200mm的硅片的正面生长一层氮化硅,如图1(a)所不O [0026] Step I, in the thickness of the wafer front side 725μπι, 200mm diameter growth layer of silicon nitride, as shown in FIG 1 (a) are not O

[0027]硅片的类型,除上述尺寸外,还可以使用现有的工业标准的各种尺寸硅片,例如4寸、6寸、8寸、12寸等。 [0027] type silicon, in addition to the dimensions, may be used conventional industry standards for all wafer diameters, e.g., 4 inch, 6 inch, 8 inch, 12 inch.

[0028]氮化硅用LPCVD(低压化学气相沉积)工艺淀积而成,其厚度视后面要刻蚀的氧化物厚度而定。 [0028] The silicon nitride with LPCVD (Low Pressure Chemical Vapor Deposition) deposited by the process, which depends on the thickness to be etched later on the thickness of the oxide.

[0029]步骤2,在硅片背面涂上一层负性光刻胶,然后将硅片周边曝光、显影,使光刻胶只保留在硅片背面的周边,如图1(b)所示。 [0029] Step 2, the back surface of the silicon wafer coated with a negative photoresist, and the wafer peripheral exposure, developing, the photoresist remains only on the back of the periphery of the wafer, FIG. 1 (b) shown in FIG. .

[0030] 所保留的光刻胶宽度为I〜5臟,厚度为1nm〜ΙΟΟμπι。 [0030] retained photoresist I~5 dirty width, thickness 1nm~ΙΟΟμπι.

[0031] 涂胶机台为TEL ACT-8。 [0031] The coating machine for the TEL ACT-8. 曝光机台为Nikon 1-14,曝光能量为20mj/cm2。 Exposure machine as Nikon 1-14, an exposure energy of 20mj / cm2.

[0032] 步骤3,在60°C下,用30 % (质量百分比浓度)的KOH水溶液,在振动恒温槽中进行湿法刻蚀(也可以用其他方法刻蚀硅片基板),在硅片背面刻蚀出一个略小于硅片的沟槽,如图1(c)所示。 [0032] Step 3, at 60 ° C, with 30% (mass concentration) of the aqueous KOH solution, wet etching (etching methods can also use other silicon wafer substrate) in a constant temperature bath vibration in silico a backside etch trenches slightly smaller than the wafer, FIG. 1 (c) shown in FIG.

[0033]沟槽的深度等于步骤I中的正常硅片的厚度减去实际需要的硅片厚度,例如,需要10ym厚度的硅片,我们就需要刻蚀725-100 = 625μπι深的沟槽。 [0033] The depth of the grooves equal to the thickness of a normal silicon wafer in step I wafer thickness minus the actual needs, for example, silicon 10ym required thickness, we need to etch deep trenches 725-100 = 625μπι.

[0034]步骤4,用干法(也可以用其他刻蚀方法)刻蚀硅片基板,进一步将沟槽刻蚀均匀光滑,如图1(d)所示。 [0034] Step 4, by a dry method (etching method may also be other) etching the silicon substrate, the trench etch is further uniform and smooth, as shown in FIG 1 (d) shown in FIG.

[0035] 干法刻蚀采用等离子(plasma)刻蚀方法,刻蚀气体为SF4和O2的混合气体。 [0035] The dry etching using plasma (Plasma) etching method, etching gas is a mixed gas of O2 and SF4.

[0036]步骤5,在沟槽中填充氧化物(例如二氧化硅)或其他导电导热材料,如图1(e)所示; [0036] Step 5, in the trench filling oxide (e.g. silicon dioxide), or other electrically and thermally conductive material, as shown in FIG 1 (e) below;

[0037]步骤6,在沟槽内的填充物上再封一层PMMA(聚丙烯酸甲酯)或者其他绝缘材料,如图1(f)所示。 [0037] Step 6, and then sealing the fill in the trench layer PMMA (polymethyl acrylate), or other insulating material, FIG. 1 (f) shown in FIG.

[0038]步骤7,后续按照传统工艺流程完成薄硅片的制备。 [0038] Step 7, a subsequent process according to the traditional preparation of thin silicon completed. 如此制备得到的薄硅片的厚度可以低至20〜500μηι,且不存在大翘曲度的问题。 The thickness of the thus prepared thin silicon may be as low 20~500μηι, the problem and there is no large degree of warpage.

[0039]硅片背面残留的PMMA等绝缘材料和氧化物可以在后面生长氮氧化物之后,做最后的焊垫光刻工艺流程之前去除。 [0039] back surface of the silicon wafer remaining PMMA and insulating material such as an oxide may grow back after the nitrogen oxides, is removed prior to final bonding pad photolithography process. 氧化物可以用有机溶剂(如苯酚、苯甲醚、氧化物)去除,典型的做法是:用HF与H2O比例为1:10的氢氟酸漂洗(漂洗时间根据要漂去的氧化物的厚度而定);溢流5分钟;冲水10次;甩干。 Oxide may be an organic solvent (e.g. phenol, anisole, oxide) is removed, the typical approach is: HF and H2O with a ratio of 1:10 hydrofluoric acid rinsing (rinsing time according to the thickness of the drift oxide be); overflow 5 minutes; flush 10 times; drying.

Claims (10)

  1. 1.薄娃片的制备方法,所述薄娃片的厚度为20〜500μηι,其特征在于,包括以下步骤: 1)在厚度为675〜775μηι的娃片上生长一层氮化娃或氮氧化娃; 2)在硅片背面涂上一层光刻胶,然后在硅片周边曝光、显影,使光刻胶只保留在硅片背面的周边; 3)在硅片背面无光刻胶的地方刻蚀沟槽,沟槽的深度为步骤I)中的硅片厚度减去所述薄硅片的厚度; 4)在沟槽内填充氧化物或导电导热材料; 5)在所述氧化物或导电导热材料上再封一层绝缘材料,然后生长氮氧化物,完成薄硅片的制备。 A method for producing a thin sheet Wa, the thickness of the thin sheet Wa 20~500μηι, characterized in that it comprises the following steps: 1) is grown in the thickness of one baby doll sheet 675~775μηι nitride or oxynitride doll ; 2) coated with a layer of photoresist on the back of the wafer, then exposed to the surrounding silicon, developing, the photoresist remains only the peripheral rear surface of the silicon wafer; 3) at the wafer backside where no resist moment trench etching, the trench depth for step I) of the wafer thickness minus the thickness of the thin silicon wafer; 4) within the trench filling oxide or electrically and thermally conductive material; 5) or the conductive oxide resealable heat conductive material on the layer of insulating material, and then the nitrogen oxide growth, thin silicon preparation is completed.
  2. 2.根据权利要求1所述的方法,其特征在于,步骤I),所述硅片的厚度为725μπι,直径为200mmο 2. The method according to claim 1, wherein the I step), a silicon wafer having a thickness of 725μπι, diameter 200mmο
  3. 3.根据权利要求1所述的方法,其特征在于,步骤I),采用低压化学气相沉积工艺生长氮化硅或氮氧化硅。 3. The method according to claim 1, wherein the I step), low pressure chemical vapor deposition growth of silicon nitride or silicon oxynitride.
  4. 4.根据权利要求1所述的方法,其特征在于,步骤2),所述光刻胶为负性光刻胶。 4. The method according to claim 1, wherein step 2), the photoresist is a negative photoresist.
  5. 5.根据权利要求1所述的方法,其特征在于,步骤2),所保留的光刻胶的宽度为I〜5mm,厚度为10nm〜100ymo 5. The method according to claim 1, wherein step 2), the width of the resist reserved for I~5mm, thickness 10nm~100ymo
  6. 6.根据权利要求1所述的方法,其特征在于,步骤3),首先用湿法刻蚀方法刻蚀出沟槽,然后用干法刻蚀方法将所述沟槽进一步刻蚀均匀光滑。 6. The method according to claim 1, wherein step 3), is first etched by a wet etching method trenches, then using a dry etching method to etch the trench further uniform and smooth.
  7. 7.根据权利要求6所述的方法,其特征在于,步骤3),所述湿法刻蚀方法为:在60 °C下,用质量百分比浓度为30%的氢氧化钾水溶液,在振动恒温槽中进行刻蚀。 7. The method according to claim 6, wherein step 3), the wet etching method as follows: at 60 ° C, with a mass concentration of 30% aqueous potassium hydroxide solution, in the vibration thermostat etching bath.
  8. 8.根据权利要求6所述的方法,其特征在于,步骤3),所述干法刻蚀方法为等离子刻蚀,刻蚀气体为SF4和O2的混合气体。 8. The method according to claim 6, wherein step 3), the dry etching method is plasma etching, etching gas is a mixed gas of SF4 and O2.
  9. 9.根据权利要求1所述的方法,其特征在于,步骤4)和步骤5)中,所述氧化物为氧化硅。 9. The method according to claim 1, wherein the step 4) and step 5), the oxide is silicon oxide.
  10. 10.根据权利要求1所述的方法,其特征在于,步骤5 ),所述绝缘材料为聚丙烯酸甲酯。 10. The method according to claim 1, wherein step 5), said insulating material is a polymethyl acrylate.
CN 201210145549 2012-05-11 2012-05-11 Preparation of thin silicon CN103390539B (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
CN101350332A (en) * 2007-07-20 2009-01-21 万国半导体股份有限公司 Ultra thin wafers having an edge support ring and manufacture method thereof

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US20080242052A1 (en) * 2007-03-30 2008-10-02 Tao Feng Method of forming ultra thin chips of power devices
US8084335B2 (en) * 2008-07-11 2011-12-27 Semiconductor Components Industries, Llc Method of thinning a semiconductor wafer using a film frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
CN101350332A (en) * 2007-07-20 2009-01-21 万国半导体股份有限公司 Ultra thin wafers having an edge support ring and manufacture method thereof

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