CN103296076A - Planar thyristor and chip and method for manufacturing planar thyristor - Google Patents
Planar thyristor and chip and method for manufacturing planar thyristor Download PDFInfo
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- CN103296076A CN103296076A CN2013102115804A CN201310211580A CN103296076A CN 103296076 A CN103296076 A CN 103296076A CN 2013102115804 A CN2013102115804 A CN 2013102115804A CN 201310211580 A CN201310211580 A CN 201310211580A CN 103296076 A CN103296076 A CN 103296076A
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Abstract
The invention relates to a planar thyristor and a chip and a method for manufacturing the planar thyristor. The thyristor comprises a shell, the chip and a frame. The chip comprises an N-type long base region N1, P-type short base regions P1 and P2, an isolation wall, a diffused phosphorous region N2 (or diffused phosphorous regions N2, N3 and N4), a field limiting ring and the like. Evaporated metal aluminum is diffused to form the isolation wall, and the isolation wall is applicable to unidirectional thyristor chips and bidirectional thyristor chips which are manufactured by planar processes. In a preferred scheme, metal aluminum is evaporated after sand blasting is performed on the surface of a silicon chip, and the isolation wall is formed after reverse photoetching, vacuum alloying and communicated isolation diffusion are completed. In another preferred scheme, a polycrystalline silicon film is deposited on a silicon chip after an isolation window is oxidized and photoetched, metal aluminum is evaporated, the width of the metal aluminum is consistent to that of the isolation window, and the isolation wall is formed after communicated isolation diffusion. The planar thyristor, the chip and the method have the advantage that the planar thyristor manufactured by the method is superior in performance and is stable and reliable.
Description
Technical field
The present invention relates to the thyristor technical field, relate to a kind of thyristor of planar technique in particular, for the manufacture of chip of thyristor and preparation method thereof.
Background technology
The power semiconductor device thyristor; mainly comprise shell, chip, framework three parts, its core is chip, and the anodic bonding of chip is connected on the framework; the gate pole of chip and negative electrode are wired to respectively on the corresponding pin of framework, and shell plays the effect of protection chip.The manufacture method of thyristor chip can be divided into by the technology classification: mesa technique and planar technique, mesa technique are divided into two mesa techniques and single table surface technology again;
1. two mesa techniques: because two mesa techniques do not adopt isolation diffusion, technology is simple relatively.But: 1. the silicon chip of this structure is broken easily in manufacturing process; 2. required cost is higher and technique controlling difficulty is bigger for the passivation protection of table top (semi-insulating polysilicon SIPOS+ glassivation+low temperature oxide LTO); 3. silicon chip its cutting-up efficient under the situation of using the emery wheel cutting-up is extremely low, and causes the chip breakage easily.4. chip is in package fabrication process, and the bonding die voidage causes chip reliability to reduce more greatly, and scolding tin is spilled over to and causes reverse voltage to lose efficacy in the backside trench, and product percent of pass reduces.
2. single table surface technology: the single table surface process using forms the insulation blocking wall to logical isolation technology, and the insulation blocking wall links to each other with the chip anode, realizes forward and reverse withstand voltage with the shared grooved table top of negative electrode.Meanwhile, divider wall also is public domain and the cutting-up zone that isolates adjacent chips, makes chip effectively overcome the shortcoming of two-sided cutting etch in manufacturing and encapsulation process.
3. planar technique: similar with single table surface technology, planar technique also adopts logical isolation technology is formed the insulation blocking wall, and N-type high resistance area and field limiting ring are tied the insulation blocking wall and kept apart (being junction termination structures) with P type master, forward and reverse withstand voltage to realize.Usually at more shallow deactivation slot of knot end surface etch, adopt SIPOS+LTO (or silicon nitride film)+polyimide multilayer passivation technology in the deactivation slot, effectively guarantee product good reliability and consistency.
Above-mentioned single table surface technology and planar technique all need the insulation blocking wall that chip is protected, and at present, realize that semiconductor power device has following two kinds to logical method of isolating: dense boron isolation diffusion method, laser beam perforation method.But all there is weak point separately in two kinds of methods:
⑴ dense boron isolation diffusion method:
1. (diffusion temperature is under 1200 ~ 1300 ℃ of conditions: the boron diffusion coefficient is about 1*10 owing to the impurity diffusion coefficient of boron in silicon is very slow
-11Cm
2/ S, and the aluminium diffusion coefficient is about 8*10
-11Cm
2/ S), the thickness of silicon chip can only be limited in below the 250um, and this make to adopt the device of dense boron isolation diffusion can only realize following withstand voltage of 1200V.
2. the diffusion temperature of dense boron isolation diffusion is higher, generally at 1250 ℃ ~ 1300 ℃, needs 120-200 hour diffusion time.Too high diffusion temperature and make long diffusion time the minority carrier life time of product shorten also can cause increasing of diffusion defect, causes the stability of product, reliability to reduce, and leakage current increases.Also cause long, power consumption height of production cycle simultaneously.
3. dense boron isolation diffusion causes higher (the general surface concentration R of logical isolated area impurity concentration
≤ 10), the PN junction depletion width reduces, and causes the reverse blocking voltage of product to reduce.
4. the horizontal proliferation of dense boron isolation diffusion is bigger, is generally 80% of diffusion depth, has reduced the effective area of chip, has reduced the on state current of product.
⑵ laser beam perforation method:
Utilize UV laser beam with certain spacing vertically perforation (the laser hole diameter can be regulated) on the divider wall around the chip, reach and accelerate the purpose that divider wall forms speed.But this method also has following deficiency:
1. the minimum needs of single silicon chip laser beam perforation moulding are 30 minutes, the less product required time longer (reaching 1.5 hours) of the chip space of a whole page particularly, and it is bigger to produce difficulty in batches.Operation processing such as follow-up process polishing cause fragment easily, and product percent of pass is low.
2. the diameter of laser hole less (diameter is generally 30-100um) usually, residual white residue is difficult to remove in the hole, pollutes easily, influences properties of product.
3. because divider wall is provided with vertical laser hole, during follow-up glass passivation protection, glass is filled out and is overlayed in the laser hole, causes the glass-film crackle during chip cutting-up easily, reduces qualification rate and the reliability of product.
Summary of the invention
The objective of the invention is to: provide a kind of for the chip that constitutes the plane thyristor, adopt evaporated metal aluminium films to realize logical method of isolating is made this thyristor chip by two kinds, so utilize that this thyristor chip produces that a kind of cost is low, with short production cycle, power consumption and pollute few superior performance, reliable and stable plane thyristor.
In order to achieve the above object, a technical scheme of the present invention provides a kind of chip for the manufacture of the plane thyristor;
This chip comprises during for the manufacture of unidirectional thyristor:
Be positioned at the middle N-type growing base area N1 of chip, be arranged on the short base P1 of a P type of N-type growing base area N1 downside, be arranged on the short base P2 of the 2nd P type of N-type growing base area N1 upside;
On the short base P2 of the 2nd P type that is arranged on first expands phosphorus zone N2, is arranged on first negative electrode that expands on the N2 of phosphorus zone; Gate pole on the short base P2 of the 2nd P type that is arranged on; Anode on the short base P1 of the P type that is arranged on;
Be arranged on the divider wall of N-type growing base area N1 periphery, the field limiting ring between the short base P2 of the 2nd P type that is arranged on and the divider wall, it is characterized in that: described divider wall is diffuseed to form by evaporated metal aluminium.
This chip further also is provided with the 3rd and expands phosphorus zone N4 during for the manufacture of the bidirectional thyristor chip on the short base P1 of a described P type; Then described anode is arranged on the short base P1 of a described P type and described the 3rd expansion phosphorus zone N4;
On the short base P2 of described the 2nd P type, also be provided with second and expand phosphorus zone N3; Then described gate pole is arranged on the described second expansion phosphorus zone N3, and described negative electrode is arranged on the described first expansion phosphorus zone N2 and the short base P2 of described the 2nd P type.
This chip is during for the manufacture of unidirectional thyristor or bidirectional thyristor chip, and described divider wall is provided with the cutting-up zone; Between described gate pole and negative electrode, between described cutting-up zone and the negative electrode, and between described cutting-up zone and the gate pole, all be provided with oxide layer, passivation film and polyimide film.
Another technical scheme of the present invention provides a kind of manufacture method of the chip for the manufacture of the plane thyristor, and described chip comprises during for the manufacture of unidirectional thyristor:
Be positioned at the middle N-type growing base area N1 of chip, be arranged on the short base P1 of a P type of N-type growing base area N1 downside, be arranged on the short base P2 of the 2nd P type of N-type growing base area N1 upside;
On the short base P2 of the 2nd P type that is arranged on first expands phosphorus zone N2, is arranged on first negative electrode that expands on the N2 of phosphorus zone; Gate pole on the short base P2 of the 2nd P type that is arranged on; Anode on the short base P1 of the P type that is arranged on;
Be arranged on the divider wall of N-type growing base area N1 periphery, the field limiting ring between the short base P2 of the 2nd P type that is arranged on and the divider wall is characterized in that:
The divider wall of described chip forms through first method or second method, wherein,
Described first method comprises following steps: silicon chip two-sided through sandblast, photoetching corrosion to board marker, evaporated metal aluminium after, anti-carve metallic aluminium to keep the locational metallic aluminium of corresponding divider wall, after carrying out the vacuum alloy again, through logical isolation diffusion is formed described divider wall;
Described second method comprises following steps: silicon chip is two-sided after window, deposited polycrystalline silicon thin film and evaporated metal aluminium are isolated in peroxidating, photoetching, carry out metallic aluminium and anti-carve to keep the metallic aluminium of isolating on the window, again by logical isolation diffusion is formed described divider wall.
In described first method, the thickness of two-sided evaporated metal aluminium film is 0.2 ~ 1.0um;
After anti-carving aluminium film, being retained in the locational metallic aluminium width of corresponding divider wall is 80 ~ 200um;
During the vacuum alloy, 480 ~ 520 ℃ of alloy temperatures, 20 ~ 40 minutes alloy time;
During to logical isolation diffusion, 1200 ~ 1280 ℃ of diffusion temperatures are isolating logical of 200-500um to realize silicon wafer thickness 20 ~ 60 hours diffusion times; Diffusion atmosphere: nitrogen and oxygen proportion 5:1 ~ 10:1, wherein, nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min, 3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall; The divider wall thickness that forms is 100 ~ 300um.
In described second method, at the thickness of oxide layer 〉=1.0um of the two-sided formation of silicon chip;
When dual surface lithography was isolated window, the width of described isolation window was 80-200um, and rotten clean oxide layer of isolating in the window;
Deposited polycrystalline silicon thin film in the isolation window of the surface of silicon chip both sides and silicon chip both sides, the thickness of described polysilicon membrane is 0.3-2.0um;
Two-sided evaporated metal aluminium makes that the aluminium film thickness is 0.2 ~ 1.0um;
Anti-carve metallic aluminium, the aluminium film width that only keeps on the described isolation window is 80 ~ 200um;
During to logical isolation diffusion, 1200 ~ 1280 ℃ of diffusion temperatures are isolating logical of 200-500um to realize silicon wafer thickness 20 ~ 60 hours diffusion times; Diffusion atmosphere: nitrogen and oxygen proportion 5:1 ~ 10:1, nitrogen flow 2 ~ 6L/min wherein, oxygen flow 0.2 ~ 0.6L/min, 3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall; The divider wall thickness that forms is 100 ~ 300um;
Also be included in the surface corrosion of carrying out after the logical isolation diffusion in described second method, to remove the alusil alloy layer of isolating in the window.
After diffuseing to form divider wall in the described chip by evaporated metal aluminium, other parts in this chip further form by following steps: photoetching boron window, boron diffusion, photoetching K district, phosphorus diffusion, positive cutting, photoetching passivation window, passivation protection, photoetching lead-in wire, double-sided metalization, metal anti-carve, alloy, polyimides formation, photoetching bonding wire window, imidization, chip testing, silicon chip cutting-up.
Described chip is during for the manufacture of bidirectional thyristor, further comprises in this chip to be arranged on the 3rd on the short base P1 of a described P type and to expand phosphorus zone N4 and be arranged on second on the short base P2 of described the 2nd P type and expand phosphorus zone N3;
Then, when carrying out the step in photoetching K district, be to form described first to expand phosphorus zone N2 and the second expansion phosphorus zone N3 in the front of silicon chip on this chip, also form the described the 3rd in silicon chip back and expand phosphorus zone N4.
Another technical scheme of the present invention provides a kind of plane thyristor, it is provided with above-mentioned any one and implements the chip of structure, the anodic bonding of described chip is connected on the framework, the gate pole of described chip and negative electrode are wired to respectively on the corresponding pin of framework, and described thyristor also is provided with the shell of this chip of protection; Wherein, be provided with the divider wall that diffuses to form through evaporated metal aluminium in the described chip;
The described divider wall that diffuses to form through evaporated metal aluminium, refer to after the sandblast of the two-sided process of silicon chip, photoetching corrosion are to board marker, evaporated metal aluminium, carry out metallic aluminium and anti-carve to keep the locational metallic aluminium of corresponding divider wall, after carrying out the vacuum alloy again, pass through formed divider wall after the logical isolation diffusion;
Perhaps, the described divider wall that diffuses to form through evaporated metal aluminium, refer at silicon chip two-sided after window, deposited polycrystalline silicon thin film and evaporated metal aluminium are isolated in peroxidating, photoetching, carry out metallic aluminium and anti-carve to keep the metallic aluminium of isolating on the window, again by logical isolation diffusion is formed formed divider wall.
Compared with prior art, plane of the present invention thyristor, for the manufacture of chip of plane thyristor and preparation method thereof, its advantage is: thyristor of the present invention comprises shell, chip, framework three parts, chip wherein comprises N-type growing base area N1, P type short base P1, P2, divider wall, expand phosphorus zone N2(or expand phosphorus zone N2, N3, N4), field limiting ring etc.Especially described divider wall is to be formed by evaporated metal aluminium diffusion: in a kind of preferred version, evaporated metal aluminium after the silicon chip surface sandblast, through anti-carve, the vacuum alloy, to forming divider wall after the logical isolation diffusion.In the another kind of preferred version, silicon chip is after window is isolated in oxidation, photoetching, and deposited polycrystalline silicon thin film evaporates the width metallic aluminium consistent with isolating window width, carries out forming divider wall after the logical isolation diffusion.Above-mentioned two kinds of methods all are suitable for for unidirectional thyristor chip, the bidirectional thyristor chip of planar technique.Employed K district version when unidirectional and difference bidirectional thyristor are photoetching K district (that is, expanding the phosphorus zone) requires to design different K districts according to product parameters and edition can realize unidirectional, bidirectional thyristor.
The present invention has eliminated because the drawback that diffusion rate of boron is slow, diffusion depth is shallow (can only realize following the isolating logical of silicon wafer thickness 250um) owing to adopt metallic aluminium to spread as impurity source.The aluminium diffusion can realize isolating logical of silicon wafer thickness 200-500um, withstand voltagely can bring up to more than the 2000V, the high temperature electric leakage is little, stable performance, the horizontal proliferation width of aluminium is 40% (the horizontal proliferation width of boron be diffusion depth 80%) of diffusion depth, improve the utilance of chip area, improve the current capacity of product.In addition, also have the following advantages: production cost is low, with short production cycle, power consumption and pollute fewly etc., adopts thyristor superior performance that the present invention produces, reliable and stable.
Description of drawings
Figure 1A ~ Fig. 1 F is in the manufacture method of the present invention, adopts evaporated metal aluminium to realize the thyristor chip structural representation corresponding to each key step in the logical isolation scheme with first kind;
Fig. 1 G ~ Fig. 1 J is among four different embodiment, the profile schematic diagram of aluminium film on the adjacent chips;
Fig. 2 A ~ Fig. 2 D is in the manufacture method of the present invention, adopts evaporated metal aluminium to realize the thyristor chip structural representation corresponding to each key step in the logical isolation scheme with second kind;
Fig. 3 is in the manufacture method of thyristor chip of the present invention, and first kind is adopted evaporated metal aluminium to realize leading to the process flow diagram of isolation scheme;
Fig. 4 is in the manufacture method of thyristor chip of the present invention, and second kind is adopted evaporated metal aluminium to realize leading to the process flow diagram of isolation scheme;
Fig. 5 is the structural representation of unidirectional thyristor chip in a preferred embodiment of the invention;
Fig. 6 is the structural representation of bidirectional thyristor chip in the another preferred embodiment of the present invention.
Among the figure: silicon chip 101, photoresist 102, to board marker 103, aluminium film 104, divider wall 105;
In the unidirectional thyristor: N-type growing base area N1901, the short base P1902 of a P type, the short base P2903 of the 2nd P type expands phosphorus zone N2904, divider wall 905, field limiting ring 906, gate pole 907, negative electrode 908, anode 909, oxide layer 910, cutting-up zone 911, passivation film 912, polyimide film 913;
In the bidirectional thyristor: N-type growing base area N11001, the short base P11002 of a P type, the short base P21003 of the 2nd P type, first expands phosphorus zone N21004, and second expands phosphorus zone N31005, and the 3rd expands phosphorus zone N41006, divider wall 1007, field limiting ring 1008, gate pole 1009, negative electrode 1010, anode 1011, oxide layer 1012, passivation film 1013, polyimide film 1014, cutting-up zone 1015.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
Embodiment 1
Thyristor in the present embodiment is the unidirectional thyristor of planar technique; mainly comprise shell, chip, framework three parts; its core is chip; the anodic bonding of chip is connected on the framework; the gate pole of chip and negative electrode are wired to respectively on the corresponding pin of framework, and shell plays the effect of protection chip.
Thyristor chip (chip structure is seen accompanying drawing 5) is the planar technique unidirectional thyristor chip, comprising: N-type growing base area N1901, the short base P1902 of a P type, the short base P2903 of the 2nd P type, expansion phosphorus zone N2904, divider wall 905, field limiting ring 906, gate pole 907, negative electrode 908, anode 909, oxide layer 910, cutting-up zone 911, passivation film 912, polyimide film 913.
Be N-type growing base area N1901 in the middle of the chip, both sides are respectively the short base P1902 of a P type, the short base P2903 of the 2nd P type up and down.N-type growing base area N1901 periphery all has divider wall 905 protections: divider wall forms (implementation step will specifically describe hereinafter) by the diffusion of evaporated metal aluminium.Cutting-up zone 911 be located at divider wall 905 directly over; expanding phosphorus zone N2904 is located on the short base P2903 of the 2nd P type; negative electrode 908 is located at and expands on the N2904 of phosphorus zone; gate pole 907 is located on the short base P2903 of the 2nd P type; anode 909 is located on the short base P1902 of a P type; field limiting ring 906 is located between divider wall 905 and the short base P2903 of the 2nd P type, and passivation film 912, polyimide film 913 passivation protection are all arranged between cutting-up zone 911, gate pole 907, the negative electrode 908.This structure except divider wall be formed by evaporated metal aluminium diffusion, remainder is identical with original planar technique unidirectional thyristor chip.
Above-mentioned planar technique unidirectional thyristor chip manufacture method: referring to accompanying drawing 3, this manufacture method comprises silicon chip Incoming Quality Control 501; two-sided sandblast and clean 502; photoetching corrosion is to board marker 503; two-sided evaporation of aluminum 504; anti-carve metallic aluminium 505; vacuum alloy 506; to logical isolation diffusion 507; twin polishing 508; oxidation 509; photoetching boron window 510; boron diffusion 511; photoetching K district 512; phosphorus diffusion 513; photoetching passivation window 514; passivation protection 515; lithography fair lead 516; double-sided metalization 517; metal anti-carves 518; alloy 519; polyimides 520; photoetching bonding wire window 521; imidization 522; chip testing 523; silicon chip cutting-up 524.
Silicon chip Incoming Quality Control 501: choose＜111〉fused silicon chip, resistivity 50-60
, silicon wafer thickness 300 ± 5um.
Two-sided sandblast cleans 502: use sand-blasting machine with the two-sided sandblast of silicon chip, the sandblast removal amount is 0.5-1.0um, cleans bath with activating agent after the sandblast and gets final product.The purpose of two-sided sandblast work step is to destroy the lattice structure of silicon chip surface silicon atom, helps metallic aluminium and the better combination of silicon in the follow-up work step.
Photoetching corrosion is to board marker 503: specifically see also shown in accompanying drawing 1A ~ Figure 1B, apply photoresist 102 respectively on the silicon chip two sides, by the mask version photoresist 102 on the silicon chip 101 is exposed, marker graphic on the mask version (square, rectangle, rectangle, circle figures all can) is copied on the silicon chip 101, by behind the developing liquid developing photoresist 102 in the marker graphic being removed totally (being that the interior silicon of figure exposes on the surface), with silicon microcorrosion liquid marker graphic is corroded, corrosion depth is generally 30-40um, removes photoresist after the corrosion, cleans.
Two-sided evaporation of aluminum 504: namely, two-sided evaporated metal aluminium (evaporation mode can adopt electron beam evaporation, sputter) aluminium film thickness is generally 0.2 ~ 1.0um.Referring to Fig. 1 C, the deposited by electron beam evaporation platform is at the two-sided evaporated metal aluminium of silicon chip, and for example, the aluminium film thickness is 0.2 ~ 1.0um.
Anti-carve metallic aluminium 505: shown in Fig. 1 D ~ Fig. 1 E, utilize photoetching technique, keep the metallic aluminium above the divider wall, with the metallic aluminium in rotten clean other zones of aluminium corrosive liquid, aluminium film width is generally 80-200um.The shape of aluminium film: shown in Fig. 1 H, adjacent chips shares continuous metal aluminium film (aluminium film width is 80-200um); Also can be shown in accompanying drawing 1G, each chip uses independent aluminium film, and the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth); Also can be shown in accompanying drawing 1I, adjacent chips shares discontinuous aluminium film, single aluminium film profile has multiple (as square, rectangle etc.), the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth), also can be shown in accompanying drawing 1J, each chip uses independent discontinuous aluminium film, and single aluminium film profile has multiple (as square, rectangle etc.), and the spacing of aluminium film and aluminium film is 50-500um (spacing can be regulated according to diffusion depth)
Vacuum alloy 506: for example, 480 ~ 520 ℃ of alloy temperatures, 20 ~ 40 minutes alloy time; The purpose of vacuum alloy work step is metallic aluminium and silicon are formed good, the uniform aluminium silicon fused mass of one deck under alloy temperature, makes the divider wall that diffuses to form have uniform diffusion depth, diffusion breadth.
To leading to isolation diffusion 507: 1200 ~ 1280 ℃ of diffusion temperatures, 20 ~ 60 hours diffusion times, can realize that silicon wafer thickness is isolating logical of 200-500um.Diffusion atmosphere: nitrogen and oxygen proportion 5:1 ~ 10:1 oxygen can be oxidized to Al with aluminium steam (under the hot conditions)
2O
3, Al
2O
3Be a kind of invalid impurity diffusion source, can not form p type island region, O at naked silicon face
2Can be used for stopping in the boiler tube or the diffusion of other impurity of silicon chip surface in naked silicon face growth oxide layer; Common nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min, 3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall.
In the preferred embodiment, 1275 ℃ of diffusion temperatures, 35 hours diffusion times, diffusion atmosphere: N
2Flow is 6L/min, O
2Flow is 0.6L/min, 4 ℃/min of heating rate, 2 ℃/min of rate of temperature fall.Forming width after the High temperature diffusion is the divider wall of 100-150um, diffusion back R
Be about 200-500
.
Twin polishing 508: will carry out twin polishing to the silicon chip after the logical isolation diffusion, and remove the surfaces of aluminum silicon alloy layer, the polishing removal amount is 15-20um.So far, diffuse to form structure behind the divider wall 105 by evaporated metal aluminium film in the thyristor chip, see also shown in Fig. 1 F.
Oxidation 509: 1100 ~ 1200 ℃ of oxidizing temperatures, oxidization time 6-8h, the oxidated layer thickness that obtains is generally 1.5um.
Photoetching boron window 510: utilize photoetching technique, the oxide layer corrosion in the short base of P type and the field limiting ring is clean.
Boron diffusion 511: inject boron (implantation dosage: 1E14 ~ 1E15), carry out High temperature diffusion then, 1200 ~ 1280 ℃ of diffusion temperatures, 20-30 hour diffusion time, boron R with ion implantor
Be 20-60
, boron junction depth are 30-50um.That is, the short base P1902 of the P type shown in Fig. 5 and the short base P2903 of the 2nd P type have been formed.
Photoetching K district 512: expand the phosphorus zone in the positive photoetching of silicon chip.
Phosphorus diffusion 513: adopt phosphorus oxychloride (POCl
3) the liquid source diffusion, 1050 ~ 1150 ℃ of pre-expansion temperature, 60-90 minute pre-expansion time, source temperature 15-20 ℃, phosphorus expands 1150 ~ 1200 ℃ of temperature again, and time 4-5 hour, R
Be 0.3-1.00
, the diffusion junction depth is 10-20um.That is, formed the expansion phosphorus zone N2904 shown in Fig. 5.
Lithography fair lead 516: carve and need carry out metallized zone, and the corrosion of the passivation protection layer in the zone is clean.
Double-sided metalization 517: evaporate titanium-nickel-Yin respectively at the positive back side of silicon chip, titanium evaporation thickness requirement 1200-1600 dust, nickel evaporation thickness requirement 4500-5500 dust, silver evaporation thickness requirement 1.4-1.7um.That is, the gate pole 907 shown in Fig. 5, negative electrode 908 and anode 909 have been formed at correspondence position.
Metal anti-carves 518: be that photoetching is carried out in the zone that does not need metal level to cover.The photoetching post-etching is removed the metal level in the above-mentioned zone, peels off then and removes photoresist.
Alloy 519: vacuum alloy, the adhesion of reinforcement metal and silicon.
Then chip is tested 523), silicon chip cutting-up 524) become thyristor chip disconnected from each other.
Chip behind the cutting-up is carried out bonding die, bonding, seals, electroplates, cuts muscle, finished product test, and final product is the plane thyristor.
Adopt plane of the present invention thyristor product electrical quantity, electrical property obviously to improve, every index all reaches designing requirement.(space of a whole page is 3.9*3.9mm with 16A/1400V
2) be example, the applicant accomplishes: on-state average current IT
(AV)=16A, forward and reverse crest voltage V
DRM=V
RRM=1400-1600V, peak on state voltage V
TM≤ 1.3V@I
T=5A, gate trigger voltage V
GT=0.8-1.2V, gate trigger current I
GT=10-30mA, high-temperature current leakage (125 ℃) I
DRM/ I
RRM=0.1-0.3mA.
Embodiment 2
Thyristor in the present embodiment is the bidirectional thyristor of planar technique; mainly comprise shell, chip, framework three parts; its core is chip; the anodic bonding of chip is connected on the framework; the gate pole of chip and negative electrode are wired to respectively on the corresponding pin of framework, and shell plays the effect of protection chip.
The chip structure of thyristor chip is seen accompanying drawing 6, be a planar technique bidirectional thyristor chip, comprise: second the 3rd expansion phosphorus zone N41006, divider wall 1007, field limiting ring 1008, gate pole 1009, negative electrode 1010, anode 1011, oxide layer 1012, passivation film 1013, polyimide film 1014, the cutting-up zone of expanding on phosphorus zone N31005, the short base P11002 of a P type 1015 under N-type growing base area N11001, the short base P11002 of a P type, the short base P21003 of the 2nd P type, the first expansion phosphorus zone N21004, the gate pole.
Be N-type growing base area N11001 in the middle of the chip, both sides are respectively the short base P11002 of a P type, the short base P21003 of the 2nd P type up and down.N-type growing base area N11001 periphery all has divider wall 1007 protections: divider wall forms (performing step will specifically describe hereinafter) by the diffusion of evaporated metal aluminium.Be provided with field limiting ring 1008 between the short base P21003 of divider wall 1007 and the 2nd P type.The 3rd expands phosphorus zone N41006 is located on the short base P11002 of a P type, and the first expansion phosphorus zone N21004 and second expands phosphorus zone N31005 and is located on the short base P21003 of the 2nd P type.Gate pole 1009 is located at second and expands on the N31005 of phosphorus zone; negative electrode 1010 is located at first and expands on phosphorus zone N21004 and the short base P21003 of the 2nd P type; anode 1011 is located at the short base P11002 of a P type and first and expands on the N21004 of phosphorus zone; cutting-up zone 1015 is located on the divider wall 1007, and passivation film 1013, polyimide film 1014 passivation protection are all arranged between gate pole 1009, negative electrode 1010, the cutting-up zone 1015.This structure except divider wall be formed by evaporated metal aluminium diffusion, remainder is identical with original planar technique bidirectional thyristor chip.The manufacture method of above-mentioned planar technique bidirectional thyristor chip, except in photoetching K district step, the two-sided needs outside the expansion of the photoetching simultaneously phosphorus zone, all the other steps are with embodiment 1.
The manufacture method of divider wall in the above-mentioned bidirectional thyristor chip is summarized as follows:
Behind the silicon chip Incoming Quality Control, two-sided sandblast and cleaning.Dual surface lithography to board marker and the corrosion to board marker, be convenient to follow-up photoetching to version, see accompanying drawing 1A ~ Figure 1B.Two-sided evaporated metal aluminium (evaporation mode can adopt electron beam evaporation, sputter), the aluminium film thickness is generally 0.2 ~ 1.0um, sees accompanying drawing 1C.Anti-carve aluminium film, only keep required aluminium film (aluminium film width is 80-200um), see accompanying drawing 1D ~ Fig. 1 E.Vacuum alloy: 480 ~ 520 ℃ of alloy temperatures, 20 ~ 40 minutes alloy time.To leading to isolation diffusion: 1200 ~ 1280 ℃ of diffusion temperatures, 20 ~ 60 hours diffusion times, can realize that silicon wafer thickness is isolating logical of 200-500um.Diffusion atmosphere: (3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall see accompanying drawing 1F for common nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min) for nitrogen and oxygen proportion 5:1 ~ 10:1.
And, the production method of above-mentioned planar technique bidirectional thyristor chip, except in photoetching K district step, two-sided photoetching is simultaneously expanded outside the phosphorus zone accordingly, and all the other steps are with embodiment 1.
Embodiment 3
Thyristor in the present embodiment is the unidirectional thyristor of planar technique; mainly comprise shell, chip, framework three parts; its core is chip; the anodic bonding of chip is connected on the framework; the gate pole of chip and negative electrode are wired to respectively on the corresponding pin of framework, and shell plays the effect of protection chip.
Thyristor chip (chip structure is seen accompanying drawing 5) is the planar technique unidirectional thyristor chip, comprising: N-type growing base area N1901, the short base P1902 of a P type, the short base P2903 of the 2nd P type, expansion phosphorus zone N2904, divider wall 905, field limiting ring 906, gate pole 907, negative electrode 908, anode 909, oxide layer 910, cutting-up zone 911, passivation film 912, polyimide film 913.This structure except divider wall be formed by evaporated metal aluminium diffusion, remainder is identical with original planar technique unidirectional thyristor chip.The formation method that then is divider wall with the difference of embodiment 1 is different.
Above-mentioned planar technique unidirectional thyristor chip manufacture method: referring to accompanying drawing 4, this manufacture method comprises silicon chip Incoming Quality Control 601; clean and oxidation 602; window 603 is isolated in photoetching; polysilicon deposition 604; two-sided evaporation of aluminum 605; photoetching aluminum window mouth 606; to logical isolation diffusion 607; surface corrosion 608; secondary oxidation 609; photoetching boron window 610; boron diffusion 611; photoetching K district 612; phosphorus diffusion 613; photoetching passivation window 614; passivation protection 615; lithography fair lead 616; double-sided metalization 617; metal anti-carves 618; alloy 619; polyimides 620; photoetching bonding wire window 621; imidization 622; chip testing 623; silicon chip cutting-up 624.
Silicon chip Incoming Quality Control 601: choose＜111〉fused silicon chip, resistivity 50-60
, silicon wafer thickness 300 ± 5um.
Clean oxidation 602: adopt dried oxygen, wet oxygen alternating oxidation, 1150 ~ 1200 ℃ of oxidizing temperatures, time 5-8 hour.Oxide layer 202 thickness that form on silicon chip 201 two sides generally greater than 〉=1.0um, can protect graphics chip inside not to be subjected to the influence of other impurity.
Photoetching isolation window 603: carry out photoetching on silicon chip 201 two sides, the oxide layer corrosion of isolating in the window is clean, isolate window width and be generally 80-200um, corrode isolation window internal oxidation layer and remove photoresist, also see Fig. 2 A.
Polysilicon deposition 604:LPCVD method deposited polycrystalline silicon thin film, film thickness is generally: 0.3 ~ 2.0um; Its effect is that (behind the evaporated metal aluminium) forms layer of even aluminum impurity source film under hot conditions, makes the diffusion depth of divider wall, width even, consistent.
Two-sided evaporation of aluminum 605: the deposited by electron beam evaporation platform is at the two-sided evaporated metal aluminium of silicon chip, and the aluminium film thickness is 0.2 ~ 1.0um, sees accompanying drawing 2B.
Photoetching aluminum window mouth 606: utilize photoetching technique, keep the metallic aluminium of isolating above the window, with the metallic aluminium in rotten clean other zones of aluminium corrosive liquid, aluminium film width is seen Fig. 2 C with isolating the window width unanimity.The shape of aluminium film: shown in Fig. 1 H, adjacent chips shares continuous metal aluminium film (aluminium film width is 80-200um); Also can be shown in accompanying drawing 1G, each chip uses independent aluminium film, and the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth); Also can be shown in accompanying drawing 1I, adjacent chips shares discontinuous aluminium film, and single aluminium film profile has multiple (as square, rectangle etc.), and the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth).Also can be shown in accompanying drawing 1J, each chip uses independent discontinuous aluminium film, and single aluminium film profile has multiple (as square, rectangle etc.), and the spacing of aluminium film and aluminium film is 50-500um (spacing can be regulated according to diffusion depth).
To leading to isolation diffusion 607: 1200 ~ 1280 ℃ of diffusion temperatures, 20 ~ 60 hours diffusion times, can realize that silicon wafer thickness is isolating logical of 200-500um.Diffusion atmosphere: (3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall see accompanying drawing 2D for common nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min) for nitrogen and oxygen proportion 5:1 ~ 10:1.
In the preferred embodiment, 1275 ℃ of diffusion temperatures, 60 hours diffusion times, diffusion atmosphere: N
2Flow is 6L/min, O
2Flow is 0.6L/min, 4 ℃/min of heating rate, 2 ℃/min of rate of temperature fall.Forming width after the High temperature diffusion is the divider wall of 100-150um, diffusion back R
Be about 200-500
.
Surface corrosion 608: clean with the alusil alloy layer corrosion that silicon etch solution will be isolated in the window.
Step 609 is identical to step 524 with the step 509 among the embodiment 1 to step 624, finally forms the described thyristor of present embodiment.
Embodiment 4
Thyristor in the present embodiment is the bidirectional thyristor of planar technique; mainly comprise shell, chip, framework three parts; its core is chip; the anodic bonding of chip is connected on the framework; the gate pole of chip and negative electrode are wired to respectively on the corresponding pin of framework, and shell plays the effect of protection chip.
Thyristor chip (chip structure is seen accompanying drawing 6) is planar technique bidirectional thyristor chip, comprising: second expansion phosphorus zone N3 1005, the P1 the last the 3rd expands the regional N4 1006 of phosphorus, divider wall 1007, field limiting ring 1008, gate pole 1009, negative electrode 1010, anode 1011, oxide layer 1012, passivation film 1013, polyimide film 1014, cutting-up zone 1015 under N-type growing base area N11001, the short base P11002 of a P type, the short base P21003 of the 2nd P type, the first expansion phosphorus zone N21004, the gate pole.This structure except divider wall be formed by evaporated metal aluminium diffusion, remainder is identical with original planar technique bidirectional thyristor chip.
The formation method that then is divider wall with the difference of embodiment 2 is different.Divider wall has used the manufacture method shown in the embodiment 3 in the above-mentioned bidirectional thyristor chip, is summarized as follows:
Silicon chip cleans, oxidation (oxidated layer thickness 〉=1.0um).Dual surface lithography shading ring (the shading ring width is 80-200um), the oxide layer in the rotten clean shading ring is seen accompanying drawing 2A.LPCVD method deposited polycrystalline silicon thin film: polysilicon membrane thickness is 0.3-2.0um.Two-sided evaporated metal aluminium, the aluminium film thickness is generally 0.2 ~ 1.0um, sees accompanying drawing 2B.Anti-carve metallic aluminium, only keep required aluminium film, see accompanying drawing 2C.To leading to isolation diffusion: 1200 ~ 1280 ℃ of diffusion temperatures, 20 ~ 60 hours diffusion times, can realize that silicon wafer thickness is isolating logical of 200-500um.Diffusion atmosphere: (3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall see accompanying drawing 2D for common nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min) for nitrogen and oxygen proportion 5:1 ~ 10:1.
The manufacture method of above-mentioned planar technique bidirectional thyristor chip, except in photoetching K district step, the two-sided needs outside the expansion of the photoetching simultaneously phosphorus zone, all the other steps are with embodiment 3.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be apparent.
For example, protection scope of the present invention is not subjected to the restriction of concrete parameter among the embodiment, as:
1. aluminium film thickness is less than 0.2um (or greater than 1.0um), and width also can be implemented the present invention less than 80um (or greater than 200um), but actual effect is the best with aluminium film thickness 0.2 ~ 1.0um, width 80-200um.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
2. the arrangement method of aluminium film: shown in Fig. 1 H, adjacent chips shares continuous metal aluminium film (aluminium film width is 80-200um); Also can be shown in accompanying drawing 1G, each chip uses independent aluminium film, and the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth); Also can be shown in accompanying drawing 1I, adjacent chips shares discontinuous aluminium film, and single aluminium film profile has multiple (as square, rectangle etc.), and the spacing of aluminium film and aluminium film is 100-500um (spacing can be regulated according to diffusion depth); Also can be shown in accompanying drawing 1J, each chip uses independent discontinuous aluminium film, and single aluminium film profile has multiple (as square, rectangle etc.), and the spacing of aluminium film and aluminium film is 50-500um (spacing can be regulated according to diffusion depth).If artificial enforcement the present invention is arranged, deliberately adopt the aluminium film arrangement method of other shapes, also should fall into protection scope of the present invention.
3. polysilicon membrane thickness also can be implemented the present invention less than 0.3 um (or greater than 2.0um), but actual effect is the best with polysilicon membrane thickness 0.3 ~ 2.0um.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
4. in order to reach the purpose of the lattice structure of destroying the silicon chip surface silicon atom, also can adopt laser to make other modes such as damage, ion injection and implement the present invention, but actual effect is the most economic, practical with the method for sandblast.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
5. the vacuum alloy temperature is lower than 480 ℃ of (or being higher than 520 ℃), times and is less than 20 minutes (or being longer than 40 minutes), also can implement the present invention, but actual effect is the best with 480 ~ 520 ℃ of vacuum alloy temperatures, 20 ~ 40 minutes alloy time.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
6. during High temperature diffusion, nitrogen and oxygen proportion are lower than 5:1 (or being higher than 10:1) also can implement the present invention, but actual effect is the best with nitrogen and oxygen proportion 5:1 ~ 10:1.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
7. oxidated layer thickness also can be implemented the present invention less than 1.0um, but actual effect is the best with oxidated layer thickness greater than 1.0um.If artificial enforcement the present invention is arranged, deliberately adopt said method, also should fall into protection scope of the present invention.
Claims (10)
1. chip for the manufacture of the plane thyristor comprises:
Be positioned at the middle N-type growing base area (N1) of chip, be arranged on the short base (P1) of a P type of N-type growing base area (N1) downside, be arranged on the short base (P2) of the 2nd P type of N-type growing base area (N1) upside;
Be arranged on first on the short base of the 2nd P type (P2) and expand phosphorus zone (N2), be arranged on first negative electrode that expands on the phosphorus zone (N2); Be arranged on the gate pole on the short base of the 2nd P type (P2); Be arranged on the anode on the short base of a P type (P1);
Be arranged on the divider wall of N-type growing base area (N1) periphery, the field limiting ring between the short base (P2) of the 2nd P type that is arranged on and the divider wall, it is characterized in that: described divider wall is diffuseed to form by evaporated metal aluminium.
2. according to claim 1 for the manufacture of the chip of plane thyristor, it is characterized in that:
On the short base of a described P type (P1), also be provided with the 3rd and expand phosphorus zone (N4); Then described anode is arranged on the short base (P1) of a described P type and described the 3rd expansion phosphorus zone (N4);
On the short base of described the 2nd P type (P2), also be provided with second and expand phosphorus zone (N3); Then described gate pole is arranged on the described second expansion phosphorus zone (N3), and described negative electrode is arranged on the described first expansion phosphorus zone (N2) and the short base of described the 2nd P type (P2).
3. as claimed in claim 1 or 2 for the manufacture of the chip of plane thyristor, it is characterized in that:
Described divider wall is provided with the cutting-up zone;
Between described gate pole and negative electrode, between described cutting-up zone and the negative electrode, and between described cutting-up zone and the gate pole, all be provided with oxide layer, passivation film and polyimide film.
4. manufacture method for the manufacture of the chip of plane thyristor, described chip comprises:
Be positioned at the middle N-type growing base area (N1) of chip, be arranged on the short base (P1) of a P type of N-type growing base area (N1) downside, be arranged on the short base (P2) of the 2nd P type of N-type growing base area (N1) upside;
Be arranged on first on the short base of the 2nd P type (P2) and expand phosphorus zone (N2), be arranged on first negative electrode that expands on the phosphorus zone (N2); Be arranged on the gate pole on the short base of the 2nd P type (P2); Be arranged on the anode on the short base of a P type (P1);
Be arranged on the divider wall of N-type growing base area (N1) periphery, the field limiting ring between the short base (P2) of the 2nd P type that is arranged on and the divider wall is characterized in that:
The divider wall of described chip forms through first method or second method, wherein,
Described first method comprises following steps: silicon chip two-sided through sandblast, photoetching corrosion to board marker, evaporated metal aluminium after, anti-carve metallic aluminium to keep the locational metallic aluminium of corresponding divider wall, after carrying out the vacuum alloy again, through logical isolation diffusion is formed described divider wall;
Described second method comprises following steps: silicon chip is two-sided after window, deposited polycrystalline silicon thin film and evaporated metal aluminium are isolated in peroxidating, photoetching, carry out metallic aluminium and anti-carve to keep the metallic aluminium of isolating on the window, again by logical isolation diffusion is formed described divider wall.
5. manufacture method as claimed in claim 4 is characterized in that:
In described first method, the thickness of two-sided evaporated metal aluminium film is 0.2 ~ 1.0um;
After anti-carving aluminium film, being retained in the locational metallic aluminium width of corresponding divider wall is 80 ~ 200um;
During the vacuum alloy, 480 ~ 520 ℃ of alloy temperatures, 20 ~ 40 minutes alloy time;
During to logical isolation diffusion, 1200 ~ 1280 ℃ of diffusion temperatures are isolating logical of 200-500um to realize silicon wafer thickness 20 ~ 60 hours diffusion times; Diffusion atmosphere: nitrogen and oxygen proportion 5:1 ~ 10:1, wherein, nitrogen flow 2 ~ 6L/min, oxygen flow 0.2 ~ 0.6L/min, 3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall; The divider wall thickness that forms is 100 ~ 300um.
6. manufacture method as claimed in claim 4 is characterized in that:
In described second method, at the thickness of oxide layer 〉=1.0um of the two-sided formation of silicon chip;
When dual surface lithography was isolated window, the width of described isolation window was 80-200um, and rotten clean oxide layer of isolating in the window;
Deposited polycrystalline silicon thin film in the isolation window of the surface of silicon chip both sides and silicon chip both sides, the thickness of described polysilicon membrane is 0.3-2.0um;
Two-sided evaporated metal aluminium makes that the aluminium film thickness is 0.2 ~ 1.0um;
Anti-carve metallic aluminium, the aluminium film width that only keeps on the described isolation window is 80 ~ 200um;
During to logical isolation diffusion, 1200 ~ 1280 ℃ of diffusion temperatures are isolating logical of 200-500um to realize silicon wafer thickness 20 ~ 60 hours diffusion times; Diffusion atmosphere: nitrogen and oxygen proportion 5:1 ~ 10:1, nitrogen flow 2 ~ 6L/min wherein, oxygen flow 0.2 ~ 0.6L/min, 3 ~ 5 ℃/min of heating rate, 1 ~ 3 ℃/min of rate of temperature fall; The divider wall thickness that forms is 100 ~ 300um;
Also be included in the surface corrosion of carrying out after the logical isolation diffusion in described second method, to remove the alusil alloy layer of isolating in the window.
7. as claim 5 or 6 described manufacture methods, it is characterized in that:
After diffuseing to form divider wall in the described chip by evaporated metal aluminium, other parts in this chip further form by following steps: photoetching boron window, boron diffusion, photoetching K district, phosphorus diffusion, positive cutting, photoetching passivation window, passivation protection, photoetching lead-in wire, double-sided metalization, metal anti-carve, alloy, polyimides formation, photoetching bonding wire window, imidization, chip testing, silicon chip cutting-up.
8. manufacture method as claimed in claim 7 is characterized in that:
Further comprise in the described chip to be arranged on the 3rd expansion phosphorus zone (N4) on the short base of a described P type (P1) and to be arranged on second on the short base of described the 2nd P type (P2) and expand phosphorus zone (N3);
Then, when carrying out the step in photoetching K district, be to form described first to expand phosphorus zone (N2) and the second expansion phosphorus zone (N3) in the front of silicon chip on this chip, also form the described the 3rd in silicon chip back and expand phosphorus zone (N4).
9. plane thyristor, it is characterized in that be provided with chip as claimed in claim 1, the anodic bonding of described chip is connected on the framework, the gate pole of described chip and negative electrode are wired to respectively on the corresponding pin of framework, and described thyristor also is provided with the shell of this chip of protection; Wherein, be provided with the divider wall that diffuses to form through evaporated metal aluminium in the described chip;
The described divider wall that diffuses to form through evaporated metal aluminium, refer to after the sandblast of the two-sided process of silicon chip, photoetching corrosion are to board marker, evaporated metal aluminium, carry out metallic aluminium and anti-carve to keep the locational metallic aluminium of corresponding divider wall, after carrying out the vacuum alloy again, pass through formed divider wall after the logical isolation diffusion;
Perhaps, the described divider wall that diffuses to form through evaporated metal aluminium, refer at silicon chip two-sided after window, deposited polycrystalline silicon thin film and evaporated metal aluminium are isolated in peroxidating, photoetching, carry out metallic aluminium and anti-carve to keep the metallic aluminium of isolating on the window, again by logical isolation diffusion is formed formed divider wall.
10. plane as claimed in claim 9 thyristor is characterized in that:
In described chip, also be provided with the 3rd on the short base of a described P type (P1) and expand phosphorus zone (N4); Then described anode is arranged on the short base (P1) of a described P type and described the 3rd expansion phosphorus zone (N4);
On the short base of described the 2nd P type (P2), also be provided with second and expand phosphorus zone (N3); Then described gate pole is arranged on the described second expansion phosphorus zone (N3), and described negative electrode is arranged on the described first expansion phosphorus zone (N2) and the short base of described the 2nd P type (P2).
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Cited By (3)
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| CN107644905A (en) * | 2017-10-25 | 2018-01-30 | 启东吉莱电子有限公司 | A kind of high voltage planar thyristor device and preparation method thereof |
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