CN103294087A - Periodical analog voltage signal generating circuit - Google Patents
Periodical analog voltage signal generating circuit Download PDFInfo
- Publication number
- CN103294087A CN103294087A CN2012100542171A CN201210054217A CN103294087A CN 103294087 A CN103294087 A CN 103294087A CN 2012100542171 A CN2012100542171 A CN 2012100542171A CN 201210054217 A CN201210054217 A CN 201210054217A CN 103294087 A CN103294087 A CN 103294087A
- Authority
- CN
- China
- Prior art keywords
- switch
- output terminal
- control
- control signal
- voltage signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a periodical analog voltage signal generating circuit, comprises a resistor, a first switch, a current source, a capacitor and a gating device, wherein the switch end of the first switch is on and off periodically and alternately under the control of a first control signal; the gating device comprises a control end, an output end and two gating ends which are alternative; the control end of the gating device receives a second control signal, with the period as same as that of the first signal, of square wave; in each period, the initial phases of the second control signal and the first control signal are identical; the square wave width, with the absolute value more than electrical level, of the second control signal is less than the square wave width, with the absolute value more than electrical level, of the first signal; and the gating device switches on the output end and the first gating end or the output end and the second gating end.
Description
Technical field
The present invention relates to a kind of periodicity simulation voltage signal generation circuit, relate more specifically to a kind of periodicity simulation voltage signal generation circuit that can suppress the Slew Rate of this rising edge of periodically simulating voltage signal.
Background technology
Periodically simulate voltage signal generation circuit more and more widely application is arranged in integrated circuit now, especially in the DCDC switching power source chip, the periodicity simulation voltage signal of periodically simulating voltage signal generation circuit output is the important parameter that determines the DCDC duty cycle of switching.The one-period of this periodic periodicity simulation voltage signal is made of two parts usually: a part is zero level, and another part is the level of the triangular wave of pulsewidths such as square wave stack and this square wave.
Fig. 1 is the structured flowchart of the periodicity simulation voltage signal generation circuit of the above-mentioned periodicity simulation of generation of the prior art voltage signal.In periodicity simulation voltage signal generation circuit 1 shown in Figure 1, V
CCRepresent that this periodically simulates the power supply of the portions of electronics device of voltage signal generation circuit 1, V
OUT1Represent that this periodically simulates the output voltage signal of voltage signal generation circuit 1, this is periodically simulated voltage signal generation circuit 1 and produces the above voltage signal V that periodically simulates
OUT1Principle of work as follows:
As shown in Figure 1, an end ground connection of resistance R; One switch terminals P1 ground connection of first switch S 1, the other end of its another switch terminals P2 and resistance R is electrically connected, the first control signal CS1 of its control end C1 receiving cycle square wave, two switch terminals P1, P2 of described first switch S 1 are switched on or switched off under the control of the first control signal CS1; Current source I
Source1An end connect power supply V
CC, current source I
Source1The other end and the other end P2 of first switch S 1 be electrically connected current source I
Source1The output current signal identical with this first control signal CS1 period T under the control of the first control signal CS1, and when first switch S 1 is connected, the current signal I of output steady current
Bias1, when first switch S 1 disconnected, output was from constant electric current I
Bias1The linear current signal I that increases of beginning
Linear1
Periodically simulate in the voltage signal generation circuit 1 at this, first switch S 1 for example is V at high level
CCIn time, connect, and disconnects when low level for example is the level GND of ground connection, and the other end P2 of first switch S 1 connects the output terminal OUT1 that periodically simulates voltage signal generation circuit 1 and periodically simulates voltage signal V with output
OUT1Fig. 2 is the oscillogram of periodically simulating the main node of voltage signal generation circuit 1.Below, in conjunction with Fig. 1 and Fig. 2 the course of work of periodically simulating voltage signal generation circuit 1 is described in detail.
When the first control signal CS1 is high level V
CCThe time, first switch S 1 is connected, and the output terminal OUT1 that then periodically simulates voltage signal generation circuit 1 is connected the voltage signal V of output with ground
OUT1Level GND for ground connection; When the first control signal CS1 by high level V
CCWhen becoming low level GND, first switch S 1 disconnects, and periodically simulates the voltage signal V of the output terminal OUT1 output of voltage signal generation circuit 1
OUT1Be current source I
Source1The electric current I of output
Linear1With the product of resistance R, again, at the first control signal CS1 by high level V
CCBecome the moment of low level GND, current source I
Source1The electric current of output is I
Bias1, therefore, at the first control signal CS1 by high level V
CCBecome the moment of low level GND, periodically simulate the voltage signal V of voltage signal generation circuit 1 output
OUT1Be I
Bias1Multiply by resistance R, i.e. voltage V shown in Fig. 2
Bias1, when the first control signal CS1 is low level, periodically simulate the voltage signal V of voltage signal generation circuit 1 output
OUT1From voltage V
Bias1Beginning is along with I
Linear1Linearity increase and correspondingly increase V as shown in Figure 2
Linear1
But, owing to reasons such as manufacturing process, there is a stray capacitance over the ground all the time in the output terminal OUT1 of the periodicity simulation voltage signal generation circuit 1 in the practical application, capacitor C as shown in frame of broken lines among Fig. 1 ', particularly this periodically simulates voltage signal generation circuit 1 when being applied in the High-Frenquency Electronic Circuit, and it is very important that stray capacitance becomes.One of them problem is exactly because the existence of this stray capacitance C ' causes this output of periodically simulating voltage signal generation circuit 1 periodically to simulate voltage signal V
OUT1Rising to high level by low level has certain time delay, and can increase this time delay along with the increase of stray capacitance, and this phenomenon just makes periodically simulates voltage signal V
OUT1Rising edge a Slew Rate is arranged, Slew Rate as shown in Figure 2 (slew rate).
Summary of the invention
Propose the present invention in order to overcome the above-mentioned problems in the prior art, the purpose of this invention is to provide a kind of periodicity simulation voltage signal generation circuit that can suppress the Slew Rate of this rising edge of periodically simulating voltage signal.
The periodicity simulation voltage signal generation circuit that the present invention relates to comprises: resistance, one end ground connection; First switch that comprises control end and two switch terminals, the other end of one switch terminals and described resistance is electrically connected, first control signal of its control end receiving cycle square wave, two switch terminals of described first switch alternately switch on and off under the control of first control signal periodically; Current source, the one end connects power supply, and a switch terminals of the other end and described first switch is electrically connected, and described current source is exported the current signal identical with the described first control signal cycle under the control of first control signal; Electric capacity, one end ground connection, another switch terminals of the other end and described first switch is electrically connected; Comprise control end, the gate of two gating ends of output terminal and alternative, a described switch terminals of the first gating end and described first switch is electrically connected, the second gating termination, one level, the output terminal of described gate is as the output terminal of described periodicity simulation voltage signal generation circuit, second control signal of the square wave of its control end reception and the described first control signal same period, it is in each cycle, described second control signal is identical with the start-phase of described first control signal, the square width of described second control signal is less than the square width of described first control signal, described square width refers to that the absolute value of control signal is greater than the square width of described level, described gate is connected described output terminal and the described first gating end or described output terminal and the described second gating end under the control of described second control signal, and during connecting described output terminal and the described first gating end, described output terminal is exported the voltage signal of the product of the current signal of described current source and described resistance, connect described output terminal and with the described second gating end during, described output terminal is exported the voltage signal of described level.
Further, described level is ground level.
Further, the gate of the periodicity simulation voltage signal generation circuit that the present invention relates to comprises: second switch, its two ends are electrically connected described output terminal and the described first gating end respectively, and connect corresponding to described gate during the output terminal and the described first gating end of described gate, described second switch is in on-state; The 3rd switch, its two ends are electrically connected output terminal and the described second gating end of described gate respectively, and connect corresponding to described gate during the output terminal and the described second gating end of described gate, and described the 3rd switch is in on-state; Described second switch disconnects during described the 3rd switch connection, and connects at described the 3rd switch off period.
Further, the concrete structure of the gate of the periodicity simulation voltage signal generation circuit that the present invention relates to is: described second switch is for comprising input end, first transmission gate of output terminal and two control ends, the input end of described first transmission gate is electrically connected the described first gating end, the output terminal of described first transmission gate is electrically connected the output terminal of described periodicity simulation voltage signal generation circuit, one control end of described first transmission gate receives described second control signal, another control end of described first transmission gate receives the inversion signal of described second control signal, and during described second switch connection, described first transmission gate is in on-state; Described the 3rd switch is for containing input end, second transmission gate of output terminal and two control ends, the input end grounding of described second transmission gate, the output terminal of the output terminal of described second transmission gate and described periodicity simulation voltage signal generation circuit is electrically connected, one control end of described second transmission gate receives described second control signal, another control end of described second transmission gate and another control end of described first transmission gate are electrically connected and receive the inversion signal of described second control signal, and during described the 3rd switch connection, described second transmission gate is in on-state.
Further, described first switch of the periodicity simulation voltage signal generation circuit that present disclosure relates to is the NMOS pipe, the described other end of its source electrode and described electric capacity is electrically connected, and its drain electrode is electrically connected with the described other end of described resistance, and its grid receives described first control signal.
Further, the described current source of the periodicity simulation voltage signal generation circuit that the present invention relates to is during described first switch connection, the current signal of output steady current, and at the described first switch off period, output begins the linear current signal that increases from described constant electric current.
Description of drawings
The general structure that realizes each feature of the present invention is hereinafter described with reference to the accompanying drawings.The accompanying drawing that provides and associated description are used for the explanation embodiments of the invention, but are not limited to the present invention.
Fig. 1 is the structured flowchart of the periodicity simulation voltage signal generation circuit of prior art.
Fig. 2 is the oscillogram that the periodicity of prior art is simulated the main node of voltage signal generation circuit.
Fig. 3 is the structured flowchart of the periodicity simulation voltage signal generation circuit of embodiments of the invention.
Fig. 4 is the circuit diagram of the periodicity simulation voltage signal generation circuit of embodiments of the invention.
Fig. 5 is the oscillogram that the periodicity of embodiments of the invention is simulated the main node of voltage signal generation circuit.
Embodiment
Below, describe for realizing preference pattern of the present invention (hereinafter referred to as embodiment).In addition, below Xu Shu embodiment is the preferred embodiments of the present invention, has therefore added technical desirable various restrictions, but scope of the present invention just is not limited to these modes as long as be not particularly limited the record of the meaning of the present invention in the following description.
At first, with reference to Fig. 3-Fig. 5, the concrete structure of the periodicity of embodiments of the present invention being simulated voltage signal generation circuit 2 describes.
Fig. 3 is the structured flowchart of the periodicity simulation voltage signal generation circuit of embodiments of the invention.With reference to Fig. 3, the periodicity simulation voltage signal generation circuit 2 that the present invention relates to comprises: resistance R, one end ground connection; First switch S 1 that comprises control end C1 and two switch terminals P1, P2, the other end of one switch terminals P2 and resistance R is electrically connected, the first control signal CS1 of its control end C1 receiving cycle square wave, two switch terminals P1, the P2 of first switch S 1 alternately connect (S1 On) periodically and disconnect (S1 Off) under the control of the first control signal C1; Current source I
Source2, the one end connects power supply V
CC, a switch terminals P2 of the other end and described first switch S 1 is electrically connected, described current source I
Source2The output current signal identical with the described first control signal CS1 period T under the control of the first control signal CS1; Capacitor C, one end ground connection, another switch terminals P1 of the other end and described first switch S 1 is electrically connected; Comprise two gating end P3 of control end C2, output terminal OUT2 and alternative, the gate D of P4, a switch terminals P2 of the first gating end P3 and first switch S 1 is electrically connected, and the second gating end P4 meets a level V
P4The output terminal OUT2 of gate D is as the output terminal OUT2 that periodically simulates voltage signal generation circuit 2, the second control signal CS2 of the square wave of its control end C2 reception and the first control signal CS1 same period T, it is in each period T, the second control signal CS2 is identical with the start-phase of the first control signal CS1, and the absolute value of the second control signal CS2 is greater than level V
P4Square width W2 less than the absolute value of the first control signal CS1 greater than level V
P4Square width W1, gate D connects output terminal OUT2 and the first gating end P3 or output terminal OUT2 and the second gating end P4 under the control of the second control signal CS2, and during connecting output terminal OUT2 and the first gating end P3, output terminal OUT2 output current source I
Source2Current signal I
Linear2Voltage signal V with the product of resistance R
Linear2, connect output terminal OUT2 and with the second gating end P4 during, the voltage signal of output terminal OUT2 output level.
In the periodicity simulation voltage signal generation circuit 2 of embodiments of the invention, the level here can be ground level GND.
In the periodicity simulation voltage signal generation circuit 2 of embodiments of the invention, gate D can comprise following electron device: second switch S2, its two ends are electrically connected output terminal OUT2 and the first gating end P3 respectively, and connect corresponding to gate D during the output terminal OUT2 and its first gating end P3 of gate D, second switch S2 is in on-state (S2 On); The 3rd switch S 3, its two ends are electrically connected gate D output terminal OUT2 and the second gating end P4 respectively, and connect corresponding to gate D during the output terminal OUT2 and the second gating end P4 of gate D, and the 3rd switch S 3 is in on-state (S3 On); Second switch S2 disconnects (S2 Off) during the 3rd switch S 3 is connected, and connects during the 3rd switch S 3 disconnects (S3 Off).
Fig. 4 is the circuit diagram of the periodicity simulation voltage signal generation circuit of embodiments of the invention.As shown in Figure 4, in the periodicity simulation voltage signal generation circuit 2 of one embodiment of the present of invention, second switch S2 is the first transmission gate TG1 that comprises input end, output terminal and two control ends, the input end of the first transmission gate TG1 is electrically connected the first gating end P3, the output terminal of the first transmission gate TG1 is electrically connected the output terminal OUT2 that periodically simulates voltage signal generation circuit 2, the control end C3 of the first transmission gate TG1 receives the described second control signal CS2, and another control end C4 of the first transmission gate TG1 receives the inversion signal of the second control signal CS2
And during second switch S2 connection, the first transmission gate TG1 is in on-state; The 3rd switch S 3 is for containing the second transmission gate TG2 of input end, output terminal and two control ends, the input end grounding of the second transmission gate TG2, the output terminal OUT2 of the output terminal of the second transmission gate TG2 and described periodicity simulation voltage signal generation circuit 2 is electrically connected, the control end C6 of the second transmission gate TG2 receives the described second control signal CS2, and another control end C4 of another control end C5 of the second transmission gate TG2 and the first transmission gate TG1 is electrically connected and receives the inversion signal of the described second control signal CS
And during 3 connections of the 3rd switch S, the second transmission gate TG2 is in on-state.
An object lesson as first switch S 1 of embodiments of the invention, first switch S 1 is NMOS pipe NMOS, the other end of its source electrode P1 and capacitor C is electrically connected, and the other end of its drain electrode P2 and resistance R is electrically connected, and its grid C1 receives the first control signal CS1.
In the periodicity simulation voltage signal generation circuit 2 of one embodiment of the present of invention, as shown in Figure 5, current source I
Source2During first switch S 1 is connected, the current signal I of output steady current
Bias2, and at first switch S, 1 off period, output is from constant electric current I
Bias2The linear current signal I that increases of beginning
Linear2Here, the current signal I of steady current
Bias2Can be the current signal I with steady current
Bias1Identical current signal, the linear current signal I that increases
Linear2Can be the current signal I that increases with linearity
Linear1Identical current signal.
Then, with reference to Fig. 4-Fig. 5, the course of work of the periodicity of embodiments of the present invention being simulated voltage signal generation circuit 2 describes.
Below, with the one-period T of the first control signal CS1 and the second control signal CS2, namely the one-period t from moment T1 to moment T4 shown in Fig. 5 describes.As implied above, the first control signal CS1 comprises identical start-phase with the second control signal CS2, i.e. moment T1 shown in Fig. 5.During from moment T1 to moment T2, first control signal is high level V
CC, then NMOS pipe conducting, the voltage at capacitor C two ends is electric current I
Bias2With the product of resistance R, i.e. V shown in Fig. 5
Bias2During from moment T1 to moment T2, the second control signal CS2 is high level V
CC, the second transmission gate TG2 is at the second control signal CS2 and its inversion signal
Effect under conducting, the first transmission gate TG1 turn-offs, at this moment, the output terminal OUT that periodically simulates voltage signal generation circuit 2 directly links to each other with ground, output ground signalling GND.At moment T2, the second control signal CS2 becomes V by high level
CCBe low level GND, the second transmission gate TG2 turn-offs, and the first transmission gate TG1 is at the second control signal CS2 and its inversion signal
Effect under conducting, and the first control signal CS1 still is high level V during the time Δ t from moment T2 to T3 constantly
CC, namely the NMOS pipe still is conducting state in the Δ t time period, namely carries out from the switching of second transmission gate TG2 to the first transmission gate TG1 at moment T2, after the time period, NMOS just switches to shutoff from conducting through Δ t.Again, in the Δ t time period, the voltage at electric capacity two ends is V
Bias2, namely the voltage of ordering of the Vcpre among Fig. 4 is V
Bias2, face becomes path through the first transmission gate TG1 to output terminal OUT2 from the NMOS pipe during this period, equates with the voltage that Vcpre is ordered so periodically simulate the voltage of the output terminal OUT of voltage signal generation circuit 2, i.e. V
Bias2, then at moment T3, the first control signal CS1 is by high level V
CCBe low level GND, NMOS manages shutoff, and in the time period from moment T3 to moment T4, the NMOS pipe is in off state, and the first transmission gate TG1 is in conducting state, and the second transmission gate TG2 is in off state, periodically simulates the output voltage V of voltage signal generation circuit 2
OUTBe current source I
Source2The electric current I of output
Linear2Product V with resistance R
Linear2
At last, in conjunction with the periodicity simulation voltage signal generation circuit 2 in periodicity simulation voltage signal generation circuit 1 of the prior art and the embodiment of the invention, to V
OUT1And V
OUT2Compare from the moment that is risen to high level by low level, suppress the periodicity simulation voltage signal V of its outputs with the periodicity simulation voltage signal generation circuit 2 in the explanation embodiments of the invention
OUT2The principle of Slew Rate (slew rate) of rising edge.
In the periodicity simulation voltage signal generation circuit 1 in the prior art, as shown in Figure 2, NMOS switches to shutoff at moment T3 by conducting, periodically simulates the periodicity simulation voltage signal V of voltage signal generation circuit 1 output
OUT1Rise to voltage V from ground potential GND
Bias1, this moment is owing to be subjected to the influence of stray capacitance C ', V
OUT1From rising to V by ground level GND
Bias1Arranged, namely at V certain time delay
OUT1Rising edge a Slew Rate (slew rate) (as shown in Figure 2) is arranged.Periodically simulating in the voltage signal generation circuit 2 according to an embodiment of the invention, because the T2 of NMOS before turn-offing turn-offed the second transmission gate TG2 constantly earlier, conducting simultaneously the first transmission gate TG1, because the voltage of electric capacity can not suddenly change, the voltage on the capacitor C is V at this moment
Bias2, namely the Vcpre voltage of ordering is V
Bias2, at this moment, become path through the first transmission gate TG1 to output terminal OUT2 from the NMOS pipe, so the voltage V of output terminal OUT2
OUT2Equate with the voltage that Vcpre is ordered, be V
Bias2, then directly from V
Bias2Beginning is linear to be increased.This shows the periodicity simulation voltage signal V in the prior art
OUT1Rise to V from ground potential GND
Bias1Switch to shutoff by the NMOS pipe by conducting and realize, and the simulation of the periodicity among the present invention voltage signal V
OUT2Rise to from V from ground potential GND
Bias2Be to utilize the voltage at capacitor C two ends not suddenly change to obtain, thereby eliminated the voltage V with respect to output terminal OUT1 in the prior art effectively
OUT1The V that is risen to by ground level GND
Bias1Time delay.
As a conversion example of embodiments of the invention, current source also can be by the electric current I that can produce with embodiments of the invention
Source2The a plurality of current sources of same waveform as constitute.
As another conversion example of embodiments of the invention, second switch S2 and the 3rd switch S 3 also can be by comprising that other electronic components or the electronic circuit that can control turn-on and turn-off constitute.
In addition; for each selected in embodiments of the present invention device; those skilled in the art are based on the common practise of this area; PMOS can be managed the corresponding NMOS of replacing with pipe; NMOS is managed the corresponding PMOS of replacing with pipe; also can select for use other devices that can realize identical function to substitute each selected in the above-described embodiments device, the perhaps connected mode between each device of corresponding change, these do not break away from protection scope of the present invention.
Though specific implementations of the present invention is described, this embodiment is just explained by the mode of example, and be not intended to limit the scope of the invention.In fact, reference voltage generating circuit described herein can be implemented by various other forms; In addition, also can carry out to reference voltage generating circuit described herein various omissions, substitute and change and do not deviate from spirit of the present invention.Attached claim and the purpose of equivalents thereof are to contain such various forms or the modification that falls in the scope and spirit of the present invention.
Claims (6)
1. a periodicity is simulated voltage signal generation circuit, it is characterized in that, comprising:
Resistance, one end ground connection;
First switch that comprises control end and two switch terminals, the other end of one switch terminals and described resistance is electrically connected, first control signal of its control end receiving cycle square wave, two switch terminals of described first switch alternately switch on and off under the control of first control signal periodically;
Current source, the one end connects power supply, and a switch terminals of the other end and described first switch is electrically connected, and described current source is exported the current signal identical with the described first control signal cycle under the control of first control signal;
Electric capacity, one end ground connection, another switch terminals of the other end and described first switch is electrically connected;
Comprise control end, the gate of two gating ends of output terminal and alternative, a described switch terminals of the first gating end and described first switch is electrically connected, the second gating termination, one level, the output terminal of described gate is as the output terminal of described periodicity simulation voltage signal generation circuit, second control signal of the square wave of its control end reception and the described first control signal same period, it is in each cycle, described second control signal is identical with the start-phase of described first control signal, the square width of described second control signal is less than the square width of described first control signal, described square width refers to that the absolute value of control signal is greater than the square width of described level, described gate is connected described output terminal and the described first gating end or described output terminal and the described second gating end under the control of described second control signal, and during connecting described output terminal and the described first gating end, described output terminal is exported the voltage signal of the product of the current signal of described current source and described resistance, connect described output terminal and with the described second gating end during, described output terminal is exported the voltage signal of described level.
2. periodicity simulation voltage signal generation circuit as claimed in claim 1 is characterized in that described level is ground level.
3. periodicity as claimed in claim 1 or 2 is simulated voltage signal generation circuit, it is characterized in that described gate comprises:
Second switch, its two ends are electrically connected output terminal and the described first gating end of described gate respectively, and connect corresponding to described gate during the output terminal and the described first gating end of described gate, and described second switch is in on-state;
The 3rd switch, its two ends are electrically connected output terminal and the described second gating end of described gate respectively, and connect corresponding to described gate during the output terminal and the described second gating end of described gate, and described the 3rd switch is in on-state;
Described second switch disconnects during described the 3rd switch connection, and connects at described the 3rd switch off period.
4. periodicity as claimed in claim 3 is simulated voltage signal generation circuit, it is characterized in that described gate comprises:
Described second switch is first transmission gate that comprises input end, output terminal and two control ends, the input end of described first transmission gate is electrically connected the described first gating end, the output terminal of described first transmission gate is electrically connected the output terminal of described periodicity simulation voltage signal generation circuit, one control end of described first transmission gate receives described second control signal, another control end of described first transmission gate receives the inversion signal of described second control signal, and during described second switch connection, described first transmission gate is in on-state;
Described the 3rd switch is for containing input end, second transmission gate of output terminal and two control ends, the input end grounding of described second transmission gate, the output terminal of the output terminal of described second transmission gate and described periodicity simulation voltage signal generation circuit is electrically connected, one control end of described second transmission gate receives described second control signal, another control end of described second transmission gate and another control end of described first transmission gate are electrically connected and receive the inversion signal of described second control signal, and during described the 3rd switch connection, described second transmission gate is in on-state.
5. periodicity simulation voltage signal generation circuit as claimed in claim 4 is characterized in that,
Described first switch is the NMOS pipe, and the described other end of its source electrode and described electric capacity is electrically connected, and its drain electrode is electrically connected with the described other end of described resistance, and its grid receives described first control signal.
6. periodicity simulation voltage signal generation circuit as claimed in claim 5 is characterized in that,
Described current source is exported the current signal of steady current during described first switch connection, and at the described first switch off period, output begins the linear current signal that increases from described constant electric current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210054217.1A CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210054217.1A CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103294087A true CN103294087A (en) | 2013-09-11 |
| CN103294087B CN103294087B (en) | 2015-01-14 |
Family
ID=49095142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210054217.1A Expired - Fee Related CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103294087B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333397A (en) * | 2018-01-12 | 2018-07-27 | 山东送变电工程有限公司 | A kind of hand-held fixed current voltage output device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1298800A1 (en) * | 2001-09-28 | 2003-04-02 | STMicroelectronics Limited | Ramp generator |
| JP2007067508A (en) * | 2005-08-29 | 2007-03-15 | Seiko Npc Corp | Sawtooth wave generating circuit and dc-dc converter |
| US20090309633A1 (en) * | 2008-06-17 | 2009-12-17 | Monolithic Power Systems | Charge pump for switched capacitor circuits with slew-rate control of in-rush current |
| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
| CN102111128A (en) * | 2009-12-23 | 2011-06-29 | 美格纳半导体有限会社 | Waveform generation circuit |
| CN102237791A (en) * | 2010-04-22 | 2011-11-09 | 通嘉科技股份有限公司 | Adaptive slope compensation module and method |
-
2012
- 2012-03-02 CN CN201210054217.1A patent/CN103294087B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1298800A1 (en) * | 2001-09-28 | 2003-04-02 | STMicroelectronics Limited | Ramp generator |
| JP2007067508A (en) * | 2005-08-29 | 2007-03-15 | Seiko Npc Corp | Sawtooth wave generating circuit and dc-dc converter |
| US20090309633A1 (en) * | 2008-06-17 | 2009-12-17 | Monolithic Power Systems | Charge pump for switched capacitor circuits with slew-rate control of in-rush current |
| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
| CN102111128A (en) * | 2009-12-23 | 2011-06-29 | 美格纳半导体有限会社 | Waveform generation circuit |
| CN102237791A (en) * | 2010-04-22 | 2011-11-09 | 通嘉科技股份有限公司 | Adaptive slope compensation module and method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333397A (en) * | 2018-01-12 | 2018-07-27 | 山东送变电工程有限公司 | A kind of hand-held fixed current voltage output device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103294087B (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103107802B (en) | There is the input/output circuitry of inductor | |
| CN102195637B (en) | Transmission gate and semiconductor device | |
| RU2010121771A (en) | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE | |
| CN105144584A (en) | Level shift circuit | |
| CN105322923A (en) | Delay line circuit and semiconductor integrated circuit | |
| US8896158B2 (en) | Variable capacitance circuit | |
| CN105183059A (en) | Digit low voltage difference voltage-stablizer and ringing elimination method thereof | |
| CN105978300A (en) | Cascading type high-voltage solid-state switch | |
| CN103944554A (en) | Level switching circuit and digital-to-analog converter | |
| CN102280872A (en) | Electrostatic-proof protection circuit | |
| JP2014072191A5 (en) | ||
| CN104991113A (en) | Zero cross detection circuit applied to high-frequency switching power supply | |
| CN103247697B (en) | Decoupling capacitor and there is the integrated circuit of this decoupling capacitor | |
| CN101542905A (en) | Inverter circuit | |
| CN101458541B (en) | High and low voltage changeover circuit | |
| CN103294087B (en) | Periodical analog voltage signal generating circuit | |
| CN103023508B (en) | Current source unit circuit of current steering type digital-to-analog converter | |
| CN103001529B (en) | A kind of surge generator | |
| CN101390352B (en) | Dual output differential line driver using single high current | |
| CN210327524U (en) | Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment | |
| CN103809646B (en) | Voltage division circuit and control method thereof | |
| CN110688264B (en) | Load simulation circuit | |
| US10164616B2 (en) | Level shift circuit | |
| CN102832790A (en) | Power generating circuit and switching circuit | |
| CN102638258A (en) | Output circuit, system including output circuit, and method of controlling output circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: RICOH MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: RICOH CO. LTD. Effective date: 20150304 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150304 Address after: Japan's Osaka Ikeda City Ji 13 No. 1 room Patentee after: Ricoh Microelectronics Co., Ltd. Address before: Japan Tokyo field area magome a chome 3 No. 6 Patentee before: Ricoh Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150114 Termination date: 20160302 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |