CN103294087B - Periodical analog voltage signal generating circuit - Google Patents
Periodical analog voltage signal generating circuit Download PDFInfo
- Publication number
- CN103294087B CN103294087B CN201210054217.1A CN201210054217A CN103294087B CN 103294087 B CN103294087 B CN 103294087B CN 201210054217 A CN201210054217 A CN 201210054217A CN 103294087 B CN103294087 B CN 103294087B
- Authority
- CN
- China
- Prior art keywords
- switch
- output terminal
- control
- control signal
- voltage signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electronic Switches (AREA)
Abstract
The invention relates to a periodical analog voltage signal generating circuit, comprises a resistor, a first switch, a current source, a capacitor and a gating device, wherein the switch end of the first switch is on and off periodically and alternately under the control of a first control signal; the gating device comprises a control end, an output end and two gating ends which are alternative; the control end of the gating device receives a second control signal, with the period as same as that of the first signal, of square wave; in each period, the initial phases of the second control signal and the first control signal are identical; the square wave width, with the absolute value more than electrical level, of the second control signal is less than the square wave width, with the absolute value more than electrical level, of the first signal; and the gating device switches on the output end and the first gating end or the output end and the second gating end.
Description
Technical field
The present invention relates to a kind of periodicity and simulate voltage signal generation circuit, relate more specifically to a kind of periodicity simulation voltage signal generation circuit that can suppress the Slew Rate of the rising edge of this periodicity analog voltage signal.
Background technology
Periodically simulation voltage signal generation circuit is in an increasingly wide range of applications in integrated circuit now, especially, in DCDC switching power source chip, the periodicity analog voltage signal that periodically simulation voltage signal generation circuit exports is the important parameter determining DCDC duty cycle of switching.The one-period of this periodic periodicity analog voltage signal is made up of two parts usually: a part is zero level, and another part is the level of the triangular wave of the pulsewidth such as square wave superposition and this square wave.
Fig. 1 is the structured flowchart of the periodicity simulation voltage signal generation circuit of the above-mentioned periodicity analog voltage signal of generation of the prior art.In the periodicity simulation voltage signal generation circuit 1 shown in Fig. 1, V
cCrepresent the power supply of the some electronic devices of this periodicity simulation voltage signal generation circuit 1, V
oUT1represent the output voltage signal of this periodicity simulation voltage signal generation circuit 1, this periodicity simulation voltage signal generation circuit 1 produces above periodicity analog voltage signal V
oUT1principle of work as follows:
As shown in Figure 1, one end ground connection of resistance R; One switch terminals P1 ground connection of the first switch S 1, the other end of its another switch terminals P2 and resistance R is electrically connected, first control signal CS1 of its control end C1 receive periodic square wave, two switch terminals P1, P2 of described first switch S 1 are switched on or switched off under the control of the first control signal CS1; Current source I
source1one end connect power supply V
cC, current source I
source1the other end and the other end P2 of the first switch S 1 be electrically connected, current source I
source1under the control of the first control signal CS1, export the current signal identical with this first control signal CS1 cycle T, and when the first switch S 1 is connected, export the current signal I of steady current
bias1, when the first switch S 1 disconnects, export from constant electric current I
bias1start the linear current signal I increased
linear1.
In this periodically simulation voltage signal generation circuit 1, the first switch S 1 is such as V at high level
cCin time, connects, and disconnects when low level is such as the level GND of ground connection, and the other end P2 of the first switch S 1 connects the output terminal OUT1 of periodically simulation voltage signal generation circuit 1 to export periodically analog voltage signal V
oUT1.Fig. 2 is the oscillogram of the main node of periodically simulation voltage signal generation circuit 1.Below, composition graphs 1 and Fig. 2 are described in detail the course of work periodically simulating voltage signal generation circuit 1.
When the first control signal CS1 is high level V
cCtime, the first switch S 1 is connected, then periodically the output terminal OUT1 of simulation voltage signal generation circuit 1 is connected to ground, the voltage signal V of output
oUT1for the level GND of ground connection; When the first control signal CS1 is by high level V
cCwhen becoming low level GND, the first switch S 1 disconnects, the voltage signal V of the periodically output terminal OUT1 output of simulation voltage signal generation circuit 1
oUT1for current source I
source1the electric current I exported
linear1with the product of resistance R, again, at the first control signal CS1 by high level V
cCbecome the moment of low level GND, current source I
source1the electric current exported is I
bias1, therefore, at the first control signal CS1 by high level V
cCbecome the moment of low level GND, the voltage signal V of periodically simulation voltage signal generation circuit 1 output
oUT1for I
bias1be multiplied by resistance R, the voltage V namely shown in Fig. 2
bias1, when the first control signal CS1 is low level, the voltage signal V of periodically simulation voltage signal generation circuit 1 output
oUT1from voltage V
bias1start along with I
linear1linear increase and correspondingly increase, V as shown in Figure 2
linear1.
But, due to reasons such as manufacturing process, all the time there is a stray capacitance over the ground in the output terminal OUT1 of the periodicity simulation voltage signal generation circuit 1 in practical application, electric capacity C ' as shown in dotted line frame in Fig. 1, when particularly this periodicity simulation voltage signal generation circuit 1 is applied in High-Frenquency Electronic Circuit, stray capacitance becomes very important.One of them problem is exactly the existence due to this stray capacitance C ', causes this periodicity to simulate the output periodically analog voltage signal V of voltage signal generation circuit 1
oUT1rise to high level by low level and have certain time delay, this time delay can increase along with the increase of stray capacitance, and this phenomenon just makes periodically analog voltage signal V
oUT1rising edge have a Slew Rate, Slew Rate as shown in Figure 2 (slew rate).
Summary of the invention
Proposing the present invention to overcome the above-mentioned problems in the prior art, the object of this invention is to provide a kind of periodicity simulation voltage signal generation circuit that can suppress the Slew Rate of the rising edge of this periodicity analog voltage signal.
The periodicity simulation voltage signal generation circuit that the present invention relates to comprises: resistance, one end ground connection, comprise the first switch of control end and two switch terminals, the other end of one switch terminals and described resistance is electrically connected, first control signal of its control end receive periodic square wave, two switch terminals of described first switch are switched in alternation periodically and disconnect under the control of the first control signal, current source, its one end connects power supply, and a switch terminals of the other end and described first switch is electrically connected, and described current source exports the current signal identical with the described first control signal cycle under the control of the first control signal, electric capacity, one end ground connection, another switch terminals electrical connection of the other end and described first switch, comprise control end, the gate of two gating ends of output terminal and alternative, a described switch terminals of the first gating end and described first switch is electrically connected, second gating termination one level, the output terminal of described gate simulates the output terminal of voltage signal generation circuit as described periodicity, its control end receives the second control signal with the square wave of described first control signal same period, it is within each cycle, described second control signal is identical with the start-phase of described first control signal, the square width of described second control signal is less than the square width of described first control signal, described square width refers to that the absolute value of control signal is greater than the square width of described level, described gate connects described output terminal and described first gating end or described output terminal and described second gating end under the control of described second control signal, and during the described output terminal of connection and described first gating end, described output terminal exports the voltage signal of the current signal of described current source and the product of described resistance, connection described output terminal and with described second gating end during, described output terminal exports the voltage signal of described level.
Further, described level is ground level.
Further, the gate of the periodicity simulation voltage signal generation circuit that the present invention relates to comprises: second switch, its two ends are electrically connected described output terminal and described first gating end respectively, and during corresponding to the described gate output terminal of connecting described gate and described first gating end, described second switch is in on-state; 3rd switch, its two ends are electrically connected the output terminal of described gate and described second gating end respectively, and during corresponding to the described gate output terminal of connecting described gate and described second gating end, described 3rd switch is in on-state; Described second switch disconnects during described 3rd switch connection, and connects at described 3rd switch off period.
Further, the concrete structure of the gate of the periodicity simulation voltage signal generation circuit that the present invention relates to is: described second switch is for comprising input end, first transmission gate of output terminal and two control ends, the described first gating end of input end electrical connection of described first transmission gate, the output terminal of described first transmission gate is electrically connected the output terminal of described periodicity simulation voltage signal generation circuit, one control end of described first transmission gate receives described second control signal, another control end of described first transmission gate receives the inversion signal of described second control signal, and during corresponding to the connection of described second switch, described first transmission gate is in on-state, described 3rd switch is for containing input end, second transmission gate of output terminal and two control ends, the input end grounding of described second transmission gate, the output terminal that the output terminal of described second transmission gate and described periodicity simulate voltage signal generation circuit is electrically connected, one control end of described second transmission gate receives described second control signal, another control end of described second transmission gate and another control end of described first transmission gate are electrically connected and receive the inversion signal of described second control signal, and during corresponding to described 3rd switch connection, described second transmission gate is in on-state.
Further, described first switch of the periodicity simulation voltage signal generation circuit that present disclosure relates to is NMOS tube, the described other end of its source electrode and described electric capacity is electrically connected, and its drain electrode is electrically connected with the described other end of described resistance, and its grid receives described first control signal.
Further, the described current source of the periodicity simulation voltage signal generation circuit that the present invention relates to is during described first switch connection, export the current signal of steady current, and at described first switch off period, export the linear current signal increased from described constant electric current.
Accompanying drawing explanation
The general structure realizing each feature of the present invention is hereafter described with reference to the accompanying drawings.The accompanying drawing provided and associated description for illustration of embodiments of the invention, but are not limited to the present invention.
Fig. 1 is the structured flowchart of the periodicity simulation voltage signal generation circuit of prior art.
Fig. 2 is the oscillogram of the main node of the periodicity simulation voltage signal generation circuit of prior art.
Fig. 3 is the structured flowchart of the periodicity simulation voltage signal generation circuit of embodiments of the invention.
Fig. 4 is the circuit diagram of the periodicity simulation voltage signal generation circuit of embodiments of the invention.
Fig. 5 is the oscillogram of the main node of the periodicity simulation voltage signal generation circuit of embodiments of the invention.
Embodiment
Below, description is used for realizing preference pattern of the present invention (hereinafter referred to as embodiment).In addition, the embodiment below described is the preferred embodiments of the present invention, therefore addition of technically desirable various restrictions, as long as but scope of the present invention is not particularly limited the record of the meaning of the present invention in the following description, be just not limited to these modes.
First, with reference to Fig. 3-Fig. 5, the concrete structure of the periodicity simulation voltage signal generation circuit 2 of embodiments of the present invention is described.
Fig. 3 is the structured flowchart of the periodicity simulation voltage signal generation circuit of embodiments of the invention.With reference to Fig. 3, the periodicity that the present invention relates to simulation voltage signal generation circuit 2 comprises: resistance R, one end ground connection; Comprise first switch S 1 of control end C1 and two switch terminals P1, P2, the other end of one switch terminals P2 and resistance R is electrically connected, first control signal CS1 of its control end C1 receive periodic square wave, two switch terminals P1, the P2 of the first switch S 1 are switched in alternation (S1 On) periodically and disconnect (S1 Off) under the control of the first control signal C1; Current source I
source2, its one end connects power supply V
cC, a switch terminals P2 of the other end and described first switch S 1 is electrically connected, described current source I
source2the current signal identical with described first control signal CS1 cycle T is exported under the control of the first control signal CS1; Electric capacity C, one end ground connection, another switch terminals P1 of the other end and described first switch S 1 is electrically connected; Comprise the gate D of two gating end P3, P4 of control end C2, output terminal OUT2 and alternative, a switch terminals P2 of the first gating end P3 and the first switch S 1 is electrically connected, and the second gating end P4 meets a level V
p4the output terminal OUT2 of gate D is as the output terminal OUT2 periodically simulating voltage signal generation circuit 2, its control end C2 receives the second control signal CS2 with the square wave of the first control signal CS1 same period T, it is in each cycle T, second control signal CS2 is identical with the start-phase of the first control signal CS1, and the absolute value of the second control signal CS2 is greater than level V
p4the square width W2 absolute value that is less than the first control signal CS1 be greater than level V
p4square width W1, gate D connects output terminal OUT2 and the first gating end P3 or output terminal OUT2 and the second gating end P4 under the control of the second control signal CS2, and connection output terminal OUT2 and the first gating end P3 during, output terminal OUT2 output current source I
source2current signal I
linear2with the voltage signal V of the product of resistance R
linear2, connection output terminal OUT2 and with the second gating end P4 during, the voltage signal of output terminal OUT2 output level.
In the periodicity simulation voltage signal generation circuit 2 of embodiments of the invention, level here can be ground level GND.
In the periodicity simulation voltage signal generation circuit 2 of embodiments of the invention, gate D can comprise following electron device: second switch S2, its two ends are electrically connected output terminal OUT2 and the first gating end P3 respectively, and during the output terminal OUT2 corresponding to gate D connection gate D and its first gating end P3, second switch S2 is in on-state (S2 On); 3rd switch S 3, its two ends are electrically connected gate D output terminal OUT2 and the second gating end P4 respectively, and during the output terminal OUT2 corresponding to gate D connection gate D and the second gating end P4, the 3rd switch S 3 is in on-state (S3 On); Second switch S2 disconnects (S2 Off) during the 3rd switch S 3 is connected, and disconnects the connection of (S3 Off) period in the 3rd switch S 3.
Fig. 4 is the circuit diagram of the periodicity simulation voltage signal generation circuit of embodiments of the invention.As shown in Figure 4, in the periodicity simulation voltage signal generation circuit 2 of one embodiment of the present of invention, second switch S2 is the first transmission gate TG1 comprising input end, output terminal and two control ends, the input end of the first transmission gate TG1 is electrically connected the first gating end P3, the output terminal OUT2 of voltage signal generation circuit 2 is periodically simulated in the output terminal electrical connection of the first transmission gate TG1, the one control end C3 of the first transmission gate TG1 receives described second control signal CS2, another control end C4 of the first transmission gate TG1 and receives the inversion signal of the second control signal CS2
and during corresponding to second switch S2 connection, the first transmission gate TG1 is in on-state; 3rd switch S 3 is the second transmission gate TG2 containing input end, output terminal and two control ends, the input end grounding of the second transmission gate TG2, the output terminal OUT2 that the output terminal of the second transmission gate TG2 and described periodicity simulate voltage signal generation circuit 2 is electrically connected, the one control end C6 of the second transmission gate TG2 receives another control end C5 of described second control signal CS2, the second transmission gate TG2 and another control end C4 of the first transmission gate TG1 and is electrically connected and receives the inversion signal of described second control signal CS
and during corresponding to the 3rd switch S 3 connection, the second transmission gate TG2 is in on-state.
As an object lesson of the first switch S 1 of embodiments of the invention, first switch S 1 is NMOS tube NMOS, the other end of its source electrode P1 and electric capacity C is electrically connected, and the other end of its drain electrode P2 and resistance R is electrically connected, and its grid C1 receives the first control signal CS1.
In the periodicity simulation voltage signal generation circuit 2 of one embodiment of the present of invention, as shown in Figure 5, current source I
source2during the first switch S 1 is connected, export the current signal I of steady current
bias2, and at the first switch S 1 off period, export from constant electric current I
bias2start the linear current signal I increased
linear2.Here, the current signal I of steady current
bias2can be the current signal I with steady current
bias1identical current signal, the linear current signal I increased
linear2the current signal I that can be and linearly increase
linear1identical current signal.
Then, with reference to Fig. 4-Fig. 5, the course of work of the periodicity simulation voltage signal generation circuit 2 of embodiments of the present invention is described.
Below, with the one-period T of the first control signal CS1 and the second control signal CS2, the one-period t from moment T1 to moment T4 namely shown in Fig. 5 is described.As implied above, the first control signal CS1 and the second control signal CS2 comprises identical start-phase, the moment T1 namely shown in Fig. 5.During from moment T1 to moment T2, the first control signal is high level V
cC, then NMOS tube conducting, the voltage at electric capacity C two ends is electric current I
bias2with the product of resistance R, the V namely shown in Fig. 5
bias2; During from moment T1 to moment T2, the second control signal CS2 is high level V
cC, the second transmission gate TG2 is at the second control signal CS2 and its inversion signal
effect under conducting, the first transmission gate TG1 turns off, and now, periodically the output terminal OUT of simulation voltage signal generation circuit 2 is directly connected to the ground, and exports ground signalling GND.At moment T2, the second control signal CS2 becomes V by high level
cCfor low level GND, the second transmission gate TG2 turns off, and the first transmission gate TG1 is at the second control signal CS2 and its inversion signal
effect under conducting, and the first control signal CS1 is still high level V during the time Δ t from moment T2 to moment T3
cC, namely NMOS tube is still conducting state in the Δ t time period, namely carries out the switching from the second transmission gate TG2 to the first transmission gate TG1 at moment T2, and after the Δ t time period, NMOS just switches to shutoff from conducting.Again, in the Δ t time period, the voltage at electric capacity two ends is V
bias2, the voltage of the Vcpre point namely in Fig. 4 is V
bias2, face becomes path through the first transmission gate TG1 to output terminal OUT2 from NMOS tube during this period, so periodically the voltage of the output terminal OUT of simulation voltage signal generation circuit 2 is equal with the voltage of Vcpre point, i.e. and V
bias2, then at moment T3, the first control signal CS1 is by high level V
cCfor low level GND, NMOS tube turns off, and from moment T3 to the time period of moment T4, NMOS tube is in off state, and the first transmission gate TG1 is in conducting state, and the second transmission gate TG2 is in off state, periodically the output voltage V of simulation voltage signal generation circuit 2
oUTfor current source I
source2the electric current I exported
linear2with the product V of resistance R
linear2.
Finally, in conjunction with the periodicity simulation voltage signal generation circuit 2 in periodicity simulation voltage signal generation circuit 1 of the prior art and the embodiment of the present invention, to V
oUT1and V
oUT2contrast from the moment being risen to high level by low level, the periodicity analog voltage signal V suppressing it to export with the periodicity simulation voltage signal generation circuit 2 illustrated in embodiments of the invention
oUT2the principle of Slew Rate (slew rate) of rising edge.
In periodicity simulation voltage signal generation circuit 1 in the prior art, as shown in Figure 2, NMOS switches to shutoff at moment T3 by conducting, the periodicity analog voltage signal V of periodically simulation voltage signal generation circuit 1 output
oUT1voltage V is risen to from ground potential GND
bias1, now owing to being subject to the impact of stray capacitance C ', V
oUT1v is risen to from by ground level GND
bias1there is certain time delay, namely at V
oUT1rising edge have a Slew Rate (slew rate) (as shown in Figure 2).Periodically simulating in voltage signal generation circuit 2 according to an embodiment of the invention, because, the NMOS T2 moment before turning off first have turned off the second transmission gate TG2, the first transmission gate TG1 of conducting simultaneously, because the voltage of electric capacity can not suddenly change, the voltage now on electric capacity C is V
bias2, namely the voltage of Vcpre point is V
bias2, now, become path through the first transmission gate TG1 to output terminal OUT2 from NMOS tube, so the voltage V of output terminal OUT2
oUT2equal with the voltage of Vcpre point, be V
bias2, then direct from V
bias2start linear increasing.As can be seen here, the periodicity analog voltage signal V in prior art
oUT1v is risen to from ground potential GND
bias1shutoff is switched to realize by NMOS tube by conducting, and the periodicity analog voltage signal V in the present invention
oUT2rise to from V from ground potential GND
bias2be utilize the voltage at electric capacity C two ends not suddenly change to obtain, thus effectively eliminate the voltage V relative to output terminal OUT1 in prior art
oUT1the V risen to by ground level GND
bias1time delay.
As an alternative of embodiments of the invention, current source also can by producing the electric current I with embodiments of the invention
source2the multiple current source of same waveform is formed.
As another alternative of embodiments of the invention, second switch S2 and the 3rd switch S 3 also can by comprising other electronic components that can control turn-on and turn-off or electronic circuit is formed.
In addition; for each device selected in embodiments of the present invention; those skilled in the art are based on the common practise of this area; NMOS tube can be replaced with by corresponding for PMOS; PMOS is replaced with by corresponding for NMOS tube; also other devices that can realize identical function can be selected to substitute each selected in the above-described embodiments device, or the connected mode between each device of corresponding change, these do not depart from protection scope of the present invention.
Although particular implementation of the present invention is described, this embodiment is just stated by the mode of example, is not intended to limit scope of the present invention.In fact, reference voltage generating circuit described herein can be implemented by other forms various; In addition, also can carry out the various omissions to reference voltage generating circuit described herein, substitute and change and do not deviate from spirit of the present invention.Attached claim and the object of equivalents thereof contain to fall into such various forms in scope and spirit of the present invention or amendment.
Claims (6)
1. periodicity simulates a voltage signal generation circuit, it is characterized in that, comprising:
Resistance, one end ground connection;
Comprise the first switch of control end and two switch terminals, the other end of one switch terminals and described resistance is electrically connected,
First control signal of its control end receive periodic square wave, two switch terminals of described first switch are switched in alternation periodically and disconnect under the control of the first control signal;
Current source, its one end connects power supply, and a switch terminals of the other end and described first switch is electrically connected, and described current source exports the current signal identical with the described first control signal cycle under the control of the first control signal;
Electric capacity, one end ground connection, another switch terminals electrical connection of the other end and described first switch;
Comprise the gate of two gating ends of control end, output terminal and alternative, the institute of the first gating end and described first switch
State a switch terminals electrical connection, second gating termination one level, the output terminal of described gate simulates the output terminal of voltage signal generation circuit as described periodicity, its control end receives the second control signal with the square wave of described first control signal same period, described second control signal is within each cycle, described second control signal is identical with the start-phase of described first control signal, the square width of described second control signal is less than the square width of described first control signal, described square width refers to that the absolute value of control signal is greater than the square width of described level, described gate connects described output terminal and described first gating end or described output terminal and described second gating end under the control of described second control signal, and during the described output terminal of connection and described first gating end, described output terminal exports the voltage signal of the current signal of described current source and the product of described resistance, connection described output terminal and with described second gating end during, described output terminal exports the voltage signal of described level.
2. periodicity as claimed in claim 1 simulates voltage signal generation circuit, and it is characterized in that, described level is ground level.
3. periodicity as claimed in claim 1 or 2 simulates voltage signal generation circuit, and it is characterized in that, described gate comprises:
Second switch, its two ends are electrically connected the output terminal of described gate and described first gating end respectively, and during corresponding to the described gate output terminal of connecting described gate and described first gating end, described second switch is in on-state;
3rd switch, its two ends are electrically connected the output terminal of described gate and described second gating end respectively, and during corresponding to the described gate output terminal of connecting described gate and described second gating end, described 3rd switch is in on-state;
Described second switch disconnects during described 3rd switch connection, and connects at described 3rd switch off period.
4. periodicity as claimed in claim 3 simulates voltage signal generation circuit, and it is characterized in that, described gate comprises:
Described second switch is the first transmission gate comprising input end, output terminal and two control ends, the described first gating end of input end electrical connection of described first transmission gate, the output terminal of described first transmission gate is electrically connected the output terminal of described periodicity simulation voltage signal generation circuit, one control end of described first transmission gate receives described second control signal, another control end of described first transmission gate receives the inversion signal of described second control signal, and during corresponding to the connection of described second switch, described first transmission gate is in on-state;
Described 3rd switch is for containing input end, second transmission gate of output terminal and two control ends, the input end grounding of described second transmission gate, the output terminal that the output terminal of described second transmission gate and described periodicity simulate voltage signal generation circuit is electrically connected, one control end of described second transmission gate receives described second control signal, another control end of described second transmission gate and another control end of described first transmission gate are electrically connected and receive the inversion signal of described second control signal, and during corresponding to described 3rd switch connection, described second transmission gate is in on-state.
5. periodicity as claimed in claim 4 simulates voltage signal generation circuit, it is characterized in that,
Described first switch is NMOS tube, and the described other end of its source electrode and described electric capacity is electrically connected, and its drain electrode is electrically connected with the described other end of described resistance, and its grid receives described first control signal.
6. periodicity as claimed in claim 5 simulates voltage signal generation circuit, it is characterized in that,
Described current source, during described first switch connection, exports the current signal of steady current, and at described first switch off period, exports the linear current signal increased from described constant electric current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210054217.1A CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210054217.1A CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103294087A CN103294087A (en) | 2013-09-11 |
| CN103294087B true CN103294087B (en) | 2015-01-14 |
Family
ID=49095142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210054217.1A Expired - Fee Related CN103294087B (en) | 2012-03-02 | 2012-03-02 | Periodical analog voltage signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103294087B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108333397A (en) * | 2018-01-12 | 2018-07-27 | 山东送变电工程有限公司 | A kind of hand-held fixed current voltage output device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1298800A1 (en) * | 2001-09-28 | 2003-04-02 | STMicroelectronics Limited | Ramp generator |
| JP2007067508A (en) * | 2005-08-29 | 2007-03-15 | Seiko Npc Corp | Sawtooth wave generating circuit and dc-dc converter |
| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
| CN102111128A (en) * | 2009-12-23 | 2011-06-29 | 美格纳半导体有限会社 | Waveform generation circuit |
| CN102237791A (en) * | 2010-04-22 | 2011-11-09 | 通嘉科技股份有限公司 | Adaptive slope compensation module and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8049551B2 (en) * | 2008-06-17 | 2011-11-01 | Monolithic Power Systems, Inc. | Charge pump for switched capacitor circuits with slew-rate control of in-rush current |
-
2012
- 2012-03-02 CN CN201210054217.1A patent/CN103294087B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1298800A1 (en) * | 2001-09-28 | 2003-04-02 | STMicroelectronics Limited | Ramp generator |
| JP2007067508A (en) * | 2005-08-29 | 2007-03-15 | Seiko Npc Corp | Sawtooth wave generating circuit and dc-dc converter |
| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
| CN102111128A (en) * | 2009-12-23 | 2011-06-29 | 美格纳半导体有限会社 | Waveform generation circuit |
| CN102237791A (en) * | 2010-04-22 | 2011-11-09 | 通嘉科技股份有限公司 | Adaptive slope compensation module and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103294087A (en) | 2013-09-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10320373B2 (en) | RF production using nonlinear semiconductor junction capacitance | |
| CN103107802B (en) | There is the input/output circuitry of inductor | |
| CN105144584A (en) | Level shift circuit | |
| RU2010121771A (en) | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE | |
| US8896158B2 (en) | Variable capacitance circuit | |
| CN105322923A (en) | Delay line circuit and semiconductor integrated circuit | |
| Jørgensen et al. | Analysis of cascaded silicon carbide MOSFETs using a single gate driver for medium voltage applications | |
| CN102684675A (en) | Level shifter | |
| CN102280872A (en) | Electrostatic-proof protection circuit | |
| CN102271300B (en) | Integrated microphone offset voltage control method and offset voltage generating circuit | |
| CN103247697B (en) | Decoupling capacitor and there is the integrated circuit of this decoupling capacitor | |
| CN103294087B (en) | Periodical analog voltage signal generating circuit | |
| CN103944554A (en) | Level switching circuit and digital-to-analog converter | |
| CN101542905A (en) | Inverter circuit | |
| CN104808731B (en) | Reference voltage circuit | |
| CN101458541B (en) | High and low voltage changeover circuit | |
| CN102545560B (en) | Power switch driver, IC chip, and DC-DC converter | |
| Lirio et al. | Switching losses analysis in sic power mosfet | |
| CN103023508B (en) | Current source unit circuit of current steering type digital-to-analog converter | |
| CN103001529B (en) | A kind of surge generator | |
| CN110688264B (en) | Load simulation circuit | |
| US10164616B2 (en) | Level shift circuit | |
| CN202424492U (en) | Power switch driver, IC (integrated circuit) chip and DC-DC converter | |
| CN104269130A (en) | Driving Circuit | |
| EP2779450B1 (en) | A method and apparatus for generating an oscillation signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: RICOH MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: RICOH CO. LTD. Effective date: 20150304 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150304 Address after: Japan's Osaka Ikeda City Ji 13 No. 1 room Patentee after: Ricoh Microelectronics Co., Ltd. Address before: Japan Tokyo field area magome a chome 3 No. 6 Patentee before: Ricoh Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150114 Termination date: 20160302 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |