CN103250251A - Ferroelectric capacitor encapsulated with hydrogen barrier - Google Patents

Ferroelectric capacitor encapsulated with hydrogen barrier Download PDF

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Publication number
CN103250251A
CN103250251A CN2010800705676A CN201080070567A CN103250251A CN 103250251 A CN103250251 A CN 103250251A CN 2010800705676 A CN2010800705676 A CN 2010800705676A CN 201080070567 A CN201080070567 A CN 201080070567A CN 103250251 A CN103250251 A CN 103250251A
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Prior art keywords
barrier layer
hydrogen barrier
integrated circuit
hydrogen
circuit according
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CN2010800705676A
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Chinese (zh)
Inventor
R·J·阿加沃尔
S·R·萨默菲尔特
G·B·巴瑟姆
T·S·莫伊兹
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Abstract

An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier (2020), and an overlying hydrogen barrier layer (2338) is provided.. A method for forming the integrated circuit containing the ferroelectric capacitor, the underlying hydrogen barrier(2020), and the overlying hydrogen barrier layer (2338) is provided.

Description

The ferroelectric condenser that uses hydrogen barrier layer to seal
Technical field
The present invention relates to integrated circuit fields; And relate more specifically to protect ferroelectric condenser not suffer the influence of hydrogen degradation.
Background technology
Summary of the invention
Description of drawings
Figure 1A-1B(prior art) and the part of Fig. 1 C-1D diagram integrated circuit.
Fig. 2 A-2E diagram is according to the step in the integrated circuit technology flow process of embodiment.
Fig. 3 A-3B diagram adds the hydrogen release film according to another embodiment.
Embodiment
Example embodiment has been described with reference to the drawings, wherein in whole accompanying drawing, has used identical Ref. No. to refer to element similar or that be equal to.The accompanying drawing not drawn on scale, and these accompanying drawings are provided only is for these example embodiment are described.Below with reference to example application some aspects have been described, in order to describe.Should be appreciated that, state that many specific detail, relation and method are for fully understanding example embodiment is provided.Yet those skilled in the art will recognize easily, can implement these example embodiment under the one or more situation in not having specific detail, or use other method to implement these example embodiment.In other examples, be not shown specifically known structure or operation, with the embodiment that avoids confusion.Example embodiment is not subjected to the restriction of the order of shown action or event because some actions can be with different occurring in sequence, and/or simultaneously and other actions or event take place.In addition, be not that all illustrated actions or event all require to realize method according to example embodiment.
Ferroelectric condenser (FeCap) is commonly used in the integrated circuit, to provide nonvolatile memory in the device such as ferroelectric (" FRAM ") memory, high K capacitor, piezoelectric device and thermoelectric device.The structure of ferroelectric condenser can be integrated in the cmos process flow, after the transistor part that forms integrated circuit (for example after " leading portion " processing), but before the metalized portion and interconnecting parts that form integrated circuit (for example in " back segment " first being processed).
Many CMOS back segment procedure of processings comprise the utilization of hydrogen.For example, hydrogen can be used to form that etching groove stops layer, etching is cleaned and copper sintering (for example, heating).During these processing steps, hydrogen may diffuse into the ferroelectric condenser material, causes the electrical characteristics of device to be degenerated (for example the switching of FRAM memory cell polarization is degenerated).Influence for the degeneration protecting FeCap not to be subjected to cause owing to hydrogen can utilize conductive hydrogen barrier layer to form the lower plate of FeCap, and the hydrogen barrier film can be deposited on the FeCap.
Term " FeCap " refers to ferroelectric condenser.The ferroelectric dielectric of FeCap can be made up of (but being not limited to) lead zirconate titanate (PZT).
Term " FeCap zone " refers to the FeCap array with two or more FeCap.
Figure 1A and Figure 1B will utilize usual manner 1000 usefulness hydrogen barrier layers to seal FeCap and compare with the execution mode 1100 of sealing fully of protecting its influence that does not suffer hydrogen degradation and present embodiment.
The integrated circuit 1000 that contains FeCap1022 among Figure 1A is formed on the substrate 1002, this substrate comprise shallow trench isolation from (" STI ") zone 1004, transistor gate 1012, transistor gate dielectric 1008 and transistor source and drain electrode 1006(its can be silication 1010).Integrated circuit 1000 also contains preceding dielectric (" the PMD ") layer 1014 of first metal, contact 1016, FeCap1022 and hydrogen barrier film 1026.Hydrogen barrier film 1026 has been deposited on the FeCap1022 top, does not suffer the influence of hydrogen degradation for the protection of the dielectric of FeCap.
Dielectric (" PMD-2 ") layer 1032 before the depositing metal above the substrate 1002 that contains FeCap1022.In PMD-2 layer 1032, form second contact 1030, be used for contacting with the top board 1024 of FeCap1022 and contacting with drain electrode 1006 with transistor source.In first order inter-metal dielectric (" IMD-1 ") 1036, form metal interconnected (" met-1 ") 1034 of the first order and metal interconnected (" met-2 ") 1042 in the second level, in second level inter-metal dielectric (" IMD-2 ") 1038, be formed for the through hole (" via-2 ") 1040 of met-2 level.Should be noted that, can utilize less or extra metal interconnected level and passivated dielectric medium level to finish integrated circuit 1000.
The enlarged drawing of FeCap1022 has been shown among Figure 1B.The base plate 1046 of FeCap1022 can be made up of conduction hydrogen barrier material, such as but not limited to TiN, TiAlN or TiAlON.Even use the hydrogen barrier material to cover FeCap as base plate 1046 and hydrogen barrier film 1026, hydrogen still may spread by the seam 1048 that forms between base plate 1046 and hydrogen barrier layer 1026.Hydrogen by seam 1048 diffusions can make the electrical characteristics of FeCap degenerate.
The embodiment that prevents that hydrogen from spreading by the seam 1148 between base plate 1146 and the hydrogen barrier layer 1126 that covers has been shown in the illustration shown in Fig. 1 D, has formed integrated circuit structure 1100 among Fig. 1 C according to this embodiment.According to this embodiment, above integrated circuit 1100 deposit bottom hydrogen barrier layer 1120.Shown in Fig. 1 D, in FeCap zone 1001, below FeCap1150, there is bottom hydrogen barrier layer 1120, this can prevent that hydrogen from spreading by seam 1148.
Shown in Fig. 2 A-2D according to the manufacture method of the formation integrated circuit of the embodiment of present embodiment.The integrated circuit 2000 that part shown in Fig. 2 A processes is structured on the substrate 2002, and comprises grid 2014 and the PMD2016 of the source diffusion region of STI2004, transistor gate dielectric 2008, transistor gate 2012, transistor source and drain electrode 2006, silication and drain diffusion regions 2010, silication.Above PMD2016 deposit bottom hydrogen barrier layer 2020.The bottom hydrogen barrier layer can be formed by one or more thin dielectric films, and for example LPCVD SiN, low hydrogen PECVD SiN(are called " UV Sin "), AlO x, AlON x, SiN xAnd SiN xH yIn the example embodiment shown in Fig. 2 A, bottom hydrogen barrier layer 2020 is SiN xH ySiN xH yFilm comprises hydrogen with the form of Si-H key and N-H key usually.Bottom hydrogen barrier layer SiN xH yAn exemplary process of film 2020 is, with high relatively nitrogen (N 2) air-flow and relative low ammonia (NH 3) air-flow utilizes plasma enhanced CVD (" PECVD ") to form low Si-H key material.This exemplary process is shown in the following table 1.Should be noted that, can utilize such as the replacement technology of high-density plasma (HDP) and produce the SiN of this example embodiment xH yThe bottom hydrogen barrier layer.
Shown in Fig. 2 A, in PMD2016, form before the electric contact piece, above integrated circuit 2000, formed photoresist contact pattern 2021, be used for exposing the position that PMD2016 is etched.Fig. 2 B illustrates and utilizes any known process technology to form contact 2018 integrated circuit 2100 afterwards, and this contact 2018 passes PMD2016 and bottom hydrogen barrier layer SiNxHy film 2020.
Fig. 2 C illustrates the exemplary step that forms FeCap2236.The layer that is deposited to form FeCap2236 comprises bottom capacitor plate 2224 and top capacitor plate 2232, and they are formed by conduction hydrogen barrier material, for example TiN, TiAlN or TiAlON.FeCap2236 also comprises top capacitor electrode 2230 and bottom capacitor electrodes 2226, and they are formed by electric conducting material, for example Pt, Pd, PdO x, IrPt alloy, Au, Ru, RuO x, (Ba, Sr, PB) RuO3, (Ba, Sr) RuO3 or LaNiO3.In addition, FeCap2236 comprises ferroelectric dielectric material 2228, for example (but being not limited to) PZT.Shown in Fig. 2 D, above integrated circuit 2200, formed FeCap photoresist figure 2233, prepare to be used for etching FeCap film 2232,2230,2228,2226,2224, in FeCap zone 2001, to form FeCap2236.
Fig. 2 D illustrates and utilizes bottom hydrogen barrier layer 2020 as etching stop layer, etching the integrated circuit 2300 behind the FeCap2236.Next, the hydrogen diffusion impervious layer 2338 that deposit covers on the top of FeCap2236, thus use the hydrogen barrier material fully to seal FeCap2236.The hydrogen barrier layer 2338 of this covering can be made up of one or more hydrogen barrier films, for example AlO x, AlON x, SiN xPerhaps SiN xH yIn Fig. 2 D, the hydrogen barrier layer 2338 of covering is illustrated as one deck, but it can be made up of one or more hydrogen barrier layer.
As described in the open 2010/0224961A1 of United States Patent (USP), hydrogen barrier film 2020 and 2338 can be by graphical and be seen Fig. 2 E from being in peripheral logic zone 2003() the transistor top carry out etching, make it possible to the interfacial state in the circuit of peripheral logic region 2003 is carried out the hydrogen passivation, and make transistorized threshold voltage (" V thus t") distribution narrow.
In another example embodiment, the hydrogen barrier layer 2338 of covering can be made up of two hydrogen diffusion barrier films.The first hydrogen barrier film that covers can be the aluminium oxide (" AlON of nitrogenize x"), can utilize physical vapor deposition (" PVD ") or atomic layer deposition (" ALD ") to come the aluminium oxide of this nitrogenize of deposit.Can pass through AlO xBe exposed to nitrogenous plasma, perhaps by in containing nitrogen environment under about 400 ℃ to AlO xAnnealing is finished AlO xNitrogenize, thereby improve the hydrogen barrier layer performance.The second hydrogen barrier film that covers can be SiN xH y, utilize the pecvd process identical with the bottom hydrogen barrier layer described in the table 1 of front to form this SiN xH y
Fig. 2 E is illustrated in extra technology to be added second layer PMD2444 and the second contact 2446(it may form by following technology, and this technology comprises that the hydrogen barrier layer 2338 that utilizes covering is as etching stop layer) afterwards integrated circuit 2400.Then, can add further interconnection layer and passivation layer to finish integrated circuit 2400.
In Fig. 3 A and Fig. 3 B, another embodiment has been shown.The hydrogen barrier layer 3020 that prevents the hydrogen influence that FeCap does not suffer to diffuse out by the seam between the hydrogen barrier layer of sealing can also prevent that hydrogen is diffused into interface 3058 and passivation interface attitude thus.The unsuitable hydrogen passivation meeting of interfacial state causes because CMOS transistor V tDistribution broadening, V tUnstable and analog transistor performance degradation and cause and make output decline.
Apply for the U. S. application 12/890 that PCT/US2010/_____(submitted to corresponding on September 24th, 2010 as the PCT that is entitled as " Hydrogen Passivation of Integrated Circuits " that submitted on December 9th, 2010,137) described, can in integrated circuit 3000, below bottom hydrogen barrier film 3020, form hydrogen release film 3022.Hydrogen release film 3022 can be SiN xH yFilm under the process conditions shown in the table 2 below, utilizes this SiN of HDP deposit xH yFilm, thus the SiNxHy film 3022 that has high concentration Si-H key formed.
Figure BDA00003316700800051
In general, the bond energy of Si-H key (for example, about 3.34eV) is lower than the bond energy (for example, about 4.05eV) of N-H key.Therefore, (for example discharge the copper annealing of hydrogen usually) during the hot working step, the Si-H key is tending towards disassociation.During the hot step of back segment (for example copper annealing), hydrogen can discharge from this hydrogen release film 3022, and can diffuse into interface 3058, then passivation interface attitude and crystal defect.Yet, upwards diffusion and FeCap is degenerated of the hydrogen that the bottom hydrogen barrier layer 3020 of present embodiment can prevent this release.The bottom hydrogen barrier film 3020 that is positioned at the top of hydrogen release film 3022 can also prevent the degeneration of passivation layer by preventing hydrogen to diffusion at a distance from the interface.
Replace the hydrogen release film 3022 of Fig. 3 A and Fig. 3 B, can use the deuterium release film to come passivation interface attitude and crystal defect.Deuterium is than hydrogen costliness, but the deuterium in the interfacial state of deuterium passivation-silicon key is more sane than the hydrogen in the interfacial state of hydrogen passivation-silicon key.Therefore, as time passes, the transistorized V on the wafer of deuterium passivation tUsually than the transistorized V on the wafer of hydrogen passivation tStable.Be similar to the hydrogen release film, the deuterium in the deuterium release film mainly is bonded to silicon (Si-D).Because the energy of Si-D key is lower to the energy of deuterium (N-D) key than nitrogen, so during high annealing, the Si-D key can dissociate, provide D-atom thus in order to carry out the passivation of interfacial state.
Can be used for preventing that photoresist from touching SiN in the optional oxide cap 3024 of the deposited on top of bottom hydrogen barrier layer 3020 xH yBottom hydrogen barrier layer 3020.When using NH 3Form SiN xH y(see top table 1) during film, residual NH 3Can stay in the film and can react with contact lithograph glue 3026, thereby make contact lithograph glue 3026 be difficult to develop and in manufacturing process, be difficult to subsequently be removed.In the embodiment shown in Fig. 3 A, contact lithograph glue 3026 is formed on the optional oxide cap.
Fig. 3 B is illustrated in and has formed first contact 3018 and removed contact lithograph glue 3026 integrated circuit 3100 afterwards.Also show FeCap3136, PMD-23444 and second contact 3446.Can carry out the extra process of other interconnection of interpolation and dielectric layer to finish integrated circuit.
Although described various embodiment above, should be appreciated that these embodiment only present by way of example, and unrestricted.Under the situation of the scope that does not depart from the present invention for required protection, according to disclosing of this paper, can carry out many changes to the disclosed embodiments.

Claims (20)

1. integrated circuit, it comprises:
Ferroelectric condenser;
The bottom hydrogen barrier layer, it is coupled to the basal surface of described ferroelectric condenser; And
The hydrogen barrier layer that covers, its part with the top surface of described bottom hydrogen barrier layer contacts.
2. integrated circuit according to claim 1, the hydrogen barrier layer of wherein said covering also is coupled to side surface and the top surface of described ferroelectric condenser.
3. integrated circuit according to claim 1, dielectric layer contacts before the metal of wherein said bottom hydrogen barrier layer and described integrated circuit.
4. integrated circuit according to claim 1, wherein said bottom hydrogen barrier layer is selected from by AlO, AlON, SiN x, SiN xH yAnd the group of combination in any composition.
5. integrated circuit according to claim 1, the hydrogen barrier layer of wherein said covering is by AlO film and the SiN of nitrogenize xH yFilm is formed.
6. integrated circuit according to claim 1, the hydrogen barrier layer of wherein said covering is SiN xH yFilm.
7. integrated circuit according to claim 1, wherein said bottom hydrogen barrier layer contacts with the base plate of described ferroelectric condenser; And the hydrogen barrier layer of described covering contacts with the top board of described ferroelectric condenser.
8. integrated circuit according to claim 1 further comprises the hydrogen release film, and described hydrogen release film is coupled to the basal surface of described bottom hydrogen barrier layer.
9. integrated circuit according to claim 8, wherein said hydrogen release film contacts with the described basal surface of described bottom hydrogen barrier layer.
10. integrated circuit according to claim 8, wherein oxide cap is coupling between the described basal surface of described bottom hydrogen barrier layer and described ferroelectric condenser.
11. integrated circuit according to claim 10, wherein said oxide cap contacts with the base plate of described ferroelectric condenser; And the hydrogen barrier layer of described covering contacts with the top board of described ferroelectric condenser.
12. integrated circuit according to claim 8, wherein said bottom hydrogen barrier layer is selected from by AlO, AlON, SiN x, SiN xH yAnd the group of combination in any composition.
13. integrated circuit according to claim 8, wherein said hydrogen release film comprises SiN xH y, this SiN xH yThe Si-H key than N-H key concentration height.
14. integrated circuit according to claim 1 further comprises the deuterium release film, described deuterium release film is coupled to the basal surface of described bottom hydrogen barrier layer.
15. integrated circuit according to claim 14, wherein oxide cap is coupling between the described basal surface of described bottom hydrogen barrier layer and described ferroelectric condenser.
16. integrated circuit according to claim 14, wherein said deuterium release film comprises SiN xD y, this SiN xD yThe Si-D key than N-D key concentration height.
17. a technology that forms integrated circuit, it comprises:
Provide and have the integrated circuit that the part of dielectric layer processes before the metal;
Deposit bottom hydrogen barrier layer on the dielectric layer before described metal; And
Above the hydrogen barrier layer of described bottom, form ferroelectric condenser.
18. technology according to claim 17 further may further comprise the steps: before the step that forms ferroelectric condenser, deposited oxide cap rock above the hydrogen barrier layer of described bottom.
19. technology according to claim 17 further may further comprise the steps: before the step of the described bottom of deposit hydrogen barrier layer, at least one in deposit hydrogen release film and the deuterium release film.
20. technology according to claim 17 further may further comprise the steps: after the step that forms ferroelectric condenser, the hydrogen barrier layer that deposit covers on described integrated circuit.
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Application publication date: 20130814