CN103235037A - Semiconductor device and manufacturing method for same - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method for the same. The invention is characterized in that the semiconductor device comprises an upper substrate and a lower substrate, a through hole, a micro inlet hole and a micro outlet hole are perforated in the upper substrate, concave pits are perforated in the bottom surface of the upper substrate, an insulating layer is arranged at the external surface of the whole upper substrate, a conductor is arranged in the through hole, the interior surface of the lower substrate has a signal processing IC, an interconnection layer and a multilayer-structured resonator are arranged on the interior surface and electrically communicated with the signal processing IC, a bottom hole is perforated in the lower substrate at a position where the resonator is located, the bottom surface of the upper substrate and the interior surface of the lower substrate are bonded together, the resonator is positioned in the concave pits in the bottom surface of the upper substrate, the conductor is communicated with the interconnection layer, and the concave pits, the micro inlet hole and the micro outlet hole form a complete flow channel, thereby obtaining the semiconductor device. According to the invention, the signal processing IC and resonator are integrated together, a micro channel is integrated on a chip, so a small size and a high integration level are realized and the semiconductor device can realize trace biological sample detection.

Description

A semiconductor device manufacturing method and semiconductor device

FIELD

[0001] The present invention relates to a semiconductor device and a method for manufacturing a thin film bulk acoustic resonator using a.

Background technique

[0002] The thin film bulk acoustic resonator having a generally sandwich-like structure of a metal electrode / piezoelectric thin film / metal electrode resonator structure, typically with gold metal electrode film layer (Au), zinc oxide piezoelectric film generally (ZnO), nitrogen aluminum (AlN) and the like; its resonance frequency, the physical characteristics of the piezoelectric film is determined by the size of the resonator structure structure, when the frequency of the excitation source device consistent with the resonance frequency, resonance occurs devices. Film bulk acoustic resonator having a high resonance frequency, small size, etc., have no access to important applications in communications. With high sensitivity biosensor technology, demand for high integration, application of such a thin film bulk acoustic resonator in the biological field sensing is also much industry attention. Biological sensing applications, the fluid typically need to establish a communication channel between the resonator and the external environment, the biological material to be detected through the fluid passage, and reach the sensitive surface of the resonator is deposited, and with the effect of the resonator surface, which will cause a change in the resonant frequency, the resonant frequency changes to be formed in the subsequent processing circuit acquires the signal, i.e. to achieve such a resonator-based bioassays. At present, it has been disclosed biosensor system based on the general wave resonator resonator provided in a separate probe, and then connected to the circuit with the processing elements and the like, which is characterized by large volume, low degree of system integration and detection It requires a large dose of a biological sample to be tested.

SUMMARY

[0003] To overcome the above conventional bio-based thin film bulk acoustic resonator detection apparatus which is bulky, low system integration, the detection process consumes a large amount of biological samples insufficient technology, the present invention provides a semiconductor device and a manufacturing method technical solutions are as follows:

[0004] As a preferred embodiment of this person, which semiconductor device can be embodied in the following aspects:

[0005] As a method of manufacturing a semiconductor device according to the present invention, which embodiment is:

[0006] A method of manufacturing a semiconductor device, comprising the steps of:

[0007] the substrate processing: processing a through hole through which the top and bottom surfaces on an upper substrate, and micro-holes into the micro-hole; then machining the bottom surface pits, each pit of said at least one communication and a micro-micro holes into the hole; then an insulating layer is provided on the entire outer surface of the upper substrate; Finally, the through hole conductor is provided, the conductive member extending to the top and bottom surfaces;

[0008] The lower base treatment: providing at the base, the lower base member having an inner surface and an opposite outer surface; on the inner surface has a signal processing 1C has completed processing, processing with electrical connections on the inner surface an interconnection layer, a multilayer structure of the resonator; the interconnect layer in electrical communication between the resonator and the signal processing IC; reprocessing a blind hole in the base body is located at a position of the resonator so that the suspended resonator;

[0009] The pressure-sensitive adhesive: the bottom surface of the base body is fitted and fixed on the inner surface of the lower substrate having the interconnect layer therebetween, the resonator is located in the pit; Meanwhile, the electrical conductor communicating with the interconnect layer to form an external circuit connected to the signal processing IC and the electrical resonator; wherein the dimples, into the micro-hole, a micro-hole to form a complete runner passage.

[0010] Preferably the method are embodied may have the following: [0011] embodiment, the through hole, into the micro pores preferred embodiment, the micro-hole, and bottomed pits can be engraved reactive ion etching or wet etching treatment; the insulating layer may be oxidized working process or vapor deposition process is made.

[0012] In the preferred embodiment, the lower base treatment step, the resonator is a three-layer structure, a vertical direction comprising: a first metal layer of the lower, middle and upper end of the intermediate layer, a second metal layer; first, using a photolithography process, forming a first metal layer of the lower end, a first metal wiring layer and the signal processing IC on the rewiring layer, the second metal layer and the electrode attached to the signal processing IC rewiring layer line mask, and then evaporated or sputtered gold layer, the release layer is formed of the first metal, the first metal wiring layer and the signal processing IC in the re-wiring layer, a second metal layer and the signal processing IC in the rewiring layer connection; and then depositing a piezoelectric thin film, photolithography, patterning the piezoelectric film to generate said intermediate layer; depositing an insulating layer, a light Hai | J, exposing the pads of the signal processing IC, said intermediate layer, and the second metal layer electrode in electrical contact with the signal processing IC on the connection window rewiring layer; finally photolithography, evaporated or sputtered gold layer forming the second metal layer is peeled off.

[0013] In the preferred embodiment, the intermediate layer material is eight 11210 ,? twenty one'.

[0014] The heat heating resistor layer and the interconnect preferred embodiment, the processing step on a substrate, processing the inner wall of the pit, so forming a patterned layer of a heating resistor, communication layer.

[0015] embodiment of the present invention has beneficial effects:

[0016] 1. The present embodiment implements the signal processing IC and the integrated thin film bulk acoustic resonators, integrated microfluidic channel on a chip, to achieve the miniaturization, high integration in biosensing applications test biological sample may be treated to reduce consumption.

[0017] 2. from the semiconductor process to make both synchronous molding, the use of sophisticated means may be a large number of conventional semiconductor process, raw

High production efficiency.

[0018] 3. The signal processing IC as an integrator resonator, a biological sensor system on a programmable chip with good capacity to adaptability, versatility.

BRIEF DESCRIPTION

[0019] The following embodiments in conjunction with the accompanying drawings of the embodiments of the present invention is further described:

[0020] Figure 1 is a schematic view of a first embodiment of the present invention, the substrate on a processing step;

[0021] FIG. 2 is a schematic view of a second embodiment of the present invention, the substrate on a processing step;

[0022] FIG. 3 is a schematic view of a third embodiment of the present invention, the substrate on a processing step;

[0023] FIG. 4 is a schematic view of a fourth embodiment of the present invention, the substrate on a processing step;

[0024] FIG. 5 is a schematic view of a fifth embodiment of the present invention, the substrate on a processing step;

[0025] FIG. 6 is an embodiment of the present invention, a schematic view of a sixth embodiment at the step of processing the substrate;

[0026] FIG. 7 is a seventh embodiment of the present invention at a substrate treating a schematic view of steps;

[0027] FIG. 8 is a sectional view according to a second embodiment of the present invention;

[0028] FIG. 9 is a sectional view according to a third embodiment of the present invention.

Detailed ways

[0029] Example a:

[0030] As shown in FIG. 1 to FIG. 7, a schematic diagram of the steps and products of the present invention embodiment. From Figures 1 to 7 shows a cross-sectional view of the present embodiment gradually illustrative embodiment of the product.

[0031] First, the substrate processing steps, including the portion shown in FIG. 1 and FIG. 2: processed 10, the fine feed holes 17 and micro outlet hole vias through the top and bottom surfaces 18 on an upper substrate I the process may be processed by reactive ion etching or wet etching process. On a substrate according to the present embodiment I is a silicon material when the through-hole 10, the fine feed holes 17 and the micro-out hole 18 molded, and then the pit I the bottom surface treatment at the substrate 40, the present embodiment pits embodiment 40 has a plurality, each of the pits 40 are in communication with a micro-feed holes 17 and a hole 18. the micro-out shown in Figure 1.

[0032] After the previous step, and then an insulating layer is provided on the entire outer surface of the upper substrate I, 11, as shown in FIG 2 on the one hand the need to consider a variety of electrical connections formed on the substrate I, and I on the base a semiconductor material, but also on the other hand the surface for subsequent process requirements. The present embodiment uses silicon dioxide insulating layer 11 molded material using an oxidation process, the actual pressure chemical vapor deposition may be employed, plasma enhanced chemical vapor deposition method.

After [0033] completing the above steps, the conductive member needs to be set in the through hole 10. The process shown in Figure 3 to 5. The process uses an auxiliary wafer 3. 3 pre-set auxiliary wafer deposited copper seed layer 32, and then coated on the bottom surface of the adhesive material 31 of the base I to the adhesive on the bottom surface of the wafer and the auxiliary base 3 I of the seed layer 32 of copper. Removing the copper seed layer 32 covering the adhesive material on the bottom of the through hole 10 is 31, herein may approach using reactive ion etching; As shown, the through hole 10 may reach the copper seed layer 323. Then, through-holes 10 of copper plating, the copper material is filled in the through hole 10, a conductor 12 is formed, as shown in FIG. Finally, removal of the auxiliary wafer 3, and the bottom surface of the substrate I is smooth, by chemical, mechanical polishing or the like, as shown, extend oriented conductive base body 12 I top and bottom surfaces shown in Fig.

After [0034] completion of the upper substrate treating step, the next substrate processing steps of: providing about 2, the lower base substrate having an inner surface and an opposite outer surface, in substantially FIG. 6 is not an inner surface of the upper, Xi Bu the lower surface. The inner surface has been treated with IC21 signal processing has been completed, the inner surface of the interconnect layer 23, and a processing resonator electrically connected with a multilayer structure 40; interconnection layer 23 and the resonator 40 and the signal processing electrical communication between the IC21, IC21 signal processing in FIG. 6 has pads 22 and interconnection layer 23 communicates in accordance with predetermined pattern. In this embodiment, the resonator 40 is a three-layer structure according to the distribution of the vertical direction comprises a first upper metal layer 43, middle layer 42 and the second intermediate metal layer 41, the lower end; and the first metal layer 43 and the first a second metal interconnect layer 41 and the layer 23 has an electrical connection. A first, a second metal layer according to the present embodiment are Au, the intermediate layer of A1N. Implementing the interconnection layer 23, the resonator 40 is the method:

[0035] First, the signal electrode 43 of the second metal layer by photolithography processing rice to prepare the first metal layer 41, a first metal wiring layer 41 to the signal processing on the interconnect layer IC21 IC21 23 in the interconnection layer 23 connecting the mask (not labeled is not), then evaporated to send radio or gold layer, a peeling layer 41 is formed of the first metal, the first metal layer 41 and the signal processing IC21 attached to the interconnect layer 23 line, the second metal layer 43 to connect the signal processing IC21 on interconnect layer 23; an insulating layer deposited films, photolithographic patterning, exposing the signal processing IC21 pad 22, the intermediate layer 42 and the second metal layer 43 in connection with the signal processing IC electrical contact window 23 on the interconnect layer; then sputter deposited to generate intermediate layer 42, photolithographic patterning the intermediate layer 42; and finally photolithography, evaporated or sputtered gold layer formed on the release a second metal layer 43.

[0036] When the resonator 40 is formed, and then the substrate 2 is located at the position of the resonator 40 a blind hole 24 of the handle so that the suspended resonator 40, the resonator 40 has a good morphology of the interference effect.

After [0037] completion of the lower base treatment step, into the bonding step, see Figure 7: a bottom surface which has been formed on the substrate I and the lower base the inner surface 2 of the fitting fixation, the present embodiment employs a graphical adhesive layer 50, the adhesive material is a layer of copper, tin, of course, may also be BCB, P1, copper, gold, alloys, gold-tin alloy and indium materials. Interconnect layer having an inner surface 23 therebetween on the substrate 2 and the lower bottom surface I of the substrate, the resonator 40 is positioned in the pit 44; at the same time, the conductive layer 12 and the interconnect 23 are connected through, and the signal constituting the external circuit processing IC21 and the resonator 40 is electrically connected; wherein the pit 44, into the hole 17 ,, the micro hole 18 formed in a micro fluid channel complete. When docked external circuit conductor 12, to monitor this parameter of the resonator 40, the micro-biological fluid injection hole 17 into the fluid pump 70, soaked in the resonator 40 after the pit 44, the resonator 40 can current data measured by the interconnection layer 23 and the signal processing IC 21, a conductive member 12 and the external control circuit to complete the communication. Be seen, the present embodiment implementing a signal processing integrated IC21 40 and the resonator, the size of the one hand, facilitate the detection of trace biological sample; on the other hand so that the two synchronized from the molding process, high efficiency, small size, especially suitable for the development of miniaturized biological detection equipment.

[0038] The present embodiment also has other features:

Actual substrate material 2 IC21 for the signal processing of the substrate [0039] of, so, when the signal processing IC21 molding, a substrate which can be directly used to make the present apparatus, is omitted additional lower base material 2, material savings and time cost semiconductor processes.

[0040] embodiment, the through hole 10 of the base I, into the micro-holes 17, the micro-apertures 18, recesses 44 and the blind hole 24 of the base body 2 can be reactive ion etching etching process, of course, the present embodiment It can be replaced by means of a wet etching process.

[0041] Example II:

[0042] As shown in FIG 8, a schematic view of second embodiment of the present invention. On a substrate I of this embodiment is a glass material, the base body 2 is also a signal processing IC21 silicon substrate. I and the structure of the substrate similar to Example 1; the pit 44, into the micro-holes 17 and the micro-apertures 18 are also similar. Employed between the substrate 2 and the lower substrate I of silicon - glass anodic bonding achieved with fixing. No additional adhesive layer material. Semiconductor processing is further simplified.

[0043] Example III:

[0044] As shown in FIG. 9, a schematic view according to a third embodiment of the present invention. This embodiment is similar to the embodiment of a configuration example, the substrate I is a baby semiconductor material, the substrate 2 where the signal processing IC21 baby substrate. The difference is that, with controlled heating resistance wire layer 45 on the inner wall of the pit 44, and the heating layer 45 in electrical communication with interconnect layer 23, thus, the conductive member 12 can also be controlled by an external circuit. The resistance wire Pt layer 45 is in the form of metal layers. Because in actual measurement, detection of biological fluid often requires a certain temperature atmosphere. By providing resistance wire layer 45 can be programmably implemented within the recesses 44 temperature (curve), easy to create a testing environment different needs. The heating layer 45 is realized in the substrate processing step I, the pit inner wall 44 is processed so shaped to form patterned layer 45 and communicating with the electric interconnection layer 23 in the bonding step.

[0045] The above are only preferred embodiments of the present invention, so it can not define the scope of the embodiments of the present invention, i.e., under this patent specification the content and scope of the invention is made such modifications and equivalent, are still present should be encompassed within the scope of the invention.

Claims (10)

1. A semiconductor device, comprising: comprising: a base body, the base body having a bottom surface opposite to a direction of the top surface and a top surface; having a through hole penetrating between the top and bottom surfaces; recess having the bottom surface pit, each pit by at least a micro-hole and into a micro the top and bottom surfaces of the bore in communication; the outer surface of a cover on the base insulating layer; and a lower base having an inner surface and an opposite inner surface direction of the an outer surface; a bottom surface of the inner surface of the upper substrate binding; having an interconnection layer between the inner surface and a bottom surface; a side surface of said inner has a signal processing IC; the pads are located in the signal processing IC said interconnection layer; wherein said pits having a multilayer structure of the resonator, the resonator in communication with the electrical interconnect layer, sealing the space between the flow channel constituting the recesses and the interconnect layer, the fine feed hole , micro-channel space and an aperture to form a complete runner passage; said lower base member having a bottom opening at a position of the resonator; said through hole on a substrate having a conductor interconnect layer of the communication, the conductive material constituting said signal processing IC, and Vibration electrical connector communicating with the outside.

2. A semiconductor device according to claim 1 claim, wherein: said resonator is a sandwich shape placed horizontally, the lower end comprising a first metal layer in the vertical direction, the upper end of the middle layer, and a second intermediate the metal layer; of the resonator of the first layer and the second metal layer and the metal interconnect layer having electrical connections.

3. A semiconductor device according to claim 1 claim, wherein: said upper having a patterned adhesive layer between the substrate and the lower substrate, the adhesive layer material may be BCB, P1, gold, copper-tin alloy, a gold-tin alloy, indium.

4. A semiconductor device as claimed in claim 1, wherein: said substrate is a glass material, the lower base body is a silicon material, a silicon between the bottom surface and the inner surface of the lower base body on the base body - glass anodic bonding with fixed achieved.

5. A semiconductor device according to the claim, characterized in that: said resistance wire pit inner wall has a controlled heating of the layer, the resistive layer and the wire in electrical communication with interconnect layer.

A method of manufacturing a semiconductor device, `characterized by: comprising the steps of: on a substrate processing: processing a through hole through which a top surface and a bottom surface on an upper substrate, fine feed holes and micro outlet hole; then machining the bottom surface pits, each pit communication with at least one inlet aperture and a micro-micro outlet hole; then in the entire outer surface of the processing substrate on the insulating layer; finishing the conductor within the through hole the electrical conductor extending to the top and bottom surfaces; lower base treatment: providing at the base, the lower base member having an inner surface and an opposite outer surface; has a signal having processed the processing performed 1C on the inner surface, processing an interconnection layer and the resonator of a multilayered structure on the inner surface; the interconnect layer in electrical communication between the resonator and the signal processing IC; reprocessing a substrate positioned in the lower position of the resonator the blind hole, so that the resonator is suspended; adhesive: on the bottom surface of the base body and the inner surface of the lower fixing fitting base body, having therebetween the interconnect layer, the resonator is located in the pit; Meanwhile, the conductor interconnect layer and Communicating, constituting an external circuit connected to the signal processing IC and the electrical resonators; wherein a seal between the recesses and the interconnect layer, so that the flow channel space constituting the inlet orifice of the micro flow path and the space micro flow passage holes to form a complete path.

6 7. A method of manufacturing a semiconductor device according to claim, characterized in that: said through-hole, into the micro-hole, a micro-hole, and bottomed pit a reactive ion etch or a wet etch process ; the insulating layer may be crafting oxidation process or a vapor deposition station.

8. The method of manufacturing a semiconductor device according to claim 6, characterized in that: said step of processing the substrate, the resonator is a three-layer structure, a vertical direction comprising: a first metal layer of the lower, middle the upper end of the intermediate layer and the second metal layer.

8 9. A method of manufacturing a semiconductor device according to claim, wherein said intermediate layer materials include AlN, ZiO or PZT.

10. A method of manufacturing a the semiconductor device according to any 6-9 claim, characterized in that: said processing step on a substrate, processing the inner wall of the pit, so that the molded pattern a layer of resistance wire, the resistance wire layer electrically connected to the interconnect layer.