CN103235037A - Semiconductor device and manufacturing method for same - Google Patents

Semiconductor device and manufacturing method for same Download PDF

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Publication number
CN103235037A
CN103235037A CN2013101143239A CN201310114323A CN103235037A CN 103235037 A CN103235037 A CN 103235037A CN 2013101143239 A CN2013101143239 A CN 2013101143239A CN 201310114323 A CN201310114323 A CN 201310114323A CN 103235037 A CN103235037 A CN 103235037A
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layer
resonator
hole
substrate
micro
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CN2013101143239A
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Chinese (zh)
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马盛林
秦利锋
孙道恒
刘兴伟
黄裕茜
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厦门大学
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Abstract

The invention discloses a semiconductor device and a manufacturing method for the same. The invention is characterized in that the semiconductor device comprises an upper substrate and a lower substrate, a through hole, a micro inlet hole and a micro outlet hole are perforated in the upper substrate, concave pits are perforated in the bottom surface of the upper substrate, an insulating layer is arranged at the external surface of the whole upper substrate, a conductor is arranged in the through hole, the interior surface of the lower substrate has a signal processing IC, an interconnection layer and a multilayer-structured resonator are arranged on the interior surface and electrically communicated with the signal processing IC, a bottom hole is perforated in the lower substrate at a position where the resonator is located, the bottom surface of the upper substrate and the interior surface of the lower substrate are bonded together, the resonator is positioned in the concave pits in the bottom surface of the upper substrate, the conductor is communicated with the interconnection layer, and the concave pits, the micro inlet hole and the micro outlet hole form a complete flow channel, thereby obtaining the semiconductor device. According to the invention, the signal processing IC and resonator are integrated together, a micro channel is integrated on a chip, so a small size and a high integration level are realized and the semiconductor device can realize trace biological sample detection.

Description

一种半导体装置以及该半导体装置的制作方法 A semiconductor device manufacturing method and semiconductor device

技术领域 FIELD

[0001] 本发明涉及一种运用薄膜体声波谐振器的半导体装置及其制作方法。 [0001] The present invention relates to a semiconductor device and a method for manufacturing a thin film bulk acoustic resonator using a.

背景技术 Background technique

[0002] 薄膜体声波谐振器一般具有类似三明治结构的金属电极/压电薄膜/金属电极谐振器结构,金属电极一般采用金薄膜层(Au),压电薄膜一般采用氧化锌(ZnO)、氮化铝(AlN)等;其谐振频率由谐振器结构的结构尺寸、压电薄膜的物理特性决定,当激励源频率与器件谐振频率一致时,器件发生谐振。 [0002] The thin film bulk acoustic resonator having a generally sandwich-like structure of a metal electrode / piezoelectric thin film / metal electrode resonator structure, typically with gold metal electrode film layer (Au), zinc oxide piezoelectric film generally (ZnO), nitrogen aluminum (AlN) and the like; its resonance frequency, the physical characteristics of the piezoelectric film is determined by the size of the resonator structure structure, when the frequency of the excitation source device consistent with the resonance frequency, resonance occurs devices. 薄膜体声波谐振器具有高谐振频率、小体积等优点,已经在无通信领域获得重要应用。 Film bulk acoustic resonator having a high resonance frequency, small size, etc., have no access to important applications in communications. 随着生物传感技术对高灵敏度、高集成度的需求,这类薄膜体声波谐振器在生物传感检测领域的应用研究也备受业界重视。 With high sensitivity biosensor technology, demand for high integration, application of such a thin film bulk acoustic resonator in the biological field sensing is also much industry attention. 在生物传感检测应用方式中,通常需要建立沟通外界环境与谐振器之间的流体通道,待检测生物物质通过流体通道,到达并沉积在谐振器敏感面,然后与谐振器表面发生作用,这将造成谐振频率的改变,谐振频率变化将被后续处理电路获取形成信号,如此即实现了基于谐振器的生物检测。 Biological sensing applications, the fluid typically need to establish a communication channel between the resonator and the external environment, the biological material to be detected through the fluid passage, and reach the sensitive surface of the resonator is deposited, and with the effect of the resonator surface, which will cause a change in the resonant frequency, the resonant frequency changes to be formed in the subsequent processing circuit acquires the signal, i.e. to achieve such a resonator-based bioassays. 目前,已公开的基于波谐振器的生物传感系统一般将谐振器设置在单独的探头中,然后连接于带有处理元件的电路等,其特点是体积大、系统集成度低,而且检测中需要大剂量的待测生物样本。 At present, it has been disclosed biosensor system based on the general wave resonator resonator provided in a separate probe, and then connected to the circuit with the processing elements and the like, which is characterized by large volume, low degree of system integration and detection It requires a large dose of a biological sample to be tested.

发明内容 SUMMARY

[0003]为克服上述现有基于薄膜体声波谐振器的生物检测装置其体积大、系统集成度低、检测过程消耗生物样本量大等技术不足,本发明提出一种半导体装置及其制作方法,其技术方案如下: [0003] To overcome the above conventional bio-based thin film bulk acoustic resonator detection apparatus which is bulky, low system integration, the detection process consumes a large amount of biological samples insufficient technology, the present invention provides a semiconductor device and a manufacturing method technical solutions are as follows:

[0004] 作为本方案的优选者,其半导体装置可以有如下方面的体现: [0004] As a preferred embodiment of this person, which semiconductor device can be embodied in the following aspects:

[0005] 作为本发明半导体装置的制作方法,其方案是: [0005] As a method of manufacturing a semiconductor device according to the present invention, which embodiment is:

[0006] 一种半导体装置的制造方法,包括以下步骤: [0006] A method of manufacturing a semiconductor device, comprising the steps of:

[0007] 上基体处理:在一上基体上加工出贯穿其顶面和底面的通孔、微进孔和微出孔;然后在其底面上加工凹坑,每个凹坑至少连通一个所述微进孔和一个微出孔;再在整个该上基体的外表面设置一层绝缘层;最后在所述通孔内设置导电体,该导电体延伸至所述顶面和底面; [0007] the substrate processing: processing a through hole through which the top and bottom surfaces on an upper substrate, and micro-holes into the micro-hole; then machining the bottom surface pits, each pit of said at least one communication and a micro-micro holes into the hole; then an insulating layer is provided on the entire outer surface of the upper substrate; Finally, the through hole conductor is provided, the conductive member extending to the top and bottom surfaces;

[0008] 下基体处理:提供一下基体,该下基体具有一内表面和其相反的外表面;在该内表面上已经具有已完成加工的信号处理1C,在该内表面上加工带有电气连接的一互连层、一多层结构的谐振器;所述互连层与该谐振器与信号处理IC之间电气连通;再在该下基体位于该谐振器的位置处理一底孔,使该谐振器悬空; [0008] The lower base treatment: providing at the base, the lower base member having an inner surface and an opposite outer surface; on the inner surface has a signal processing 1C has completed processing, processing with electrical connections on the inner surface an interconnection layer, a multilayer structure of the resonator; the interconnect layer in electrical communication between the resonator and the signal processing IC; reprocessing a blind hole in the base body is located at a position of the resonator so that the suspended resonator;

[0009] 粘合:将所述上基体的底面与该下基体的内表面配合固定,二者之间具有所述互连层,所述谐振器位于该凹坑中;同时,所述导电体与互连层相连通,构成外部电路与所述信号处理IC和谐振器的电气连接;其中,所述凹坑、微进孔、微出孔形成完整的流道通路。 [0009] The pressure-sensitive adhesive: the bottom surface of the base body is fitted and fixed on the inner surface of the lower substrate having the interconnect layer therebetween, the resonator is located in the pit; Meanwhile, the electrical conductor communicating with the interconnect layer to form an external circuit connected to the signal processing IC and the electrical resonator; wherein the dimples, into the micro-hole, a micro-hole to form a complete runner passage.

[0010] 该方法的优选者可以有如下体现:[0011] 较佳实施例中,所述通孔、微进孔、微出孔、凹坑和底孔可采用反应离子刻蚀或湿法刻蚀处理;所述绝缘层可用氧化工工艺或气相沉积的工艺制成。 [0010] Preferably the method are embodied may have the following: [0011] embodiment, the through hole, into the micro pores preferred embodiment, the micro-hole, and bottomed pits can be engraved reactive ion etching or wet etching treatment; the insulating layer may be oxidized working process or vapor deposition process is made.

[0012] 较佳实施例中,所述下基体处理步骤中,所述谐振器为三层结构,竖直方向包括:下端的第一金属层、中段的中间层以及上端的第二金属层;首先采用光刻工艺,制作该下端的第一金属层、第一金属层与该信号处理IC在重新布线层上的连线、第二金属层电极与所述信号处理IC在重新布线层的连线的掩膜,然后蒸发或溅射金层,剥离形成所述第一金属层、第一金属层与信号处理IC在重新布线层的连线、第二金属层与信号处理IC在重新布线层的连线;然后沉积压电薄膜,光刻、图形化压电薄膜,生成所述中间层;沉积绝缘层,光亥|J,暴露出所述信号处理IC的焊盘、所述中间层以及第二金属层电极与信号处理IC在重新布线层上的连线的电接触窗口;最后光刻,蒸发或溅射金层,剥离形成所述第二金属层。 [0012] In the preferred embodiment, the lower base treatment step, the resonator is a three-layer structure, a vertical direction comprising: a first metal layer of the lower, middle and upper end of the intermediate layer, a second metal layer; first, using a photolithography process, forming a first metal layer of the lower end, a first metal wiring layer and the signal processing IC on the rewiring layer, the second metal layer and the electrode attached to the signal processing IC rewiring layer line mask, and then evaporated or sputtered gold layer, the release layer is formed of the first metal, the first metal wiring layer and the signal processing IC in the re-wiring layer, a second metal layer and the signal processing IC in the rewiring layer connection; and then depositing a piezoelectric thin film, photolithography, patterning the piezoelectric film to generate said intermediate layer; depositing an insulating layer, a light Hai | J, exposing the pads of the signal processing IC, said intermediate layer, and the second metal layer electrode in electrical contact with the signal processing IC on the connection window rewiring layer; finally photolithography, evaporated or sputtered gold layer forming the second metal layer is peeled off.

[0013] 较佳实施例中,所述中间层材料为八11210、? [0013] In the preferred embodiment, the intermediate layer material is eight 11210 ,? 21'。 twenty one'.

[0014] 较佳实施例中,所述上基体处理步骤中,对所述凹坑内壁进行加工,使之成型为图案化的一加热电阻丝层,该加热电阻丝热层与所述互连层可连通。 [0014] The heat heating resistor layer and the interconnect preferred embodiment, the processing step on a substrate, processing the inner wall of the pit, so forming a patterned layer of a heating resistor, communication layer.

[0015] 本发明方案带来的有益效果有: [0015] embodiment of the present invention has beneficial effects:

[0016] 1.本方案实现了信号处理IC和薄膜体声波谐振器的整合,在片上集成了微流道,实现了小型化、高集成度,在生物传感应用中可以降低对待测生物样本的消耗量。 [0016] 1. The present embodiment implements the signal processing IC and the integrated thin film bulk acoustic resonators, integrated microfluidic channel on a chip, to achieve the miniaturization, high integration in biosensing applications test biological sample may be treated to reduce consumption.

[0017] 2.从半导体工艺上使二者同步成型,可大量运用现有半导体工艺的成熟手段,生 [0017] 2. from the semiconductor process to make both synchronous molding, the use of sophisticated means may be a large number of conventional semiconductor process, raw

产效率高。 High production efficiency.

[0018] 3.将信号处理IC与谐振器整合制作,使片上生物传感系统具备良好的可编程能力,使其适应性好,通用性强。 [0018] 3. The signal processing IC as an integrator resonator, a biological sensor system on a programmable chip with good capacity to adaptability, versatility.

附图说明 BRIEF DESCRIPTION

[0019] 以下结合附图实施例对本发明作进一步说明: [0019] The following embodiments in conjunction with the accompanying drawings of the embodiments of the present invention is further described:

[0020] 图1是本发明实施例一上基体处理步骤的第一个示意图; [0020] Figure 1 is a schematic view of a first embodiment of the present invention, the substrate on a processing step;

[0021] 图2是本发明实施例一上基体处理步骤的第二个示意图; [0021] FIG. 2 is a schematic view of a second embodiment of the present invention, the substrate on a processing step;

[0022] 图3是本发明实施例一上基体处理步骤的第三个示意图; [0022] FIG. 3 is a schematic view of a third embodiment of the present invention, the substrate on a processing step;

[0023] 图4是本发明实施例一上基体处理步骤的第四个示意图; [0023] FIG. 4 is a schematic view of a fourth embodiment of the present invention, the substrate on a processing step;

[0024] 图5是本发明实施例一上基体处理步骤的第五个示意图; [0024] FIG. 5 is a schematic view of a fifth embodiment of the present invention, the substrate on a processing step;

[0025] 图6是本发明实施例一下基体处理步骤的第六个示意图; [0025] FIG. 6 is an embodiment of the present invention, a schematic view of a sixth embodiment at the step of processing the substrate;

[0026] 图7是本发明实施例一下基体处理步骤的第七个示意图; [0026] FIG. 7 is a seventh embodiment of the present invention at a substrate treating a schematic view of steps;

[0027] 图8是本发明实施例二的剖面示意图; [0027] FIG. 8 is a sectional view according to a second embodiment of the present invention;

[0028] 图9是本发明实施例三的剖面示意图。 [0028] FIG. 9 is a sectional view according to a third embodiment of the present invention.

具体实施方式 Detailed ways

[0029] 实施例一: [0029] Example a:

[0030] 如图1至图7,本发明实施例一的步骤和产品示意图。 [0030] As shown in FIG. 1 to FIG. 7, a schematic diagram of the steps and products of the present invention embodiment. 从图1至图7展示了本实施例产品逐步实现的剖面示意。 From Figures 1 to 7 shows a cross-sectional view of the present embodiment gradually illustrative embodiment of the product.

[0031] 首先是上基体处理步骤,包括了图1和图2所示的部分:在一上基体I上加工出贯穿其顶面和底面的通孔10、微进孔17和微出孔18,加工的方法可以是反应离子刻蚀或湿法刻蚀处理。 [0031] First, the substrate processing steps, including the portion shown in FIG. 1 and FIG. 2: processed 10, the fine feed holes 17 and micro outlet hole vias through the top and bottom surfaces 18 on an upper substrate I the process may be processed by reactive ion etching or wet etching process. 本实施例的上基体I为硅材料,当通孔10、微进孔17和微出孔18成型后,然后在上基体I其底面上处理处凹坑40,本实施例中凹坑40有多个,每个凹坑40均连通了一个微进孔17和一个微出孔18.见图1所示。 On a substrate according to the present embodiment I is a silicon material when the through-hole 10, the fine feed holes 17 and the micro-out hole 18 molded, and then the pit I the bottom surface treatment at the substrate 40, the present embodiment pits embodiment 40 has a plurality, each of the pits 40 are in communication with a micro-feed holes 17 and a hole 18. the micro-out shown in Figure 1.

[0032] 完成上述步骤,再在整个该上基体I的外表面设置一层绝缘层11,如图2所示,一方面考虑到需要在上基体I上成型各种电器连接,而上基体I为半导体材料,另一方面也是为了后续表面工艺的要求。 [0032] After the previous step, and then an insulating layer is provided on the entire outer surface of the upper substrate I, 11, as shown in FIG 2 on the one hand the need to consider a variety of electrical connections formed on the substrate I, and I on the base a semiconductor material, but also on the other hand the surface for subsequent process requirements. 本实施例绝缘层11采用二氧化硅材料利用氧化工艺成型,实际也可以采用低压化学气相沉积、等离子体增强化学气相沉积等方法。 The present embodiment uses silicon dioxide insulating layer 11 molded material using an oxidation process, the actual pressure chemical vapor deposition may be employed, plasma enhanced chemical vapor deposition method.

[0033] 完成上述步骤后,需要在通孔10内设置导电体。 After [0033] completing the above steps, the conductive member needs to be set in the through hole 10. 该流程如图3至图5所示。 The process shown in Figure 3 to 5. 该流程使用了辅助晶圆3。 The process uses an auxiliary wafer 3. 辅助晶圆3预先设置好沉积的铜种子层32,然后再上基体I的底面上涂覆粘接材料31,用以粘接上基体I的底面与辅助晶圆3的铜种子层32。 3 pre-set auxiliary wafer deposited copper seed layer 32, and then coated on the bottom surface of the adhesive material 31 of the base I to the adhesive on the bottom surface of the wafer and the auxiliary base 3 I of the seed layer 32 of copper. 除去覆盖在铜种子层32在通孔10的底部的粘接材料31,此处可以使用反应离子刻蚀的办法;如图3所示,通孔10可以直达铜种子层32。 Removing the copper seed layer 32 covering the adhesive material on the bottom of the through hole 10 is 31, herein may approach using reactive ion etching; As shown, the through hole 10 may reach the copper seed layer 323. 然后,对通孔10进行铜电镀,使铜材料填充在通孔10内,形成了导电体12,如图3所示。 Then, through-holes 10 of copper plating, the copper material is filled in the through hole 10, a conductor 12 is formed, as shown in FIG. 最后去除辅助晶圆3,并使上基体I的底面平整光滑,可采用化学、机械抛光等方法,如图5所示,导电体12延伸至上基体I的顶面和底面。 Finally, removal of the auxiliary wafer 3, and the bottom surface of the substrate I is smooth, by chemical, mechanical polishing or the like, as shown, extend oriented conductive base body 12 I top and bottom surfaces shown in Fig.

[0034] 完成上述上基体处理步骤后,进入下基体处理步骤:提供一下基体2,该下基体具有一内表面和其相反的外表面,在图6中显不为内表面在上,夕卜表面在下。 After [0034] completion of the upper substrate treating step, the next substrate processing steps of: providing about 2, the lower base substrate having an inner surface and an opposite outer surface, in substantially FIG. 6 is not an inner surface of the upper, Xi Bu the lower surface. 内表面上已经具有已完成加工的信号处理IC21,在内表面上加工带有电气连接的一互连层23以及一多层结构的谐振器40 ;互连层23与该谐振器40和信号处理IC21之间电气连通,图6中信号处理IC21的焊盘22已经与互连层23按照设定好的图形连通。 The inner surface has been treated with IC21 signal processing has been completed, the inner surface of the interconnect layer 23, and a processing resonator electrically connected with a multilayer structure 40; interconnection layer 23 and the resonator 40 and the signal processing electrical communication between the IC21, IC21 signal processing in FIG. 6 has pads 22 and interconnection layer 23 communicates in accordance with predetermined pattern. 本实施例中,谐振器40为三层结构,按照竖直方向的分布包括上端的第一金属层43、中段的中间层42以及下端的第二金属层41 ;且第一金属层43与第二金属层41与互连层23具有电气连接。 In this embodiment, the resonator 40 is a three-layer structure according to the distribution of the vertical direction comprises a first upper metal layer 43, middle layer 42 and the second intermediate metal layer 41, the lower end; and the first metal layer 43 and the first a second metal interconnect layer 41 and the layer 23 has an electrical connection. 本实施例的第一、第二金属层均为Au,而中间层为A1N。 A first, a second metal layer according to the present embodiment are Au, the intermediate layer of A1N. 实现该互连层23、谐振器40的方法是: Implementing the interconnection layer 23, the resonator 40 is the method:

[0035] 首先米用光刻工艺,制作该第一金属层41、第一金属层41与该信号处理IC21在互连层23上的连线、第二金属层43电极与所述信号处理IC21在互连层23上连线的掩膜(未标不),然后蒸发或派射金层,剥离形成第一金属层41、第一金属层41与信号处理IC21在互连层23上的连线、第二金属层43与信号处理IC21在互连层23上的连线;沉积绝缘层薄膜,光刻图形化,暴露出信号处理IC21的焊盘22、中间层42以及第二金属层43与信号处理IC在互连层23上的连线的电接触窗口;然后溅射、沉积生成中间层42,光刻图形化中间层42 ;最后光刻,蒸发或溅射金层,剥离形成第二金属层43。 [0035] First, the signal electrode 43 of the second metal layer by photolithography processing rice to prepare the first metal layer 41, a first metal wiring layer 41 to the signal processing on the interconnect layer IC21 IC21 23 in the interconnection layer 23 connecting the mask (not labeled is not), then evaporated to send radio or gold layer, a peeling layer 41 is formed of the first metal, the first metal layer 41 and the signal processing IC21 attached to the interconnect layer 23 line, the second metal layer 43 to connect the signal processing IC21 on interconnect layer 23; an insulating layer deposited films, photolithographic patterning, exposing the signal processing IC21 pad 22, the intermediate layer 42 and the second metal layer 43 in connection with the signal processing IC electrical contact window 23 on the interconnect layer; then sputter deposited to generate intermediate layer 42, photolithographic patterning the intermediate layer 42; and finally photolithography, evaporated or sputtered gold layer formed on the release a second metal layer 43.

[0036] 当谐振器40成型后,再在该下基体2位于该谐振器40的位置处理一底孔24,使该谐振器40悬空,此形态谐振器40具有良好的抗干扰效果。 [0036] When the resonator 40 is formed, and then the substrate 2 is located at the position of the resonator 40 a blind hole 24 of the handle so that the suspended resonator 40, the resonator 40 has a good morphology of the interference effect.

[0037] 完成上述下基体处理步骤后,进入粘合步骤,请见图7:将已经成型的上基体I的底面与下基体2的内表面配合固定,本实施例的固定方式采用了图形化的粘接层50,该粘接层材料为金属铜锡,当然还可以为BCB、P1、铜、金、合金、金锡合金、铟等材质。 After [0037] completion of the lower base treatment step, into the bonding step, see Figure 7: a bottom surface which has been formed on the substrate I and the lower base the inner surface 2 of the fitting fixation, the present embodiment employs a graphical adhesive layer 50, the adhesive material is a layer of copper, tin, of course, may also be BCB, P1, copper, gold, alloys, gold-tin alloy and indium materials. 在上基体I的底面和下基体2的内表面二者之间具有互连层23,谐振器40位于凹坑44中;同时,导电体12与互连层23相连通,构成外部电路与信号处理IC21和谐振器40的电气连接;其中,凹坑44、微进孔17、、微出孔18形成完整的流体通道。 Interconnect layer having an inner surface 23 therebetween on the substrate 2 and the lower bottom surface I of the substrate, the resonator 40 is positioned in the pit 44; at the same time, the conductive layer 12 and the interconnect 23 are connected through, and the signal constituting the external circuit processing IC21 and the resonator 40 is electrically connected; wherein the pit 44, into the hole 17 ,, the micro hole 18 formed in a micro fluid channel complete. 当导电体12驳接外部电路时,即可监控此谐振器40的参数,将生物流体用流体泵70注入微进孔17,在凹坑44内浸过谐振器40后,谐振器40即可测得当前数据,通过互连层23与信号处理IC21,利用导电体12与外部控制电路完成通信。 When docked external circuit conductor 12, to monitor this parameter of the resonator 40, the micro-biological fluid injection hole 17 into the fluid pump 70, soaked in the resonator 40 after the pit 44, the resonator 40 can current data measured by the interconnection layer 23 and the signal processing IC 21, a conductive member 12 and the external control circuit to complete the communication. 可见,本方案实现了信号处理IC21和谐振器40整合,一方面实现了小型化,有助于微量生物样品检测;另一方面从工艺上使二者同步成型,生产效率高,体积小,特别适用于研制小型化生物检测设备。 Be seen, the present embodiment implementing a signal processing integrated IC21 40 and the resonator, the size of the one hand, facilitate the detection of trace biological sample; on the other hand so that the two synchronized from the molding process, high efficiency, small size, especially suitable for the development of miniaturized biological detection equipment.

[0038] 本实施例还具有其他一些特点: [0038] The present embodiment also has other features:

[0039] 下基体2实际为该信号处理IC21的衬底材料,如此,当信号处理IC21成型后,可以直接利用其衬底来制作本装置,省略了额外的下基体2材料,节省了材料和半导体工艺的时间成本。 Actual substrate material 2 IC21 for the signal processing of the substrate [0039] of, so, when the signal processing IC21 molding, a substrate which can be directly used to make the present apparatus, is omitted additional lower base material 2, material savings and time cost semiconductor processes.

[0040] 本实施例中,上基体I的通孔10、微进孔17、微出孔18、凹坑44和下基体2的底孔24可采用反应离子刻蚀法刻蚀处理,当然也可以用湿法刻蚀处理等手段进行置换。 [0040] embodiment, the through hole 10 of the base I, into the micro-holes 17, the micro-apertures 18, recesses 44 and the blind hole 24 of the base body 2 can be reactive ion etching etching process, of course, the present embodiment It can be replaced by means of a wet etching process.

[0041] 实施例二: [0041] Example II:

[0042] 如图8所示,本发明实施例二的示意图。 [0042] As shown in FIG 8, a schematic view of second embodiment of the present invention. 本实施例的上基体I为玻璃材料,下基体2亦为信号处理IC21的硅衬底。 On a substrate I of this embodiment is a glass material, the base body 2 is also a signal processing IC21 silicon substrate. 而上基体I的结构与实施例1类似;其凹坑44、微进孔17和微出孔18也相似。 I and the structure of the substrate similar to Example 1; the pit 44, into the micro-holes 17 and the micro-apertures 18 are also similar. 上基体I与下基体2之间采用了硅-玻璃阳极键合实现配合固定。 Employed between the substrate 2 and the lower substrate I of silicon - glass anodic bonding achieved with fixing. 不需额外的粘合层、材料等。 No additional adhesive layer material. 进一步简化了半导体的工艺。 Semiconductor processing is further simplified.

[0043] 实施例三: [0043] Example III:

[0044] 如图9所示,本发明实施例三的示意图。 [0044] As shown in FIG. 9, a schematic view according to a third embodiment of the present invention. 本实施例与实施例一的结构类似,上基体I为娃半导体材料,下基体2为信号处理IC21所在娃衬底。 This embodiment is similar to the embodiment of a configuration example, the substrate I is a baby semiconductor material, the substrate 2 where the signal processing IC21 baby substrate. 不同的是,在凹坑44内壁具有可受控加热的电阻丝层45,该电热层45与互连层23具有电气连通,因此,也可通过导电体12由外部电路控制。 The difference is that, with controlled heating resistance wire layer 45 on the inner wall of the pit 44, and the heating layer 45 in electrical communication with interconnect layer 23, thus, the conductive member 12 can also be controlled by an external circuit. 该电阻丝层45为Pt金属层的形态。 The resistance wire Pt layer 45 is in the form of metal layers. 因为在实际测量中,生物流体检测往往需要一定的温度氛围。 Because in actual measurement, detection of biological fluid often requires a certain temperature atmosphere. 通过设置电阻丝层45,能够可编程地实现凹坑44内温度变化(曲线),便于营造不同需求的测试环境。 By providing resistance wire layer 45 can be programmably implemented within the recesses 44 temperature (curve), easy to create a testing environment different needs. 该电热层45的实现是在上基体I处理步骤中,对凹坑44内壁进行加工,使之成型为图案化的形态,并且在粘合步骤中将该电热层45与互连层23连通。 The heating layer 45 is realized in the substrate processing step I, the pit inner wall 44 is processed so shaped to form patterned layer 45 and communicating with the electric interconnection layer 23 in the bonding step.

[0045] 以上所述,仅为本发明较佳实施例而已,故不能依此限定本发明实施的范围,即依本发明专利范围及说明书内容所作的等效变化与修饰,皆应仍属本发明涵盖的范围内。 [0045] The above are only preferred embodiments of the present invention, so it can not define the scope of the embodiments of the present invention, i.e., under this patent specification the content and scope of the invention is made such modifications and equivalent, are still present should be encompassed within the scope of the invention.

Claims (10)

1.一种半导体装置,其特征在于:包括: 一上基体,该上基体具有一顶面和该顶面相反方向的底面;该顶面与底面之间具有贯穿的通孔;该底面具有凹坑,每个凹坑通过至少一微进孔和一微出孔连通所述顶面与底面;该上基体的外表面覆盖一绝缘层;以及一下基体,具有一内表面和该内表面相反方向的外表面;内表面与所述上基体的底面相结合;所述内表面与底面之间具有一互连层;所述内表面一侧具有信号处理IC ;该信号处理IC的焊盘位于所述互连层; 其中,所述凹坑内具有多层结构的谐振器,该谐振器与所述互连层电连通,该凹坑与互连层之间密封构成一流道空间,该微进孔、流道空间和微出孔形成完整的流道通路;所述下基体在该谐振器的位置具有一的底孔;所述上基体的通孔内具有连通所述互连层的导电体,该导电体构成了所述信号处理IC和 1. A semiconductor device, comprising: comprising: a base body, the base body having a bottom surface opposite to a direction of the top surface and a top surface; having a through hole penetrating between the top and bottom surfaces; recess having the bottom surface pit, each pit by at least a micro-hole and into a micro the top and bottom surfaces of the bore in communication; the outer surface of a cover on the base insulating layer; and a lower base having an inner surface and an opposite inner surface direction of the an outer surface; a bottom surface of the inner surface of the upper substrate binding; having an interconnection layer between the inner surface and a bottom surface; a side surface of said inner has a signal processing IC; the pads are located in the signal processing IC said interconnection layer; wherein said pits having a multilayer structure of the resonator, the resonator in communication with the electrical interconnect layer, sealing the space between the flow channel constituting the recesses and the interconnect layer, the fine feed hole , micro-channel space and an aperture to form a complete runner passage; said lower base member having a bottom opening at a position of the resonator; said through hole on a substrate having a conductor interconnect layer of the communication, the conductive material constituting said signal processing IC, and 振器与外部连通的电气连接。 Vibration electrical connector communicating with the outside.
2.根据权利要求1所述一种半导体装置,其特征在于:所述谐振器为水平放置的三明治形态,在竖直方向上包括下端的第一金属层、中段的中间层以及上端的第二金属层;该谐振器的第一金属层与第二金属层与所述互连层具有电气连接。 2. A semiconductor device according to claim 1 claim, wherein: said resonator is a sandwich shape placed horizontally, the lower end comprising a first metal layer in the vertical direction, the upper end of the middle layer, and a second intermediate the metal layer; of the resonator of the first layer and the second metal layer and the metal interconnect layer having electrical connections.
3.根据权利要求1所述一种半导体装置,其特征在于:所述上基体和下基体之间具有一图形化的粘接层,该粘接层材料可以为BCB、P1、金、铜锡合金、金锡合金、铟。 3. A semiconductor device according to claim 1 claim, wherein: said upper having a patterned adhesive layer between the substrate and the lower substrate, the adhesive layer material may be BCB, P1, gold, copper-tin alloy, a gold-tin alloy, indium.
4.根据权利要求1所述一种半导体装置,其特征在于:所述上基体为玻璃材料,所述下基体主体为硅材料,该上基体的底面和下基体的内表面之间通过硅-玻璃阳极键合实现配合固定。 4. A semiconductor device as claimed in claim 1, wherein: said substrate is a glass material, the lower base body is a silicon material, a silicon between the bottom surface and the inner surface of the lower base body on the base body - glass anodic bonding with fixed achieved.
5.根据权利要求1所述一种半导体装置,其特征在于:所述凹坑内壁具有可受控加热的电阻丝层,该电阻丝层与所述互连层具有电气连通。 5. A semiconductor device according to the claim, characterized in that: said resistance wire pit inner wall has a controlled heating of the layer, the resistive layer and the wire in electrical communication with interconnect layer.
6.一种半导体装置的制造方法,`其特征在于:包括以下步骤: 上基体处理:在一上基体上加工出贯穿其顶面和底面的通孔、微进孔和微出孔;然后在其底面上加工凹坑,每个凹坑至少连通一个所述微进孔和一个微出孔;再在整个该上基体的外表面加工一层绝缘层;最后在所述通孔内加工导电体,该导电体延伸至所述顶面和底面; 下基体处理:提供一下基体,该下基体具有一内表面和其相反的外表面;在该内表面上已经具有已加工完成的信号处理1C,在该内表面上加工一互连层和一多层结构的谐振器;所述互连层与该谐振器与信号处理IC之间电气连通;再在该下基体位于该谐振器的位置处理一底孔,使该谐振器悬空; 粘合:将所述上基体的底面与该下基体的内表面配合固定,二者之间具有所述互连层,所述谐振器位于该凹坑中;同时,所述导电体与互连层 A method of manufacturing a semiconductor device, `characterized by: comprising the steps of: on a substrate processing: processing a through hole through which a top surface and a bottom surface on an upper substrate, fine feed holes and micro outlet hole; then machining the bottom surface pits, each pit communication with at least one inlet aperture and a micro-micro outlet hole; then in the entire outer surface of the processing substrate on the insulating layer; finishing the conductor within the through hole the electrical conductor extending to the top and bottom surfaces; lower base treatment: providing at the base, the lower base member having an inner surface and an opposite outer surface; has a signal having processed the processing performed 1C on the inner surface, processing an interconnection layer and the resonator of a multilayered structure on the inner surface; the interconnect layer in electrical communication between the resonator and the signal processing IC; reprocessing a substrate positioned in the lower position of the resonator the blind hole, so that the resonator is suspended; adhesive: on the bottom surface of the base body and the inner surface of the lower fixing fitting base body, having therebetween the interconnect layer, the resonator is located in the pit; Meanwhile, the conductor interconnect layer and 连通,构成外部电路与所述信号处理IC和谐振器的电气连接;其中,所述凹坑与所述互连层之间密封,以至于构成一流道空间,使所述微进孔、流道空间和微出孔形成完整流道通路。 Communicating, constituting an external circuit connected to the signal processing IC and the electrical resonators; wherein a seal between the recesses and the interconnect layer, so that the flow channel space constituting the inlet orifice of the micro flow path and the space micro flow passage holes to form a complete path.
7.根据权利要求6所述一种半导体装置的制造方法,其特征在于:所述通孔、微进孔、微出孔、凹坑和底孔可采用反应离子刻蚀或湿法刻蚀处理;所述绝缘层可用氧化工工艺或气相沉积的工艺加工。 6 7. A method of manufacturing a semiconductor device according to claim, characterized in that: said through-hole, into the micro-hole, a micro-hole, and bottomed pit a reactive ion etch or a wet etch process ; the insulating layer may be crafting oxidation process or a vapor deposition station.
8.根据权利要求6所述一种半导体装置的制造方法,其特征在于:所述下基体处理步骤中,所述谐振器为三层结构,竖直方向包括:下端的第一金属层、中段的中间层以及上端的第二金属层。 8. The method of manufacturing a semiconductor device according to claim 6, characterized in that: said step of processing the substrate, the resonator is a three-layer structure, a vertical direction comprising: a first metal layer of the lower, middle the upper end of the intermediate layer and the second metal layer.
9.根据权利要求8所述一种半导体装置的制造方法,其特征在于,所述中间层材料包括AlN、ZiO 或PZT。 8 9. A method of manufacturing a semiconductor device according to claim, wherein said intermediate layer materials include AlN, ZiO or PZT.
10.根据权利要求6至9中任一项所述一种半导体装置的制造方法,其特征在于:所述上基体处理步骤中,对所述凹坑内壁进行加工,使之成型为图案化的一电阻丝层,该电阻丝层与所述互连层电气连接。 10. A method of manufacturing a the semiconductor device according to any 6-9 claim, characterized in that: said processing step on a substrate, processing the inner wall of the pit, so that the molded pattern a layer of resistance wire, the resistance wire layer electrically connected to the interconnect layer.
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