CN103235037A - Semiconductor device and manufacturing method for same - Google Patents

Semiconductor device and manufacturing method for same Download PDF

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Publication number
CN103235037A
CN103235037A CN2013101143239A CN201310114323A CN103235037A CN 103235037 A CN103235037 A CN 103235037A CN 2013101143239 A CN2013101143239 A CN 2013101143239A CN 201310114323 A CN201310114323 A CN 201310114323A CN 103235037 A CN103235037 A CN 103235037A
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China
Prior art keywords
resonator
layer
matrix
hole
lower substrate
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CN2013101143239A
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Chinese (zh)
Inventor
马盛林
秦利锋
孙道恒
刘兴伟
黄裕茜
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Xiamen University
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Xiamen University
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Priority to CN2013101143239A priority Critical patent/CN103235037A/en
Publication of CN103235037A publication Critical patent/CN103235037A/en
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Abstract

The invention discloses a semiconductor device and a manufacturing method for the same. The invention is characterized in that the semiconductor device comprises an upper substrate and a lower substrate, a through hole, a micro inlet hole and a micro outlet hole are perforated in the upper substrate, concave pits are perforated in the bottom surface of the upper substrate, an insulating layer is arranged at the external surface of the whole upper substrate, a conductor is arranged in the through hole, the interior surface of the lower substrate has a signal processing IC, an interconnection layer and a multilayer-structured resonator are arranged on the interior surface and electrically communicated with the signal processing IC, a bottom hole is perforated in the lower substrate at a position where the resonator is located, the bottom surface of the upper substrate and the interior surface of the lower substrate are bonded together, the resonator is positioned in the concave pits in the bottom surface of the upper substrate, the conductor is communicated with the interconnection layer, and the concave pits, the micro inlet hole and the micro outlet hole form a complete flow channel, thereby obtaining the semiconductor device. According to the invention, the signal processing IC and resonator are integrated together, a micro channel is integrated on a chip, so a small size and a high integration level are realized and the semiconductor device can realize trace biological sample detection.

Description

The method for making of a kind of semiconductor device and this semiconductor device
Technical field
The present invention relates to a kind of semiconductor device that uses thin film bulk acoustic resonator and preparation method thereof.
Background technology
Thin film bulk acoustic resonator generally has the metal electrode/piezoelectric membrane/metal electrode resonator structure of similar sandwich structure, and metal electrode generally adopts gold thin film layer (Au), and piezoelectric membrane generally adopts zinc paste (ZnO), aluminium nitride (AlN) etc.; Its resonance frequency determines by the physical characteristics of the physical dimension of resonator structure, piezoelectric membrane, when the driving source frequency is consistent with the device resonance frequency, and device generation resonance.Thin film bulk acoustic resonator has advantages such as high resonance frequency, small size, obtains important application in the no communications field.Along with the demand of biosensor technique to high sensitivity, high integration, this class thin film bulk acoustic resonator also enjoys industry to pay attention in the applied research of bio-sensing detection range.Detect in the application mode at bio-sensing, usually need to set up the fluid passage of linking up between external environment and the resonator, biological substance to be detected passes through the fluid passage, arrive and be deposited on the resonator sensitive area, have an effect with resonator surface then, this will cause the change of resonance frequency, and resonance frequency changes will be obtained the formation signal by subsequent process circuit, so namely realize the biological detection based on resonator.At present, the disclosed biological sensing system based on wave resonator generally is arranged on resonator in the independent probe, be connected in the circuit that has treatment element etc. then, be characterized in that volume is big, level of integrated system is low, and need heavy dose of biological specimen to be measured in detecting.
Summary of the invention
Big for its volume of biological detection device of overcoming above-mentioned existing based thin film bulk acoustic wave resonator, level of integrated system is low, testing process consumes technical deficiencies such as the biological specimen amount is big, the present invention proposes a kind of semiconductor device and preparation method thereof, and its technical scheme is as follows:
As the preferred person of this programme, its semiconductor device can have the embodiment of following aspect:
As the method for making of semiconductor device of the present invention, its scheme is:
A kind of manufacture method of semiconductor device may further comprise the steps:
Last matrix is handled: matrix processes the through hole that runs through its end face and bottom surface, littlely advances hole and little portalling on one; Process pit in its bottom surface then, each pit is communicated with described little advance hole and little portalling at least; The outside surface of matrix arranges a layer insulating on whole being somebody's turn to do again; In described through hole electric conductor is set at last, this electric conductor extends to described end face and bottom surface;
Lower substrate is handled: a lower substrate is provided, and this lower substrate has the inside surface outside surface opposite with it; On this inside surface, had the signal processing IC of having finished processing, had an interconnection layer that is electrically connected, the resonator of a sandwich construction in this inside surface processing; Electrical communication between described interconnection layer and this resonator and the signal processing IC; Handle a bottom outlet in the position that this lower substrate is positioned at this resonator again, make this resonator unsettled;
Bonding: described bottom surface of going up matrix cooperated with the inside surface of this lower substrate fix, have described interconnection layer between the two, described resonator is arranged in this pit; Simultaneously, described electric conductor is connected with interconnection layer, constitutes being electrically connected of external circuit and described signal processing IC resonator; Wherein, described pit, littlely enter hole, little portalling and form complete runner path.
The preferred person of this method can have following embodiment:
In the preferred embodiment, described through hole, littlely enter the hole, littlely portal, pit and bottom outlet can adopt reactive ion etching or wet etching treatment; The technology of described insulation course available oxygen chemical process or vapour deposition is made.
In the preferred embodiment, in the described lower substrate treatment step, described resonator is three-decker, and vertical direction comprises: second metal level of the first metal layer of lower end, the middle layer in stage casing and upper end; At first adopt photoetching process, make the first metal layer, the first metal layer and this signal processing IC line, the second metal level electrode and the described signal processing IC on re-wiring layer of this lower end at the mask of the line of re-wiring layer, evaporation or sputter gold layer are then peeled off and are formed described the first metal layer, the first metal layer and signal processing IC at line, second metal level and the signal processing IC of the re-wiring layer line at re-wiring layer; Deposit piezoelectric membrane then, photoetching, graphical piezoelectric membrane generate described middle layer; Depositing insulating layer, photoetching exposes the window that electrically contacts of the pad of described signal processing IC, described middle layer and the second metal level electrode and the line of signal processing IC on re-wiring layer; Last photoetching, evaporation or sputter gold layer are peeled off and are formed described second metal level.
In the preferred embodiment, described intermediate layer material is AlN, ZiO, PZT.
In the preferred embodiment, described going up in the matrix treatment step processed described pit inwall, makes it to be shaped to a resistive heater layer of patterning, and this resistive heater thermosphere can be communicated with described interconnection layer.
The beneficial effect that the present invention program brings has:
1. this programme has been realized the integration of signal processing IC and thin film bulk acoustic resonator, and integrated fluid channel has realized miniaturization, high integration on sheet, can reduce the consumption to biological specimen to be measured in bio-sensing is used.
2. make the two synchronous forming from semiconductor technology, can use the ripe means of existing semiconductor technology in a large number, the production efficiency height.
3. with signal processing IC and resonator integration and making, make that biological sensing system possesses good programmability on the sheet, make its adaptability good, highly versatile.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing embodiment:
Fig. 1 is first synoptic diagram of matrix treatment step on the embodiment of the invention one;
Fig. 2 is second synoptic diagram of matrix treatment step on the embodiment of the invention one;
Fig. 3 is the 3rd synoptic diagram of matrix treatment step on the embodiment of the invention one;
Fig. 4 is the 4th synoptic diagram of matrix treatment step on the embodiment of the invention one;
Fig. 5 is the 5th synoptic diagram of matrix treatment step on the embodiment of the invention one;
Fig. 6 is the 6th synoptic diagram of the embodiment of the invention one lower substrate treatment step;
Fig. 7 is the 7th synoptic diagram of the embodiment of the invention one lower substrate treatment step;
Fig. 8 is the diagrammatic cross-section of the embodiment of the invention two;
Fig. 9 is the diagrammatic cross-section of the embodiment of the invention three.
Embodiment
Embodiment one:
As Fig. 1 to Fig. 7, the step of the embodiment of the invention one and product synoptic diagram.Showed the section signal that the present embodiment product is progressively realized from Fig. 1 to Fig. 7.
At first be to go up the matrix treatment step, comprised part illustrated in figures 1 and 2: matrix 1 processes the through hole 10 that runs through its end face and bottom surface, littlely enters hole 17 and littlely portal 18 on one, and method for processing can be reactive ion etching or wet etching treatment.The last matrix 1 of present embodiment is silicon materials, when through hole 10, little advance hole 17 and little 18 moulding of portalling after, processing place pit 40 on last matrix 1 its bottom surface then, present embodiment pits 40 has a plurality of, each pit 40 all be communicated with one little advance hole 17 and one little portal 18. see shown in Figure 1.
Finish above-mentioned steps, the outside surface of matrix 1 arranges a layer insulating 11 on whole being somebody's turn to do again, as shown in Figure 2, considers on the one hand and need connect by the various electrical equipment of moulding on last matrix 1, and upward matrix 1 is semiconductor material, also is the requirement for follow-up surface treatment on the other hand.Present embodiment insulation course 11 adopts earth silicon material to utilize the oxidation technology moulding, and reality also can adopt methods such as low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition.
After finishing above-mentioned steps, need in through hole 10, electric conductor be set.This flow process such as Fig. 3 are to shown in Figure 5.This flow process has been used secondary wafer 3.Secondary wafer 3 pre-sets the copper seed layer 32 of deposition, and then applies adhesives 31 on the bottom surface of last matrix 1, in order to the bonding bottom surface of matrix 1 and the copper seed layer 32 of secondary wafer 3 gone up.Remove and cover copper seed layer 32 at the adhesives 31 of the bottom of through hole 10, can use the way of reactive ion etching herein; As shown in Figure 3, through hole 10 copper seed layer 32 that can go directly.Then, through hole 10 is carried out copper electroplate, copper product is filled in the through hole 10, formed electric conductor 12, as shown in Figure 3.Remove secondary wafer 3 at last, and make the bottom surface of matrix 1 smooth smooth, can adopt methods such as chemistry, mechanical buffing, as shown in Figure 5, electric conductor 12 extends to end face and the bottom surface of matrix 1.
After finishing above-mentioned upward matrix treatment step, enter the lower substrate treatment step: a lower substrate 2 is provided, and this lower substrate has the inside surface outside surface opposite with it, is shown as inside surface last in Fig. 6, and outside surface is following.Had the signal processing IC 21 of having finished processing on the inside surface, had the interconnection layer 23 that is electrically connected and the resonator 40 of a sandwich construction in inside surface processing; Electrical communication between interconnection layer 23 and this resonator 40 and the signal processing IC 21, the pad 22 of signal processing IC 21 is communicated with according to the figure that configures with interconnection layer 23 among Fig. 6.In the present embodiment, resonator 40 is three-decker, comprises the first metal layer 43, the middle layer 42 in stage casing and second metal level 41 of lower end of upper end according to the distribution of vertical direction; And the first metal layer 43 and second metal level 41 have with interconnection layer 23 and are electrically connected.First, second metal level of present embodiment is Au, and the middle layer is AlN.The method that realizes this interconnection layer 23, resonator 40 is:
At first adopt photoetching process, make this first metal layer 41, the first metal layer 41 and the mask (do not indicate) of this signal processing IC 21 at the line on the interconnection layer 23, second metal level, 43 electrodes and described signal processing IC 21 line on interconnection layer 23, evaporation or sputter gold layer is peeled off and is formed the first metal layer 41, the first metal layer 41 and signal processing IC 21 at the line on the interconnection layer 23, second metal level 43 and the line of signal processing IC 21 on interconnection layer 23 then; The depositing insulating layer film, photolithography patterning exposes pad 22, middle layer 42 and second metal level 43 of signal processing IC 21 and the window that electrically contacts of the line of signal processing IC on interconnection layer 23; Sputter then, deposition generate middle layer 42, photolithography patterning middle layer 42; Last photoetching, evaporation or sputter gold layer are peeled off and are formed second metal level 43.
After resonator 40 moulding, handle a bottom outlet 24 in the position that this lower substrate 2 is positioned at this resonator 40 again, make this resonator 40 unsettled, this form resonator 40 has good anti-interference effect.
After finishing above-mentioned lower substrate treatment step, enter adhesion step, ask for an interview Fig. 7: cooperate the bottom surface of the last matrix 1 of moulding fixing with the inside surface of lower substrate 2, the fixed form of present embodiment has adopted patterned adhesive linkage 50, this adhesive linkage material is metallic copper tin, can also be materials such as BCB, PI, copper, gold, alloy, gold-tin alloy, indium certainly.Have interconnection layer 23 at the inside surface of the bottom surface of last matrix 1 and lower substrate 2 between the two, resonator 40 is arranged in pit 44; Simultaneously, electric conductor 12 is connected with interconnection layer 23, constitutes being electrically connected of external circuit and signal processing IC 21 resonator 40; Wherein, pit 44, little advance hole 17,, little portalling 18 form complete fluid passage.When electric conductor 12 is refuted when connecing external circuit, can monitor the parameter of this resonator 40, biofluid is injected little hole 17 of advancing with fluid pump 70, after in pit 44, soaking resonator 40, resonator 40 can record current data, by interconnection layer 23 and signal processing IC 21, utilize electric conductor 12 to finish with external control circuit and communicate by letter.As seen, this programme has been realized 40 integration of signal processing IC 21 resonator, has realized miniaturization on the one hand, helps micro-biology sample detection; Make the two synchronous forming from technology on the other hand, the production efficiency height, volume is little, is specially adapted to develop miniaturization biological detection equipment.
Present embodiment also has some other characteristics:
Lower substrate 2 reality are the backing material of this signal processing IC 21, so, after signal processing IC 21 moulding, can directly utilize its substrate to make this device, have omitted extra lower substrate 2 materials, have saved the time cost of material and semiconductor technology.
In the present embodiment, the through hole 10 of last matrix 1, littlely enter hole 17, littlely portal 18, the bottom outlet 24 of pit 44 and lower substrate 2 can adopt reactive ion etching method etching processing, can certainly replace with means such as wet etching treatment.
Embodiment two:
As shown in Figure 8, the synoptic diagram of the embodiment of the invention two.The last matrix 1 of present embodiment is glass material, and lower substrate 2 also is the silicon substrate of signal processing IC 21.And the structure that goes up matrix 1 is similar to Example 1; Its pit 44, little advance hole 17 with little portal 18 also similar.Having adopted silicon-glass anode linkage to realize cooperating between last matrix 1 and the lower substrate 2 fixes.Do not need extra bonding coat, material etc.Further simplified semi-conductive technology.
Embodiment three:
As shown in Figure 9, the synoptic diagram of the embodiment of the invention three.The structure of present embodiment and embodiment one is similar, and last matrix 1 is silicon semiconductor material, and lower substrate 2 is signal processing IC 21 place silicon substrates.Different is, but the resistance wire layer 45 that has controlled heat at pit 44 inwalls, and this electrothermal layer 45 has electrical communication with interconnection layer 23, therefore, also can be controlled by external circuit by electric conductor 12.This resistance wire layer 45 is the form of Pt metal level.Because in actual measurement, biofluid detects often needs certain temperature atmosphere.By resistance wire layer 45 is set, can realize temperature variation (curve) in the pit 44 able to programmely, be convenient to build the test environment of different demands.The realization of this electrothermal layer 45 is in last matrix 1 treatment step, and pit 44 inwalls are processed, and makes it to be shaped to the form of patterning, and in adhesion step this electrothermal layer 45 is communicated with interconnection layer 23.
The above, only for preferred embodiment of the present invention, so can not limit scope of the invention process according to this, i.e. the equivalence of doing according to claim of the present invention and description changes and modifies, and all should still belong in the scope that the present invention contains.

Claims (10)

1. semiconductor device is characterized in that: comprising:
Matrix on one, matrix has an end face and the rightabout bottom surface of this end face on this; Has the through hole that runs through between this end face and the bottom surface; This bottom surface has pit, and each pit littlely enters the hole and little portalling is communicated with described end face and bottom surface by at least one; The outside surface that should go up matrix covers an insulation course; And
One lower substrate has an inside surface and the rightabout outside surface of this inside surface; Inside surface combines with described bottom surface of going up matrix; Has an interconnection layer between described inside surface and the bottom surface; Described inside surface one side has signal processing IC; The pad of this signal processing IC is positioned at described interconnection layer;
Wherein, have the resonator of sandwich construction in the described pit, this resonator and described interconnection layer electric connection, sealing constitutes a runner space between this pit and the interconnection layer, and this is little to advance hole, flow channel space and little portalling and forms complete runner path; Described lower substrate has one bottom outlet in the position of this resonator; Have the electric conductor that is communicated with described interconnection layer in the through hole of described upward matrix, this electric conductor has constituted being electrically connected of described signal processing IC resonator and external communications.
2. according to the described a kind of semiconductor device of claim 1, it is characterized in that: described resonator is the sandwich form of horizontal positioned, and in the vertical direction comprises the first metal layer of lower end, the middle layer in stage casing and second metal level of upper end; The first metal layer of this resonator and second metal level and described interconnection layer have and are electrically connected.
3. according to the described a kind of semiconductor device of claim 1, it is characterized in that: described going up between matrix and the lower substrate has a patterned adhesive linkage, and this adhesive linkage material can be BCB, PI, gold, signal bronze, gold-tin alloy, indium.
4. according to the described a kind of semiconductor device of claim 1, it is characterized in that: described upward matrix is glass material, and described lower substrate main body is silicon materials, realizes cooperating fixing by silicon-glass anode linkage between the inside surface of the bottom surface of matrix and lower substrate on this.
5. according to the described a kind of semiconductor device of claim 1, it is characterized in that: but described pit inwall has the resistance wire layer of controlled heat, and this resistance wire layer and described interconnection layer have electrical communication.
6. the manufacture method of a semiconductor device is characterized in that: may further comprise the steps:
Last matrix is handled: matrix processes the through hole that runs through its end face and bottom surface, littlely advances hole and little portalling on one; Process pit in its bottom surface then, each pit is communicated with described little advance hole and little portalling at least; The outside surface of matrix is processed a layer insulating on whole being somebody's turn to do again; Process electric conductor at last in described through hole, this electric conductor extends to described end face and bottom surface;
Lower substrate is handled: a lower substrate is provided, and this lower substrate has the inside surface outside surface opposite with it; On this inside surface, had the signal processing IC that has machined, at the resonator of this inside surface processing one interconnection layer and a sandwich construction; Electrical communication between described interconnection layer and this resonator and the signal processing IC; Handle a bottom outlet in the position that this lower substrate is positioned at this resonator again, make this resonator unsettled;
Bonding: described bottom surface of going up matrix cooperated with the inside surface of this lower substrate fix, have described interconnection layer between the two, described resonator is arranged in this pit; Simultaneously, described electric conductor is connected with interconnection layer, constitutes being electrically connected of external circuit and described signal processing IC resonator; Wherein, seal between described pit and the described interconnection layer, to such an extent as to constitute a runner space, make and describedly littlely advance hole, flow channel space and little portalling and form complete runner path.
7. according to the manufacture method of the described a kind of semiconductor device of claim 6, it is characterized in that: described through hole, littlely enter the hole, littlely portal, pit and bottom outlet can adopt reactive ion etching or wet etching treatment; The processes of described insulation course available oxygen chemical process or vapour deposition.
8. according to the manufacture method of the described a kind of semiconductor device of claim 6, it is characterized in that: in the described lower substrate treatment step, described resonator is three-decker, and vertical direction comprises: second metal level of the first metal layer of lower end, the middle layer in stage casing and upper end.
9. the manufacture method of described a kind of semiconductor device according to Claim 8 is characterized in that described intermediate layer material comprises AlN, ZiO or PZT.
10. according to the manufacture method of each described a kind of semiconductor device in the claim 6 to 9, it is characterized in that: described going up in the matrix treatment step, described pit inwall is processed, made it to be shaped to a resistance wire layer of patterning, this resistance wire layer and described interconnection layer are electrically connected.
CN2013101143239A 2013-04-02 2013-04-02 Semiconductor device and manufacturing method for same Pending CN103235037A (en)

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Application publication date: 20130807