CN103219302A - Intermediate plate with punched hole - Google Patents

Intermediate plate with punched hole Download PDF

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Publication number
CN103219302A
CN103219302A CN2012100181084A CN201210018108A CN103219302A CN 103219302 A CN103219302 A CN 103219302A CN 2012100181084 A CN2012100181084 A CN 2012100181084A CN 201210018108 A CN201210018108 A CN 201210018108A CN 103219302 A CN103219302 A CN 103219302A
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CN
China
Prior art keywords
perforation
insulating barrier
conduction
face
intermediate plate
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100181084A
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Chinese (zh)
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CN103219302B (en
Inventor
陈明志
谢昌宏
胡迪群
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Unimicron Technology Suzhou Corp
Original Assignee
Unimicron Technology Suzhou Corp
Xinxing Electronics Co Ltd
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Application filed by Unimicron Technology Suzhou Corp, Xinxing Electronics Co Ltd filed Critical Unimicron Technology Suzhou Corp
Priority to CN201210018108.4A priority Critical patent/CN103219302B/en
Publication of CN103219302A publication Critical patent/CN103219302A/en
Application granted granted Critical
Publication of CN103219302B publication Critical patent/CN103219302B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Provided is an intermediate plate with a punched hole. The wall of the conductive punched hole is provided with a first insulating layer, a second insulating layer formed on the first insulating layer, and a metal layer formed on the second insulating layer, and the first insulating layer and the second insulating layer are made of different materials. Due to the fact that the two insulating layers made of the different materials are formed on the wall of the conductive punched hole, the intermediate plate with the punched hole has better anti-creeping and high-voltage-resistant characteristics.

Description

The perforation intermediate plate
Technical field
The relevant a kind of intermediate plate of the present invention refers to a kind of intermediate plate with perforation especially.
Background technology
Since IBM Corporation introduces Flip-Chip Using (Flip Chip Package) technology in early days in nineteen sixty, engage (Wire Bond) technology than routing, flip chip technology (fct) is characterised in that electric connection between semiconductor chip and substrate is by solder bump but not general gold thread.And the advantage of this kind flip chip technology (fct) is that this technology can promote packaging density to reduce the package assembling size, and simultaneously, this kind flip chip technology (fct) need not use the long gold thread of length, so can promote electrical performance.In view of this, industry is used high temperature scolding tin on ceramic substrate, and (Control-Collapse Chip Connection C4), has for many years the chip interconnection technique of promptly so-called control disintegration.In recent years, because high density, at a high speed and the increase of semiconductor subassembly demand cheaply, simultaneously in response to the diminishing trend of the volume of electronic product, flip-chip assembly (for example is arranged at cheaply organic circuit board, printed circuit board (PCB) or substrate), and with epoxy resin primer (Underfill resin) be filled in chip below with between the framework that reduces silicon and organic circuit board because of the thermal stress that thermal dilation difference was produced, presented volatile growth.
In existing flip chip technology (fct), dispose electronic pads (electronic pad) on the surface of semiconductor integrated circuit (IC) chip, and base plate for packaging also has corresponding flip-chip weld pad, solder bump or other conduction soldering tin material can suitably be set between this chip and base plate for packaging, making this chip is to be arranged on this base plate for packaging to act on ventricumbent pattern, wherein, this solder bump or conductive adhesive material provide electrical I/O (I/O) and the mechanical connection between this chip and base plate for packaging.Follow-up when this base plate for packaging and semiconductor chip etc. are carried out packaging technology, for providing this base plate for packaging to be able to and extraneous electronic installation (as circuit board) electrically connects, must plant a plurality of soldered balls in this base plate for packaging bottom surface usually.
Along with electronic product more is tending towards demand compact and that function constantly promotes, the wiring density of this semiconductor chip is more and more high, and with nano-scale office, thereby the spacing between each flip-chip weld pad of this base plate for packaging is littler.
The spacing of the flip-chip weld pad of base plate for packaging is with micron-scale office at present, and can't effectively be contracted to size to the spacing of each electronic pads that should chip, though cause having the semiconductor chip of elevated track density, the base plate for packaging that can cooperate is not but arranged, so that can't effectively produce electronic product.
For overcoming above-mentioned problem, so between this base plate for packaging 9 and semiconductor chip 8, set up a silicon intermediate plate (Silicon interposer) 1, shown in Figure 1A, this silicon intermediate plate 1 has silicon body 10, be arranged in silicon perforation (the Through-silicon via in this silicon body 10, TSV) 14 and be located at bore a hole circuit rerouting layer (Redistributionlayer on 14 tops of this silicon body 10 and silicon, RDL) 13, the bottom that makes this silicon perforation 14 is by conductive projection 92 electrical flip-chip weld pads 90 in conjunction with the bigger base plate for packaging 9 of spacing, and the superiors' circuit of this circuit rerouting layer 13 has electric connection pad, with by solder bump 81 electrical electronic padses 80, form packing colloid 7 again in conjunction with the less semiconductor chip 8 of spacing.
Whereby, make this base plate for packaging 9 can be, and reach the purpose of the semiconductor chip 8 of integrating high wiring density in conjunction with semiconductor chip 8 with high wiring density electronic pads 80.So by this silicon intermediate plate 1, not only can solve the problem of the base plate for packaging that shortage can cooperate, and can not change IC industry supply chain (supply chain) and infrastructure device (infrastructure) originally.
In the making of silicon perforation 14, can form insulating barrier (isolation layer) 11 on the hole wall of this silicon perforation 14 at present, shown in Figure 1B, its material is generally used SiN X, the SiO that produces of polymer, high temperature furnace or chemical vapor deposition (CVD) 2
But, make in the technology of this insulating barrier 11, equal some disappearances, for example: it is too high that the technology of chemical vapour deposition (CVD) has the possibility of electric leakage, polymer to have its temperature of technology of problem, high temperature furnace of dielectric, and the SiO that produces 2Really up to the mark or the insulating barrier 11 of material is single kind of material of tool only, has the problem of reliability and insulating properties.
Therefore, how to overcome above-mentioned variety of problems of the prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, main purpose of the present invention is to provide a kind of perforation intermediate plate, by the insulating barrier that forms two kinds of materials on the hole wall of conduction perforation, to have better anticreep and high voltage withstanding characteristic.
Perforation intermediate plate provided by the present invention has first insulating barrier on the hole wall of its conduction perforation, is formed at second insulating barrier on this first insulating barrier and is formed at metal material on this second insulating barrier, and the material of this first and second insulating barrier is inequality.
In the aforesaid perforation intermediate plate, this first and second insulating barrier may extend on the substrate of perforation intermediate plate.Perhaps, can form the first electrical isolation layer on this substrate.
As from the foregoing, perforation intermediate plate of the present invention is by form the insulating barrier of two kinds of materials on the hole wall of conduction perforation, than the single material insulating barrier of prior art, have better anticreep and high voltage withstanding characteristic, and can improve insulating properties and promote the electrically reliability of conduction.
Description of drawings
Figure 1A is the encapsulation cross-sectional schematic of existing base plate for packaging, semiconductor chip and silicon intermediate plate;
Figure 1B amplifies cross-sectional schematic for the part of existing silicon intermediate plate; And
Fig. 2 A to Fig. 2 H is the bore a hole cross-sectional schematic of first embodiment of method for making of intermediate plate of the present invention; Wherein, Fig. 2 A ' and Fig. 2 D ' are respectively the vertical view of Fig. 2 A and Fig. 2 D;
Fig. 3 A to Fig. 3 C is the bore a hole cross-sectional schematic of second embodiment of method for making of intermediate plate of the present invention;
Fig. 4 A to Fig. 4 C is the bore a hole cross-sectional schematic of the 3rd embodiment of method for making of intermediate plate of the present invention;
Fig. 5 A to Fig. 5 H is the bore a hole cross-sectional schematic of the 4th embodiment of method for making of intermediate plate of the present invention; Wherein, Fig. 5 B ' is the vertical view of Fig. 5 B;
Fig. 6 A to Fig. 6 C is the bore a hole cross-sectional schematic of the 5th embodiment of method for making of intermediate plate of the present invention; And
Fig. 7 A to Fig. 7 C is the bore a hole cross-sectional schematic of the 6th embodiment of method for making of intermediate plate of the present invention.
The primary clustering symbol description
1 silicon intermediate plate
10 silicon bodies
11 insulating barriers
13 circuit rerouting layers
The perforation of 14 silicon
2,2 ', 2 ", 3,3 ', 3 " perforation intermediate plate
20,30 substrates
20a, the 30a first surface
20b, 20b ', 30b, 30b ' second surface
200,300 looping pits
200a, 201a, 300a, 301a bottom
201,301 perforation
21,31 first insulating barriers
22,32 second insulating barriers
220,360 perforates
23a, 33a first line layer
23b, 33b second line layer
24,24 ', 24 ", 34,34 ', 34 " conduction perforation
24a, 24a ", 34a, 34a " and first end face
24b, 24b ', 24b ", 34b, 34b ', 34b " and second end face
240,340 metal materials
25a, 35a first protective layer
25b, 35b second protective layer
250a, 350a first perforate
250b, 350b second perforate
26 electrical isolation layers
The 36a first electrical isolation layer
The 36b second electrical isolation layer
7 packing colloids
8 semiconductor chips
80 electronic padses
81 solder bumps
9 base plate for packaging
90 flip-chip weld pads
92 conductive projections.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
Notice, the appended graphic structure that illustrates of this specification, ratio, size etc., all only in order to cooperate the content that specification disclosed, understanding and reading for those skilled in the art, be not in order to limit the enforceable qualifications of the present invention, so technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not influencing under effect that the present invention can produce and the purpose that can reach, all should still drop on disclosed technology contents and get in the scope that can contain.Simultaneously, quoted in this specification as " on " reach terms such as " one ", also understanding only for ease of narration, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment under no essence change technology contents, also ought be considered as the enforceable category of the present invention.
See also Fig. 2 A to Fig. 2 H, it is the cross-sectional schematic of first embodiment of the method for making of perforation intermediate plate 2 of the present invention.
Shown in Fig. 2 A and Fig. 2 A ', provide a substrate 20 with opposite first 20a and second surface 20b.Then, go up formation looping pit 200 in the first surface 20a of this substrate 20, this looping pit 200 has bottom 200a.
In present embodiment, the material that forms this substrate 20 can be glass, silicon wafer, metal, Polymer.In addition, the profile of this looping pit 200 can be circle or polygon, and there is no particular restriction.
Shown in Fig. 2 B, on the hole wall of the first surface 20a of this substrate 20 and looping pit 200, form one first insulating barrier 21.Then, on first insulating barrier 21 on the first surface 20a of this substrate 20, form one second insulating barrier 22, and this second insulating barrier 22 also fills up this looping pit 200.
In present embodiment, the material of described first and second insulating barrier 21,22 is inequality, and this first insulating barrier 21 is the hard material, and this second insulating barrier 22 is that this first insulating barrier 21 is soft material relatively.The material of this first and second insulating barrier 21,22 can be organic material or inorganic material again, as epoxy resin, SiN X, SiO 2Deng.
Shown in Fig. 2 C, on this second insulating barrier 22, form perforate 220 that should looping pit 200, remove first insulating barrier 21 in this perforate 220 again, to expose the substrate 20 first surface 20a that are positioned at these looping pit 200 rings.
Shown in Fig. 2 D and Fig. 2 D ', remove substrate 20 materials in this perforate 220, form the perforation 201 that is communicated with this substrate 20 first surface 20a to make this looping pit 200, this perforation 201 has bottom 201a, and this first and second insulating barrier 21,22 is as the hole wall of this perforation 201.
Shown in Fig. 2 E, on second insulating barrier 22 on the first surface 20a of this substrate 20, form one first line layer 23a, and in this perforation 201, form a metal material 240, to form conduction perforation 24.Then, go up formation one first protective layer 25a in this second insulating barrier 22 with this first line layer 23a.
In present embodiment, be to form this first line layer 23a and conduction perforation 24 with plating mode, just form crystal seed layer (seed layer on second insulating barrier 22 prior to second insulating barrier 22 on the first surface 20a of this substrate 20 and these 201 hole walls of boring a hole, figure does not show), again with this crystal seed layer as the conducting path of current, on this crystal seed layer, form this metal material 240, to form this first line layer 23a and conduction perforation 24.
In addition, this conduction perforation 24 have to the first end face 24a that should first surface 20a with to the second end face 24b that should second surface 20b, and the first end face 24a of this conduction perforation 24 electrically connects this first line layer 23a, and has this metal material 240 on the bottom 201a of this perforation 201.
Simultaneously, the material of this conduction perforation 24 comprises this metal material 240, first and second insulating barrier 21,22.In addition, this conduction perforation 24 is a hollow form, makes this first protective layer 25a be filled in this conduction perforation 24.
Shown in Fig. 2 F, remove the part material of second surface 20b of this substrate 20 and the metal material 240 of these 201 bottom 201a that bore a hole, flush with the second end face 24b of this conduction perforation 24 with the second surface 20b ' that makes this substrate 20, and the second end face 24b of this conduction perforation 24 is exposed.
Shown in Fig. 2 G, go up formation one electrical isolation layer 26 in the second surface 20b ' of this substrate 20, to cover first and second insulating barrier 21,22 in this conduction perforation 24, make this electrical isolation layer 26 expose the part second end face 24b of this conduction perforation 24.
Shown in Fig. 2 H, on this electrical isolation layer 26, form one second line layer 23b, and this second line layer 23b electrically connects the second end face 24b of this conduction perforation 24.At last; go up formation one second protective layer 25b in this electrical isolation layer 26 with this second line layer 23b; and in this first and second protective layer 25a; a plurality of first and second perforate of the last formation of 25b 250a; 250b; to make this first and second line layer 23a, the part surface of 23b exposes to those first and second perforates 250a, 250b.
See also Fig. 3 A to Fig. 3 C, it is the cross-sectional schematic of second embodiment of the method for making of perforation intermediate plate 2 ' of the present invention.The difference of the present embodiment and first embodiment only is to keep the metal material 240 of these 201 bottom 201a that bore a hole, and other related process is all identical, so same section does not repeat them here.
As shown in Figure 3A, it is the technology of Fig. 2 E, forms one first line layer 23a on second insulating barrier 22 on the first surface 20a of this substrate 20, and forms the conduction perforation 24 ' of hollow form, and the bottom 201a of this perforation 201 has this metal material 240.Then, go up formation one first protective layer 25a with this first line layer 23a, and this first protective layer 25a is filled in this conduction perforation 24 ' in this second insulating barrier 22.
Shown in Fig. 3 B, remove the part material of second surface 20b of this substrate 20 and first insulating barrier 21 of these 201 bottom 201a that bore a hole, and keep the metal material 240 of this 201 bottom 201a that bore a hole, the second end face 24b ' of this conduction perforation 24 ' is exposed, and make the middle vacancy of the second end face 24b ' of this conduction perforation 24 ' of these metal material 240 cappings.
Shown in Fig. 3 C, go up formation one electrical isolation layer 26 in the second surface 20b ' of this substrate 20, and on this electrical isolation layer 26, form the second line layer 23b of the second end face 24b ' of this conduction perforation 24 ' of an electric connection.At last, go up formation one second protective layer 25b in this electrical isolation layer 26 with this second line layer 23b.
See also Fig. 4 A to Fig. 4 C, it is a perforation intermediate plate 2 of the present invention " the cross-sectional schematic of the 3rd embodiment of method for making.The difference of the present embodiment and first embodiment only is conduction perforation 24 " structure, other related process is all identical, so same section does not repeat them here.
Shown in Fig. 4 A, it is in the technology of Fig. 2 E, on this second insulating barrier 22, form one first line layer 23a, and in this perforation 201, fill up this metal material 240 to form conduction perforation 24 ", make this first insulating barrier 21, second insulating barrier 22 and metal material 240 fill up this conduction perforation 24 ".
Shown in Fig. 4 B, remove the part material of the second surface 20b of this substrate 20, make this conduction perforation 24 " the second end face 24b " flush with the second surface 20b ' of this substrate 20.
Shown in Fig. 4 C, go up in the second surface 20b ' of this substrate 20 and to form an electrical isolation layer 26, and on this electrical isolation layer 26, form one and electrically connect this conduction perforation 24 " the second end face 24b " the second line layer 23b.At last, go up formation one second protective layer 25b in this electrical isolation layer 26 with this second line layer 23b.
Therefore; the invention provides a kind of perforation intermediate plate 2; 2 '; 2 " it comprises: the substrate 20 with opposite first 20a and second surface 20b '; be located at the conduction perforation 24 in this substrate 20; 24 ', 24 "; be located at the first line layer 23a on the first surface 20a of this substrate 20; be located at the first surface 20a of this substrate 20 and the first protective layer 25a on this first line layer 23a; be located at the electrical isolation layer 26 on the second surface 20b ' of this substrate 20; be located at the second line layer 23b on this electrical isolation layer 26; and be located at the second protective layer 25b on this electrical isolation layer 26 and the second line layer 23b.
Described substrate 20 is a silicon substrate, it has by this looping pit 200 and perforation 201 perforation structures that constitute, and have one first insulating barrier 21 and one second insulating barrier 22 that is formed on this first insulating barrier 21 on this first surface 20a, wherein, this first and second insulating barrier 21,22 material is inequality, be the hard material as this first insulating barrier 21, and this second insulating barrier 22 is soft material.
Described conduction perforation 24,24 ', 24 " be formed in this perforation structure and be communicated with first and second surperficial 20a of this substrate 20; 20b '; and have; 24a the first end face 24a that should first surface 20a " with to the second end face 24b that should second surface 20b ', 24b ', 24b "; this first and second insulating barrier 21,22 also extends in this perforation structure with as this conduction perforation 24,24 ' again; 24 " hole wall structure, make a metal material 240 be located on second insulating barrier 22 in this perforation structure.
The described first line layer 23a is located on second insulating barrier 22 on the first surface 20a of this substrate 20, and electrically connects this conduction perforation 24,24 ', 24 " the first end face 24a, 24a ".
The described first protective layer 25a also is located on second insulating barrier 22 on the first surface 20a of this substrate 20.
Described electrical isolation layer 26 covers this conduction perforation 24,24 ', 24 " in first and second insulating barrier 21,22, bore a hole 24,24 ', 24 to expose this conduction " the part second end face 24b, 24b ', 24b ".
The described second line layer 23b electrically connects this conduction perforation 24,24 ', 24 " the second end face 24b, 24b ', 24b ".
In addition, in first and second embodiment, described conduction perforation 24,24 ' is a hollow form, and this first protective layer 25a is filled in this conduction perforation 24,24 '.For example, in first embodiment, this first protective layer 25a is communicated with the first end face 24a and the second end face 24b of this conduction perforation 24, and in second embodiment, the middle vacancy of the second end face 24b ' of conduction perforation 24 ' is somebody's turn to do in these metal material 240 cappings.
In addition, in the 3rd embodiment, this first insulating barrier 21, second insulating barrier 22 and metal material 240 fill up this conduction perforation 24 ".
See also Fig. 5 A to Fig. 5 H, it is the cross-sectional schematic of the 4th embodiment of the method for making of perforation intermediate plate 3 of the present invention.The difference of the present embodiment and first embodiment only is the structure on the first surface 30a of substrate 30, and other related process is all identical, so same section does not repeat them here.
Shown in Fig. 5 A, structure just like Fig. 2 B is provided, promptly have and form looping pit 300 on the substrate 30 of opposite first 30a and second surface 30b in one, this looping pit 300 has bottom 300a, and form one first insulating barrier 31 on the first surface 30a of this substrate 30 and the hole wall of this looping pit 300, and on this first insulating barrier 31 with in this looping pit 300, form one second insulating barrier 32.
Shown in Fig. 5 B and Fig. 5 B ', remove first insulating barrier 31 and second insulating barrier 32 on the first surface 30a of this substrate 30, only keep first insulating barrier 31 and second insulating barrier 32 in this looping pit 300.
Shown in Fig. 5 C, go up in the first surface 30a of this substrate 30 and to form one first electrical isolation layer 36a, and this first electrical isolation layer 36a has to perforate 360 that should looping pit 300, with the 30 first surface 30a of the substrate in the ring that exposes this looping pit 300.
Shown in Fig. 5 D, remove substrate 30 materials in this perforate 360, form the perforation 301 that is communicated with this substrate 30 first surface 30a to make this looping pit 300, this perforation 301 has bottom 301a, and this first and second insulating barrier 31,32 is as the hole wall of this perforation 301.
Shown in Fig. 5 E, upward form one first line layer 33a in this first electrical isolation layer 36a, and plated metal material 340 bores a hole 34 to form conduction in this perforation 301.Then, go up formation one first protective layer 35a in this first electrical isolation layer 36a and this first line layer 33a.
In present embodiment, this conduction perforation 34 have to the first end face 34a that should first surface 30a with to the second end face 34b that should second surface 30b, and the first end face 34a of this conduction perforation 34 electrically connects this first line layer 33a, and the bottom 301a of this perforation 301 has this metal material 340.
In addition, this conduction perforation 34 includes this metal material 340, first and second insulating barrier 31,32, and should conduction perforation 34 be hollow form, makes this first protective layer 35a be filled in this conduction perforation 34.
Shown in Fig. 5 F, remove the part material of second surface 30b of this substrate 30 and the metal material 340 of these 301 bottom 301a that bore a hole, make the second surface 30b ' of this substrate 30 flush, to expose the second end face 34b of this conduction perforation 34 with the second end face 34b of this conduction perforation 34.
Shown in Fig. 5 G, go up formation one second electrical isolation layer 36b in the second surface 30b ' of this substrate 30, and cover first and second insulating barrier 31,32 of this conduction perforation 34, make this second electrical isolation layer 36b expose the part second end face 34b of this conduction perforation 34.
Shown in Fig. 5 H, go up formation one second line layer 33b in this second electrical isolation layer 36b, and this second line layer 33b electrically connects the second end face 34b of this conduction perforation 34.At last; go up formation one second protective layer 35b in this second electrical isolation layer 36b and this second line layer 33b; and in this first and second protective layer 35a; a plurality of first and second perforate of the last formation of 35b 350a; 350b; to make this first and second line layer 33a, the part surface of 33b exposes to those first and second perforates 350a, 350b.
See also Fig. 6 A to Fig. 6 C, be the cross-sectional schematic of the 5th embodiment of the method for making of perforation intermediate plate 3 ' of the present invention.The difference of present embodiment and the 4th embodiment only is to keep the metal material 340 of these 301 bottom 301a that bore a hole, and other related process is all identical, so same section does not repeat them here.
As shown in Figure 6A, it is the technology of Fig. 5 E, goes up in this first electrical isolation layer 36a and forms one first line layer 33a, and form the conduction perforation 34 ' of this hollow form, has this metal material 340 on the bottom 301a of this perforation 301.Then, go up formation one first protective layer 35a, and this first protective layer 35a is filled in this conduction perforation 34 ' in this first electrical isolation layer 36a and the first line layer 33a.
Shown in Fig. 6 B, remove the part material of second surface 30b of this substrate 30 and first insulating barrier 31 of these 301 bottom 301a that bore a hole, and keep the metal material 340 of this 301 bottom 301a that bore a hole, the second end face 34b ' of this conduction perforation 34 ' is exposed, and make the middle vacancy of the second end face 34b ' of this conduction perforation 34 ' of these metal material 340 cappings.
Shown in Fig. 6 C, go up in the second surface 30b ' of this substrate 30 and to form one second electrical isolation layer 36b, and go up in this second electrical isolation layer 36b and to form second a line layer 33b who electrically connects the second end face 34b ' of this conduction perforation 34 '.At last, go up formation one second protective layer 35b in this second electrical isolation layer 36b and the second line layer 33b.
See also Fig. 7 A to Fig. 7 C, it is a perforation intermediate plate 3 of the present invention " the cross-sectional schematic of the 6th embodiment of method for making.The difference of present embodiment and the 4th embodiment only is conduction perforation 34 " structure, other related process is all identical, so same section does not repeat them here.
Shown in Fig. 7 A, it is in the technology of Fig. 5 E, go up formation one first line layer 33a in this first electrical isolation layer 36a, and in this perforation 301, fill up this metal material 340 to form conduction perforation 34 ", make this first insulating barrier 31, second insulating barrier 32 and metal material 340 fill up this conduction perforation 34 ".
Shown in Fig. 7 B, remove the part material of second surface 30b of this substrate 30 and first insulating barrier 31 of these 301 bottom 301a that bore a hole, make this conduction perforation 34 " the second end face 34b " flush with the second surface 30b ' of this substrate 30.
Shown in Fig. 7 C, go up in the second surface 30b ' of this substrate 30 and to form one second electrical isolation layer 36b, and go up in this second electrical isolation layer 36b form one and electrically connect this conduction perforation 34 " the second end face 34b " the second line layer 33b.At last, go up formation one second protective layer 35b in this second electrical isolation layer 36b and the second line layer 33b.
Therefore; the invention provides another kind of perforation intermediate plate 3; 3 '; 3 " it comprises: the substrate 30 with opposite first 30a and second surface 30b '; be located at the conduction perforation 34 in this substrate 30; 34 ', 34 "; be located at the first electrical isolation layer 36a on the first surface 30a of this substrate 30; be located at the first line layer 33a on this first electrical isolation layer 36a; be located at the first protective layer 35a on this first electrical isolation layer 36a and the first line layer 33a; be located at the second electrical isolation layer 36b on the second surface 30b ' of this substrate 30; be located at the second line layer 33b on this second electrical isolation layer 36b; and be located at the second protective layer 35b on this second electrical isolation layer 36b and the second line layer 33b.
Described substrate 30 is a silicon substrate, and has by this looping pit 300 and perforation 301 perforation structures that constitute.
Described conduction perforation 34,34 ', 34 " be formed in this perforation structure and be communicated with first and second surperficial 30a of this substrate 30; 30b '; and have to the first end face 34a that should first surface 30a 34a " with to the second end face 34b that should second surface 30b ', 34b ', 34b ", and have one first insulating barrier 31, one second insulating barrier 32 and a metal material 340 on the hole wall of this perforation structure in regular turn.Wherein, the material of this first and second insulating barrier 31,32 is also inequality, be the hard material as this first insulating barrier 31, and this second insulating barrier 32 is soft material.
The described first electrical isolation layer 36a covers this conduction perforation 34,34 ', 34 " first and second insulating barrier 31,32, bore a hole 34,34 ', 34 to expose this conduction " the first end face 34a, 34a ".
The described first line layer 33a electrically connects this conduction perforation 34,34 ', 34 " the first end face 34a, 34a ".
The described second electrical isolation layer 36b covers this conduction perforation 34,34 ', 34 " first and second insulating barrier 31,32, bore a hole 34,34 ', 34 to expose this conduction " the part second end face 34b, 34b ', 34b ".
The described second line layer 33b electrically connects this conduction perforation 34,34 ', 34 " the second end face 34b, 34b ', 34b ".
In addition, in the 4th and the 5th embodiment, described conduction perforation 34,34 ' is a hollow form, and this first protective layer 35a is filled in this conduction perforation 34,34 '.For example: in the 4th embodiment, this first protective layer 35a is communicated with the first end face 34a and the second end face 34b of this conduction perforation 34, and in the 5th embodiment, the middle vacancy of the second end face 34b ' of conduction perforation 34 ' is somebody's turn to do in these metal material 340 cappings.
In addition, in the 6th embodiment, this first insulating barrier 31, second insulating barrier 32 and metal material 340 fill up this conduction perforation 34 ".
In sum, perforation intermediate plate of the present invention mainly has two kinds of insulation materials on the hole wall of this conduction perforation, having better anticreep and high voltage withstanding characteristic, and improves insulating properties and promotes electrical reliability of conducting.
In addition, perforation intermediate plate of the present invention is manufacturing technology cheaply, the volume production that is beneficial to.
The foregoing description is only in order to illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So the scope of the present invention, should be listed as claims.

Claims (14)

  1. One kind the perforation intermediate plate, it comprises:
    Substrate, it has opposite first and second surface, and is communicated with the perforation structure of this first surface and second surface, and have first insulating barrier and second insulating barrier that is formed on this first insulating barrier on the first surface of this substrate, the material of this first and second insulating barrier is inequality again;
    The conduction perforation, it is formed in this perforation structure, this first and second insulating barrier also extends in this perforation structure with the hole wall structure as this conduction perforation, and this conduction perforation also has to first end face that should first surface and to second end face that should second surface and be located at metal material on second insulating barrier in this perforation structure;
    First line layer, it is located on second insulating barrier on the first surface of this substrate, and electrically connects first end face of this conduction perforation;
    First protective layer, it is located on second insulating barrier and this first line layer on the first surface of this substrate;
    The electrical isolation layer, it is located on the second surface of this substrate, and exposes second end face of this conduction perforation;
    Second line layer, it is located on this electrical isolation layer, and electrically connects second end face of this conduction perforation; And
    Second protective layer, it is located on this electrical isolation layer and this second line layer.
  2. 2. perforation intermediate plate according to claim 1 is characterized in that, this electrical isolation layer also covers first and second insulating barrier on this conduction perforation second end face.
  3. 3. perforation intermediate plate according to claim 1 is characterized in that, this first protective layer also is filled in this conduction perforation.
  4. 4. perforation intermediate plate according to claim 3 is characterized in that, this first protective layer is communicated with first end face and second end face of this conduction perforation.
  5. 5. perforation intermediate plate according to claim 3 is characterized in that, second end face of conduction perforation is somebody's turn to do in this metal material capping.
  6. 6. perforation intermediate plate according to claim 1 is characterized in that, this metal material fills up this conduction perforation, and the material of this metal material is a copper.
  7. 7. perforation intermediate plate according to claim 1 is characterized in that, this first insulating barrier is the hard material, and this second insulating barrier this first insulating barrier relatively is soft material.
  8. One kind the perforation intermediate plate, it comprises:
    Substrate, it has opposite first and second surface, and is communicated with the perforation structure of this first surface and second surface;
    The conduction perforation, it is formed in this perforation structure, the perforation of this conduction have to first end face that should first surface with to second end face that should second surface, and have first insulating barrier on the hole wall of this perforation structure, be formed at second insulating barrier on this first insulating barrier and be formed at metal material on this second insulating barrier, the material of this first and second insulating barrier is inequality again;
    The first electrical isolation layer, it is located on the first surface of this substrate, and exposes first end face of this conduction perforation;
    First line layer, it is located on this first electrical isolation layer, and electrically connects first end face of this conduction perforation;
    First protective layer, it is located on this first electrical isolation layer and this first line layer;
    The second electrical isolation layer, it is located on the second surface of this substrate, and exposes second end face of this conduction perforation;
    Second line layer, it is located on this second electrical isolation layer, and electrically connects second end face of this conduction perforation; And
    Second protective layer, it is located on this second electrical isolation layer and this second line layer.
  9. 9. perforation intermediate plate according to claim 8 is characterized in that, this first and second electrical isolation layer covers first and second insulating barrier on this first and second end face of conduction perforation respectively.
  10. 10. perforation intermediate plate according to claim 8 is characterized in that, this first protective layer also is filled in this conduction perforation.
  11. 11. perforation intermediate plate according to claim 10 is characterized in that, this first protective layer is communicated with first end face and second end face of this conduction perforation.
  12. 12. perforation intermediate plate according to claim 11 is characterized in that, second end face of conduction perforation is somebody's turn to do in this metal material capping.
  13. 13. perforation intermediate plate according to claim 8 is characterized in that, this metal material fills up this conduction perforation, and the material of this metal material is a copper.
  14. 14. perforation intermediate plate according to claim 8 is characterized in that, this first insulating barrier is the hard material, and this second insulating barrier this first insulating barrier relatively is soft material.
CN201210018108.4A 2012-01-19 2012-01-19 Perforation intermediate plate Active CN103219302B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616458A (en) * 2013-11-21 2019-04-12 大日本印刷株式会社 Through electrode substrate and the semiconductor device for utilizing through electrode substrate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1901198A (en) * 2005-06-24 2007-01-24 西门子公司 Electronic assembly and method for producing an electronic assembly
CN101542722A (en) * 2007-04-10 2009-09-23 揖斐电株式会社 Interposer
CN101794717A (en) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 Stacked integrated chips and methods of fabrication thereof
US20100308435A1 (en) * 2009-06-08 2010-12-09 Qualcomm Incorporated Through Silicon Via With Embedded Decoupling Capacitor
US20110304057A1 (en) * 2009-03-04 2011-12-15 Panasonic Corporation Semiconductor device and manufacturing method of the device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1901198A (en) * 2005-06-24 2007-01-24 西门子公司 Electronic assembly and method for producing an electronic assembly
CN101542722A (en) * 2007-04-10 2009-09-23 揖斐电株式会社 Interposer
CN101794717A (en) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 Stacked integrated chips and methods of fabrication thereof
US20110304057A1 (en) * 2009-03-04 2011-12-15 Panasonic Corporation Semiconductor device and manufacturing method of the device
US20100308435A1 (en) * 2009-06-08 2010-12-09 Qualcomm Incorporated Through Silicon Via With Embedded Decoupling Capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616458A (en) * 2013-11-21 2019-04-12 大日本印刷株式会社 Through electrode substrate and the semiconductor device for utilizing through electrode substrate
US11362028B2 (en) 2013-11-21 2022-06-14 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate

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Patentee after: Unimicron Technology (SuZhou) Corp.

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Patentee before: Xinxing Electronics Co., Ltd.

Patentee before: Unimicron Technology (SuZhou) Corp.