KR100727261B1 - Semiconductor device and fabricating method thereof - Google Patents

Semiconductor device and fabricating method thereof Download PDF

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KR100727261B1
KR100727261B1 KR1020060082545A KR20060082545A KR100727261B1 KR 100727261 B1 KR100727261 B1 KR 100727261B1 KR 1020060082545 A KR1020060082545 A KR 1020060082545A KR 20060082545 A KR20060082545 A KR 20060082545A KR 100727261 B1 KR100727261 B1 KR 100727261B1
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semiconductor device
electrode
insulating layer
layer
forming
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KR1020060082545A
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Korean (ko)
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전동기
한재원
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A semiconductor device and a manufacturing method thereof are provided to acquire stably easily a penetrating electrode from the semiconductor device itself by forming the penetrating electrode using a predetermined material with a melting point range of 900°C or less. A semiconductor device includes a semiconductor substrate(10) with a transistor region, an insulating layer, a penetrating electrode, and a metal line layer. The insulating layer is formed on the substrate. The insulating layer has a contact. The penetrating electrode is formed in a through hole(13), wherein the through hole is formed in the insulating layer and the substrate. The metal line layer is formed on the insulating layer in order to be connected with the contact. The metal line layer is made of the same material as that of the penetrating electrode. The penetrating electrode is made of a predetermined material with a melting point range of 900°C or less. The predetermined material is one selected from a group consisting of Au, Ag, Pb and Al.

Description

반도체 소자 및 그 제조방법{Semiconductor device and fabricating method thereof}Semiconductor device and fabrication method

도 1은 종래 반도체 소자 제조방법에 의하여 제조된 SiP(System In a Package) 형태의 반도체 소자를 개념적으로 나타낸 도면.1 is a conceptual view showing a semiconductor device in the form of a system in a package (SiP) manufactured by a conventional semiconductor device manufacturing method.

도 2 내지 도 6은 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 도면.2 to 6 are views for explaining a semiconductor device manufacturing method according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10... 반도체 기판 11... 컨택10 ... Semiconductor Substrate 11 ... Contact

13... 관통홀 15... 금속층13 ... through hole 15 ... metal layer

17... 관통전극 19... 배선층17 through electrode 19 wiring layer

20... 절연층20 ... insulation layer

본 발명은 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device and a method of manufacturing the same.

도 1은 종래 반도체 소자 제조방법에 의하여 제조된 SiP(System In a Package) 형태의 반도체 소자를 개념적으로 나타낸 도면이다.1 is a diagram conceptually illustrating a semiconductor device having a system in a package (SiP) type manufactured by a conventional semiconductor device manufacturing method.

종래 SiP 형태의 반도체 소자는, 도 1에 나타낸 바와 같이, 인터포저(interposer)(11), 제 1 소자(13), 제 2 소자(15), 제 3 소자(17)를 포함한다.As shown in FIG. 1, a conventional SiP type semiconductor device includes an interposer 11, a first device 13, a second device 15, and a third device 17.

상기 제 1 내지 제 3 소자(13)(15)(17)는 예를 들어, CPU, SRAM, DRAM, Frash Memory, Logic LSI, Power IC, Control IC, Analog LSI, MM IC, CMOS RF-IC, Sensor Chip, MEMS Chip 등에서 선택된 어느 하나일 수 있다.The first to third devices 13, 15, and 17 may include, for example, a CPU, an SRAM, a DRAM, a crash memory, a logic LSI, a power IC, a control IC, an analog LSI, an MM IC, a CMOS RF-IC, It may be any one selected from a sensor chip, a MEMS chip, and the like.

상기 제 1 소자(13)와 제 2 소자(15), 제 2 소자(15)와 제 3 소자(17) 간에는 각 소자 간의 신호연결을 위한 연결수단이 형성되어 있다.Connection means for signal connection between the elements is formed between the first element 13 and the second element 15, the second element 15, and the third element 17.

상기 각 소자 간의 신호연결을 위한 연결수단의 하나로서 관통전극(through via)이 제시될 수 있다. 상기 관통전극은 상기 소자를 관통하여 형성된 전극으로서, 해당 소자와 상부에 적층되는 소자를 전기적으로 연결하는 기능을 수행할 수 있다. 또한 상기 관통전극은 해당 소자와 하부에 적층되는 소자를 전기적으로 연결하는 기능을 수행할 수도 있다.Through vias may be provided as one of the connection means for signal connection between the devices. The through electrode is an electrode formed through the device and may perform a function of electrically connecting the device and a device stacked thereon. In addition, the through electrode may perform a function of electrically connecting a corresponding device and a device stacked below.

이러한 관통전극 물질로는 일반적으로 저항이 낮은 어떠한 금속도 사용이 가능하다. 하지만, 관통전극의 구경(diameter)에 비하여 상부와 하부 칩 간의 거리가 약 10~50㎛ 정도로 aspect ratio(칩 간 거리 vs 구경) 로 보면 약 50:1 ~ 300:1 정도가 된다. 이에 따라, 상부 영역부터 하부 영역에 이르기까지 안정적으로 연결된 관통전극을 형성하기가 어렵다는 문제점이 있다.As the through electrode material, any metal having low resistance can be used. However, when the aspect ratio (distance between chips vs. aperture) is about 10 to 50 μm, the distance between the upper and lower chips is about 50: 1 to about 300: 1 compared to the diameter of the through electrode. Accordingly, there is a problem that it is difficult to form a through electrode stably connected from the upper region to the lower region.

따라서, 이와 같이 가늘고 긴 관통전극을 효율적이고 안정적으로 형성할 수 있는 방안이 제시되어야 한다.Therefore, a method for efficiently and stably forming the thin and long through electrode should be proposed.

본 발명은 SiP(System In a Package) 형태를 갖는 반도체 소자의 상부에 위치되는 소자와 하부에 위치된 소자 간에 신호를 연결하는 관통전극을 안정적으로 형성할 수 있는 반도체 소자 및 그 제조방법을 제공함에 그 목적이 있다.The present invention provides a semiconductor device capable of stably forming a through electrode for connecting a signal between a device positioned above and a device positioned below the semiconductor device having a System In a Package (SiP) form and a method of manufacturing the same. The purpose is.

상기 목적을 달성하기 위하여 본 발명에 따른 반도체 소자는, 트랜지스터 영역이 형성된 반도체 기판; 상기 반도체 기판 위에 형성되며, 컨택을 구비하는 절연층; 상기 절연층 및 상기 반도체 기판에 형성된 관통홀에 채워진 관통전극; 상기 관통전극과 동일 물질로 형성되며, 상기 절연층 위에 형성되어 상기 컨택과 연결된 배선층; 을 포함한다.In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate on which a transistor region is formed; An insulating layer formed on the semiconductor substrate and having a contact; A through electrode filled in the through hole formed in the insulating layer and the semiconductor substrate; A wiring layer formed of the same material as the through electrode and formed on the insulating layer and connected to the contact; It includes.

또한 본 발명에 의하면, 상기 관통전극은 용융점이 900℃ 보다 낮은 금속으로 형성되며, 상기 관통전극은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성된다.According to the present invention, the through electrode is formed of a metal having a melting point lower than 900 ° C., and the through electrode is formed of any one or more materials selected from gold, silver, lead, and aluminum.

또한 상기 목적을 달성하기 위하여 본 발명에 따른 반도체 소자 제조방법은, 반도체 기판 위에 컨택을 구비하는 절연층을 형성하는 단계; 상기 절연층 및 상기 반도체 기판에 관통홀을 형성하는 단계; 상기 결과물 위에 금속층을 형성하는 단계; 상기 금속층에 대한 열처리를 통하여, 상기 금속층을 이루는 금속을 용융시켜 상기 관통홀을 채우는 관통전극을 형성하는 단계; 를 포함한다.In addition, the semiconductor device manufacturing method according to the present invention in order to achieve the above object, forming an insulating layer having a contact on the semiconductor substrate; Forming through holes in the insulating layer and the semiconductor substrate; Forming a metal layer on the resultant; Forming a through electrode filling the through hole by melting the metal constituting the metal layer through heat treatment of the metal layer; It includes.

또한 본 발명에 의하면, 상기 금속층은 용융점이 900℃ 보다 낮은 금속으로 형성되며, 상기 금속층은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성된다.In addition, according to the present invention, the metal layer is formed of a metal having a melting point lower than 900 ℃, the metal layer is formed of any one or more materials selected from gold, silver, lead, aluminum.

또한 본 발명에 의하면, 상기 열처리는 노(furnace)을 이용하여 처리하거나 또는 RTP 방식에 의하여 처리한다.In addition, according to the present invention, the heat treatment is processed by using a furnace (furnace) or by the RTP method.

또한 본 발명에 의하면, 상기 관통전극을 형성하는 단계 이후에, 상기 절연층 위에 있는 금속층에 대한 패터닝을 수행하여, 상기 컨택과 연결된 배선층을 형성하는 단계를 더 포함한다.According to the present invention, after the forming of the through electrode, patterning the metal layer on the insulating layer further comprises the step of forming a wiring layer connected to the contact.

또한 본 발명에 의하면, 상기 관통전극을 형성하는 단계 이후에, 상기 반도체 기판의 뒷면을 연마하여 상기 관통전극을 노출시키는 단계를 더 포함한다.According to the present invention, after the step of forming the through electrode, the step of polishing the back of the semiconductor substrate further comprises the step of exposing the through electrode.

이와 같은 본 발명에 의하면, SiP(System In a Package) 형태를 갖는 반도체 소자의 상부에 위치되는 소자와 하부에 위치된 소자 간에 신호를 연결하는 관통전극을 안정적으로 형성할 수 있는 장점이 있다.According to the present invention, there is an advantage that it is possible to stably form a through electrode for connecting a signal between the device located above and the device located above the semiconductor device having a System In a Package (SiP) form.

본 발명에 따른 실시 예의 설명에 있어서, 각 층(막), 영역, 패턴 또는 구조물들이 기판, 각 층(막), 영역, 패드 또는 패턴들의 "위(on/above/over/upper)"에 또는 "아래(down/below/under/lower)"에 형성되는 것으로 기재되는 경우에 있어, 그 의미는 각 층(막), 영역, 패드, 패턴 또는 구조물들이 직접 기판, 각 층(막), 영역, 패드 또는 패턴들에 접촉되어 형성되는 경우로 해석될 수도 있으며, 다른 층(막), 다른 영역, 다른 패드, 다른 패턴 또는 다른 구조물들이 그 사이에 추가적으로 형성되는 경우로 해석될 수도 있다. 따라서, 그 의미는 발명의 기술적 사상에 의하여 판단되어야 한다.In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is "on / above / over / upper" of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure formed in between. Therefore, the meaning should be determined by the technical spirit of the invention.

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2 내지 도 6은 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 도 면이다.2 to 6 are views for explaining a semiconductor device manufacturing method according to the present invention.

본 발명에 따른 반도체 소자 제조방법은, 도 2 내지 도 6에 나타낸 바와 같이, 먼저 트랜지스터 영역이 형성된 반도체 기판(10) 위에 컨택(11)을 구비하는 절연층(20)을 형성한다. 도 3에서는 상기 절연층(20)이 PMD(Pre Metal Dielectric)층인 경우를 예로서 나타내었다.In the method of manufacturing a semiconductor device according to the present invention, as shown in FIGS. 2 to 6, first, an insulating layer 20 including a contact 11 is formed on a semiconductor substrate 10 on which a transistor region is formed. In FIG. 3, a case in which the insulating layer 20 is a PMD layer is illustrated as an example.

그러나, 본 발명에 의하면 상기 절연층(20)은 PMD(Pre Metal Dielectric)층에 한정되지 않으며, 상기 절연층(20)은 IMD(Inter Metal Dielectric)층이 될 수도 있으며, 상기 절연층(20)과 상기 반도체 기판(10) 사이에 컨택을 구비하는 복수의 절연층이 더 구비될 수도 있다. However, according to the present invention, the insulating layer 20 is not limited to a pre metal dielectric (PMD) layer, and the insulating layer 20 may be an inter metal dielectric (IMD) layer, and the insulating layer 20 A plurality of insulating layers may be further provided between the semiconductor substrate 10 and the semiconductor substrate 10.

이어서 도 4에 나타낸 바와 같이, 상기 절연층(20) 및 상기 반도체 기판(10)에 관통홀(13)을 형성한다. 상기 관통홀(13)은 상기 절연층(20)을 관통하도록 형성되며, 상기 반도체 기판(10)의 소정 깊이까지 형성되도록 할 수 있다.Subsequently, as shown in FIG. 4, through holes 13 are formed in the insulating layer 20 and the semiconductor substrate 10. The through hole 13 may be formed to penetrate the insulating layer 20, and may be formed to a predetermined depth of the semiconductor substrate 10.

그리고, 도 5에 나타낸 바와 같이, 상기 결과물 위에 금속층(15)을 형성한다.As shown in FIG. 5, a metal layer 15 is formed on the resultant.

상기 금속층(15)은 용융점이 낮은 금속, 예컨대 용융점이 900℃ 보다 낮은 금속으로 형성되도록 할 수 있다. 예로서 상기 금속층(15)은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성되도록 할 수 있다.The metal layer 15 may be formed of a metal having a low melting point, for example, a metal having a melting point lower than 900 ° C. For example, the metal layer 15 may be formed of any one or more materials selected from gold, silver, lead, and aluminum.

이후, 상기 금속층(15)에 대한 열처리를 통하여, 상기 금속층(15)을 이루는 금속을 용융시켜 상기 관통홀(13)을 채우는 관통전극(17)을 형성한다.Subsequently, through the heat treatment of the metal layer 15, the metal forming the metal layer 15 is melted to form a through electrode 17 filling the through hole 13.

상기 열처리는 노(furnace)을 이용하여 처리하거나 또는 RTP 방식에 의하여 처리할 수 있다.The heat treatment may be performed using a furnace or by RTP.

이와 같이 본 발명에 의하면 용융점이 낮은 금속층(15)에 대한 열처리를 통하여 상기 금속층(15)이 용융되도록 할 수 있다. 이에 따라, 용융된 상기 금속이 상기 관통홀(13)을 채울 수 있게 되며, 상기 관통전극(17)은 상기 관통홀(13)의 바닥부에까지 안정적으로 형성될 수 있게 된다.As described above, according to the present invention, the metal layer 15 may be melted through heat treatment of the metal layer 15 having a low melting point. Accordingly, the molten metal can fill the through hole 13, and the through electrode 17 can be stably formed to the bottom of the through hole 13.

본 발명에 의하면, PVD와 같은 증착 방법을 통하여 금속층(15)을 형성하고, 그 결과물에 대한 열처리를 통하여 관통전극(17)을 형성할 수 있게 된다. 이에 따라 본 발명에 따른 반도체 소자 제조방법에 의하면 상기 관통전극(17)을 안정적으로 형성할 수 있게 되며, 또한 제조 비용을 감소시킬 수 있게 된다.According to the present invention, the metal layer 15 may be formed through a deposition method such as PVD, and the through electrode 17 may be formed through heat treatment of the resultant. Accordingly, according to the method of manufacturing a semiconductor device according to the present invention, the through electrode 17 can be stably formed and the manufacturing cost can be reduced.

또한 본 발명에 의하면, 상기 관통전극(17)을 형성하는 단계 이후에, 상기 절연층(20) 위에 있는 금속층에 대한 패터닝을 수행하여, 상기 컨택(11)과 연결된 배선층(19)을 형성하는 단계를 더 포함한다.According to the present invention, after forming the through electrode 17, patterning the metal layer on the insulating layer 20 to form a wiring layer 19 connected to the contact 11. It further includes.

또한 본 발명에 의하면, 상기 관통전극(17)을 형성하는 단계 이후에, 상기 반도체 기판(10)의 뒷면을 연마하여 상기 관통전극(17)을 노출시키는 단계를 더 수행할 수도 있다.In addition, according to the present invention, after the forming of the through electrode 17, the step of polishing the back surface of the semiconductor substrate 10 may further perform the step of exposing the through electrode 17.

따라서 본 발명에 따른 반도체 소자 제조방법에 의하면, SiP(System In a Package) 형태를 갖는 반도체 소자의 상부에 위치되는 소자와 하부에 위치된 소자 간에 신호를 연결하는 관통전극을 안정적으로 형성할 수 있게 된다.Therefore, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to stably form a through electrode connecting a signal between a device located above and a device positioned below the semiconductor device having a System In a Package (SiP) form. do.

이와 같은 반도체 소자 제조방법에 의하여 제조된 반도체 소자는 트랜지스터 영역이 형성된 반도체 기판(10)과, 상기 반도체 기판(10) 위에 형성되며 컨택(11) 을 구비하는 절연층(20)을 포함한다.The semiconductor device manufactured by the semiconductor device manufacturing method as described above includes a semiconductor substrate 10 having a transistor region formed thereon and an insulating layer 20 formed on the semiconductor substrate 10 and having a contact 11.

본 발명에 의하면 상기 절연층(20)은 PMD(Pre Metal Dielectric)층에 한정되지 않으며, 상기 절연층(20)은 IMD(Inter Metal Dielectric)층이 될 수도 있으며, 상기 절연층(20)과 상기 반도체 기판(10) 사이에 컨택을 구비하는 복수의 절연층이 더 구비될 수도 있다. According to the present invention, the insulating layer 20 is not limited to a PMD (Pre Metal Dielectric) layer, and the insulating layer 20 may be an IMD (Inter Metal Dielectric) layer, and the insulating layer 20 and the A plurality of insulating layers having contacts between the semiconductor substrates 10 may be further provided.

또한 본 발명에 따른 반도체 소자는 상기 절연층(20) 및 상기 반도체 기판(10)에 형성된 관통홀(13)에 채워진 관통전극(17)을 포함한다. 또한 본 발명에 따른 반도체 소자는 상기 관통전극(17)과 동일 물질로 형성되며, 상기 절연층(20) 위에 형성되어 상기 컨택(11)과 연결된 배선층(19)을 포함한다.In addition, the semiconductor device according to the present invention includes the insulating layer 20 and the through electrode 17 filled in the through hole 13 formed in the semiconductor substrate 10. In addition, the semiconductor device according to the present invention includes a wiring layer 19 formed of the same material as the through electrode 17 and formed on the insulating layer 20 and connected to the contact 11.

또한 본 발명에 의하면, 상기 관통전극(17)은 용융점이 900℃ 보다 낮은 금속으로 형성되며, 예로서 상기 관통전극(17)은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성될 수 있다.In addition, according to the present invention, the through electrode 17 is formed of a metal having a melting point lower than 900 ° C. For example, the through electrode 17 may be formed of any one or more materials selected from gold, silver, lead, and aluminum. have.

이에 따라 본 발명에 따른 반도체 소자는, SiP(System In a Package) 형태를 갖는 반도체 소자의 상부에 위치되는 소자와 하부에 위치된 소자 간에 신호를 연결하는 관통전극을 안정적으로 형성할 수 있게 된다.Accordingly, the semiconductor device according to the present invention can stably form a through electrode for connecting a signal between a device positioned above and a device positioned below the semiconductor device having a System In a Package (SiP) form.

이상의 설명에서와 같이 본 발명에 따른 반도체 소자 및 그 제조방법에 의하면, SiP(System In a Package) 형태를 갖는 반도체 소자의 상부에 위치되는 소자와 하부에 위치된 소자 간에 신호를 연결하는 관통전극을 안정적으로 형성할 수 있는 장점이 있다.As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, a through electrode connecting a signal between a device located above and a device positioned below the semiconductor device having a SiP (System In a Package) form There is an advantage that can be formed stably.

Claims (10)

트랜지스터 영역이 형성된 반도체 기판;A semiconductor substrate on which a transistor region is formed; 상기 반도체 기판 위에 형성되며, 컨택을 구비하는 절연층;An insulating layer formed on the semiconductor substrate and having a contact; 상기 절연층 및 상기 반도체 기판에 형성된 관통홀에 채워진 관통전극;A through electrode filled in the through hole formed in the insulating layer and the semiconductor substrate; 상기 관통전극과 동일 물질로 형성되며, 상기 절연층 위에 형성되어 상기 컨택과 연결된 배선층;A wiring layer formed of the same material as the through electrode and formed on the insulating layer and connected to the contact; 을 포함하는 것을 특징으로 하는 반도체 소자.A semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 관통전극은 용융점이 900℃ 보다 낮은 금속으로 형성된 것을 특징으로 하는 반도체 소자.The through electrode is a semiconductor device, characterized in that the melting point is formed of a metal lower than 900 ℃. 제 1항에 있어서,The method of claim 1, 상기 관통전극은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성된 것을 특징으로 하는 반도체 소자.The through electrode is a semiconductor device, characterized in that formed of any one or more materials selected from gold, silver, lead, aluminum. 반도체 기판 위에 컨택을 구비하는 절연층을 형성하는 단계;Forming an insulating layer having a contact on the semiconductor substrate; 상기 절연층 및 상기 반도체 기판에 관통홀을 형성하는 단계;Forming through holes in the insulating layer and the semiconductor substrate; 상기 결과물 위에 금속층을 형성하는 단계;Forming a metal layer on the resultant; 상기 금속층에 대한 열처리를 통하여, 상기 금속층을 이루는 금속을 용융시켜 상기 관통홀을 채우는 관통전극을 형성하는 단계;Forming a through electrode filling the through hole by melting the metal constituting the metal layer through heat treatment of the metal layer; 를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Semiconductor device manufacturing method comprising a. 제 4항에 있어서,The method of claim 4, wherein 상기 금속층은 용융점이 900℃ 보다 낮은 금속으로 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The metal layer is a semiconductor device manufacturing method, characterized in that the melting point is formed of a metal lower than 900 ℃. 제 4항에 있어서,The method of claim 4, wherein 상기 금속층은 금, 은, 납, 알루미늄에서 선택된 어느 하나 이상의 물질로 형성된 것을 특징으로 하는 반도체 소자 제조방법.The metal layer is a semiconductor device manufacturing method, characterized in that formed of one or more materials selected from gold, silver, lead, aluminum. 제 4항에 있어서,The method of claim 4, wherein 상기 열처리는 노(furnace)을 이용하여 처리하거나 또는 RTP 방식에 의하여 처리하는 것을 특징으로 하는 반도체 소자 제조방법. The heat treatment is a semiconductor device manufacturing method characterized in that the treatment using a furnace (furnace) or by the RTP method. 제 4항에 있어서,The method of claim 4, wherein 상기 관통전극을 형성하는 단계 이후에,After forming the through electrode, 상기 절연층 위에 있는 금속층에 대한 패터닝을 수행하여, 상기 컨택과 연결된 배선층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조방 법.And patterning the metal layer on the insulating layer, thereby forming a wiring layer connected to the contact. 제 4항에 있어서,The method of claim 4, wherein 상기 관통전극을 형성하는 단계 이후에,After forming the through electrode, 상기 반도체 기판의 뒷면을 연마하여 상기 관통전극을 노출시키는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조방법.And polishing the back surface of the semiconductor substrate to expose the through electrode. 제 4항에 있어서,The method of claim 4, wherein 상기 금속층은 PVD 방법에 의하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The metal layer is a semiconductor device manufacturing method, characterized in that formed by the PVD method.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817718B1 (en) * 2006-12-27 2008-03-27 동부일렉트로닉스 주식회사 Semiconductor device fabricating method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050061573A (en) * 2002-10-28 2005-06-22 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Method and apparatus to improve picture aesthetics during switch-on of a screen
KR20060058953A (en) * 2004-11-26 2006-06-01 삼성전자주식회사 Packaged semiconductor die and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050061573A (en) * 2002-10-28 2005-06-22 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Method and apparatus to improve picture aesthetics during switch-on of a screen
KR20060058953A (en) * 2004-11-26 2006-06-01 삼성전자주식회사 Packaged semiconductor die and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100817718B1 (en) * 2006-12-27 2008-03-27 동부일렉트로닉스 주식회사 Semiconductor device fabricating method
US7709381B2 (en) 2006-12-27 2010-05-04 Dongbu Hi Tek Co., Ltd. Semiconductor device fabricating method

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