CN103208308A - Continuous ramp pulse type writing circuit in resistive random access memory - Google Patents
Continuous ramp pulse type writing circuit in resistive random access memory Download PDFInfo
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- CN103208308A CN103208308A CN2013101733363A CN201310173336A CN103208308A CN 103208308 A CN103208308 A CN 103208308A CN 2013101733363 A CN2013101733363 A CN 2013101733363A CN 201310173336 A CN201310173336 A CN 201310173336A CN 103208308 A CN103208308 A CN 103208308A
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Abstract
The invention discloses a continuous ramp pulse type writing circuit in a resistive random access memory. The continuous ramp pulse type writing circuit comprises a voltage stabilizing circuit, a resistor, a current mirror, a capacitor, a gate tube, a variable-resistance unit and a transistor, wherein the output end of the voltage stabilizing circuit is connected into the input end of the current mirror by the resistor; the output end of the current mirror is connected with the capacitor in parallel; simultaneously, the output end of the current mirror is also added on the variable-resistance unit by the gate tube; and the other end of the variable-resistance unit is grounded by the transistor. The continuous ramp pulse type writing circuit disclosed by the invention has the advantages of fastness in resetting operation and high device durability.
Description
Technical field
The invention belongs to integrated circuit fields, be specifically related to continuous slope pulsed write circuit in a kind of resistance-variable storing device.
Background technology
Resistance-variable storing device (RRAM) is a kind of novel nonvolatile memory, and is simple in structure because of it, and good with the CMOS processing compatibility, contractibility is good, so resistance-variable storing device has obtained research widely.Resistance-variable storing device has four kinds of basic operations: the initialization operation of unit (forming); Set operation (set), low-resistance is put in main realization; Reset operation (reset) realizes putting high resistant; Read operation (read).The current change for great majority hinders material, the set operating performance is better, and speed reaches 10ns, and success ratio can reach 100%, but operate for reset, performance is unsatisfactory, mainly contains two shortcomings: the first, and the running time is long, and have a very wide distribution, general reset operation will reach about 100us, and in the same array, different units reset time similar normal state is distributed in 100ns-1ms; The second, reset success ratio is low, for WO
xThe group of resistive material is compiled storer, and a reset success ratio so just needs multiple algorithm to improve success ratio less than 30%; The 3rd, the discreteness of high resistant is big, between high resistance area be 100k ohm to 10M ohm, window reaches 100 times between high resistance area.In order to address these problems, some scholars have proposed following three kinds of schemes:
(1) reset schemes of continuous constant amplitude, its principle is shown in Fig. 1 (a): if a reset operation is unsuccessful, then repeat repeatedly reset operation, until success.The advantage of this scheme has been to promote the success ratio of reset operation, but or some unit, increase the how many times reset operation and all can not successfully reset, therefore consider to promote success ratio by the amplitude that increases reset operation.
(2) reset schemes of slope pulse, its principle is shown in Fig. 1 (b): in the time will realizing high resistant, the existing high resistant that does not reach critical value 1M ohm of checking after usefulness-0.9V square wave resets for the first time, then with high 0.1V-the 1.0V square-wave pulse resets again, if be proved to be successful then interrupt operation, otherwise continue rising 0.1V.This scheme has improved the success ratio of reset operation, and success ratio can reach more than 90%, and has promoted the resistance of high resistant, has enlarged the resistance window, has improved the resistance discreteness.The shortcoming of this scheme is: repeatedly reset has made the write operation time lengthening more than the twice, deteriorates to 2us from before 1us, and operating speed reduces by half; One time high resistant on average needs twice reset operation, half before the permanance of device is low to moderate, and the memory read/write number of times reduces by half.
(3) reset schemes of increase pulsewidth, its principle is shown in Fig. 1 (c), carry out reset operation one time, checking back is found not reach desirable resistance, increases reset operation burst length Treset then, if is that all right merit, then increase pulse width again, increase by twice at most, if can't be successful, then continue to repeat to reset with the wideest pulse.Such scheme also can promote the reset operation success ratio, but effect is generally effective not as slope pulse scheme.The shortcoming of this scheme is: the reset operation time generally reaches 100us, if improve success ratio by increasing pulse width again, seriously reduces reset speed; Limited to the reset operation effect, the aaset bit operating effect is comparatively obvious, and therefore for the long change resistance material of reset operation, this scheme is inapplicable.
Summary of the invention
The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or provides a kind of useful commerce to select at least.For this reason, the objective of the invention is to propose a kind of continuous slope pulsed write circuit in the resistance-variable storing device that reset operation is fast, the device permanance is high that has.
According to continuous slope pulsed write circuit in the resistance-variable storing device of the embodiment of the invention, comprise: mu balanced circuit, resistance, current mirror, electric capacity, gate tube, change resistance unit and transistor, wherein: the output terminal of described mu balanced circuit inserts the input end of described current mirror by described resistance, the output terminal of described current mirror described electric capacity in parallel, the output terminal of described current mirror also is added on the described change resistance unit by described gate tube simultaneously, and the other end of described change resistance unit is through described transistor ground connection.
In the resistance-variable storing device of the present invention continuously slope pulsed write circuit have following advantage: 1, adopt trapezoidal wave to meet RRAM unit component characteristic most, therefore pulse high resistant of just can realizing ideal.RRAM unit reset operation is realized high value and institute's making alive amplitude direct ratio, and the unit accumulates enough energy could realize that resistance changes.Trapezoidal wave amplitude in the same burst length is higher, and the energy that applies is bigger, the high resistant that can realize ideal.2, because only need once reset, so the reset operation time of device the shortest, speed is faster, and permanance is the highest.
Additional aspect of the present invention and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment in conjunction with following accompanying drawing, wherein:
Fig. 1 is the schematic diagram of reset schemes among the existing RRAM;
Fig. 2 is the schematic diagram of the reset schemes of continuous slope pulsed among the RRAM of the present invention; With
Fig. 3 is the circuit diagram of continuous slope pulsed write circuit among the RRAM of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical or similar label is represented identical or similar elements or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
In the present invention, unless clear and definite regulation and restriction are arranged in addition, broad understanding should be done in terms such as term " installation ", " linking to each other ", " connection ", " fixing ", for example, can be fixedly connected, also can be to removably connect, or connect integratedly; Can be mechanical connection, also can be to be electrically connected; Can be directly to link to each other, also can link to each other indirectly by intermediary, can be the connection of two element internals.For the ordinary skill in the art, can understand above-mentioned term concrete implication in the present invention as the case may be.
As mentioning in the background technology, existing scheme all adopts square-wave pulse, adopted repeatedly reset operation, and the present invention has used the trapezoidal wave pulse first, only need once reset the high resistant of just can realizing ideal.
The schematic diagram of the reset schemes of continuous slope pulsed as shown in Figure 2 among the RRAM that the present invention proposes, when needing reset operation, adopt trapezoidal wave as follows to reset, trapezoidal wave is in the time of a pulse, amplitude has covered the selectable voltage scope of reset operation by 0.7V added value 1.2V.
According to continuously the circuit diagram of slope pulsed write circuit is as shown in Figure 3 among the RRAM of the embodiment of the invention, comprise: mu balanced circuit 100, resistance 200, current mirror 300, electric capacity 400, gate tube 500, change resistance unit 600 and transistor 700, wherein: the output terminal of mu balanced circuit 100 inserts the input end of current mirror 300 by resistance 200, the output terminal shunt capacitance 400 of current mirror 300, the output terminal of current mirror 300 also is added in by gate tube 500 and becomes on the resistance unit 600 simultaneously, and this other end that becomes resistance unit 600 is through transistor 700 ground connection.
In this write circuit, mu balanced circuit 100 and resistance 200 produce stable input current, and electric capacity 400 chargings of 300 pairs of output terminals of current mirror can obtain an ever-increasing ramp type output voltage of amplitude, be added on the change resistance unit 600 by gate tube 500, constitute continuous slope write pulse.Become the transistor 700 of resistance unit 600 another terminations, in array, select to want operated unit, when set operation, by controlling its gate input voltage, can realize current limliting simultaneously, prevent the excessive low-resistance that causes of electric current problem on the low side.
In sum, continuous slope pulsed write circuit has following advantage among the RRAM of the present invention:
1, adopt trapezoidal wave to meet RRAM unit component characteristic most, therefore pulse high resistant of just can realizing ideal.RRAM unit reset operation is realized high value and institute's making alive amplitude direct ratio, and the unit accumulates enough energy could realize that resistance changes.Trapezoidal wave amplitude in the same burst length is higher, and the energy that applies is bigger, the high resistant that can realize ideal.
2, because only need once reset, so the reset operation time of device the shortest, speed is faster, and permanance is the highest.
In the description of this instructions, concrete feature, structure, material or characteristics that the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example description are contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete feature, structure, material or the characteristics of description can be with the suitable manner combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment under the situation that does not break away from principle of the present invention and aim within the scope of the invention, modification, replacement and modification.
Claims (1)
1. slope pulsed write circuit continuously in the resistance-variable storing device is characterized in that, comprising: mu balanced circuit, resistance, current mirror, electric capacity, gate tube, change resistance unit and transistor, wherein:
The output terminal of described mu balanced circuit inserts the input end of described current mirror by described resistance, the output terminal of described current mirror described electric capacity in parallel, the output terminal of described current mirror also is added on the described change resistance unit by described gate tube simultaneously, and the other end of described change resistance unit is through described transistor ground connection.
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| CN201310173336.3A CN103208308B (en) | 2013-05-10 | 2013-05-10 | Continuous slope pulsed write circuit in resistance-variable storing device |
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| CN201310173336.3A CN103208308B (en) | 2013-05-10 | 2013-05-10 | Continuous slope pulsed write circuit in resistance-variable storing device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022617A (en) * | 2016-11-04 | 2018-05-11 | 财团法人工业技术研究院 | Variable resistance memory circuit and writing method of variable resistance memory circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350225A (en) * | 2007-05-23 | 2009-01-21 | 三星电子株式会社 | Nonvolatile memory device using variable resistive materials |
| US20100110760A1 (en) * | 2008-10-31 | 2010-05-06 | Seagate Technology Llc | Resistive Sense Memory Calibration for Self-Reference Read Method |
-
2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350225A (en) * | 2007-05-23 | 2009-01-21 | 三星电子株式会社 | Nonvolatile memory device using variable resistive materials |
| US20100110760A1 (en) * | 2008-10-31 | 2010-05-06 | Seagate Technology Llc | Resistive Sense Memory Calibration for Self-Reference Read Method |
Non-Patent Citations (3)
| Title |
|---|
| 于杰，张文俊，焦斌: "《基于WO_x阻变材料的RRAM电路设计》", 《固体电子学研究与进展》 * |
| 吴雨欣，李萌，林殷茵: "《一种提高阻变存储器擦除可靠性的写电路设计》", 《固体电子学研究与进展》 * |
| 金钢，吴雨欣等: "《基于0_13m标准逻辑工艺的1Mb阻变存储器设计与实现》", 《固体电子学研究与进展》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022617A (en) * | 2016-11-04 | 2018-05-11 | 财团法人工业技术研究院 | Variable resistance memory circuit and writing method of variable resistance memory circuit |
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Effective date of registration: 20180903 Address after: The 100084 Zhongguangcun, Haidian District, Beijing Cities street Zhi Zao D 315 Patentee after: Beijing Xin Yi Science and Technology Ltd.s Address before: 100084 Haidian District 100084-82 mailbox in Beijing Patentee before: Tsinghua University |