CN103199852B - A kind of analog multiplier for Active PFC chip - Google Patents

A kind of analog multiplier for Active PFC chip Download PDF

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CN103199852B
CN103199852B CN201310080944.XA CN201310080944A CN103199852B CN 103199852 B CN103199852 B CN 103199852B CN 201310080944 A CN201310080944 A CN 201310080944A CN 103199852 B CN103199852 B CN 103199852B
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type triode
pnp type
resistance
emitter
connects
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CN103199852A (en
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方健
谷洪波
彭宜建
王贺龙
贾姚瑶
赵前利
张波
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University of Electronic Science and Technology of China
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Abstract

For an analog multiplier of FPC, belong to electronic technology field.Comprise output circuit four modules that prime differential amplifier, active attenuator, second level differential amplifier and current signal are converted into voltage signal.Compared to conventional P FC multiplier circuit, the present invention adopts active attenuator, and in active attenuator, introduce negative feedback, in the differential amplifier of the second level, P type triode emitter-base bandgap grading introduces resistance respectively, and adopt β helper structure, said structure reduces the nonlinearity erron of multiplier greatly.

Description

A kind of analog multiplier for Active PFC chip
Technical field
The invention belongs to electronic technology field, relate to the analog multiplier circuit in integrated circuit technique, be specifically related to a kind of analog multiplier for PFC of nonlinear error reduction.
Background technology
Along with the various power electronic equipments taking Switching Power Supply as representative get more and more, create a large amount of current harmonics components and blow back into electrical network, cause the harmonic pollution of electrical network.In order to suppress these current harmonics components, usually adopt Active PFC (Power Factor Correction is called for short PFC) technology.And the analog multiplier module that to be most PFC chip indispensable, and improving the linearity of multiplier, nonlinear error reduction becomes an important directions of research analog multiplier.
Summary of the invention
The object of the invention is the nonlinearity erron in order to reduce analog multiplier in PFC technology, and propose a kind of analog multiplier for FPC, this analog multiplier has minimum nonlinearity erron.
Technical scheme of the present invention is:
A kind of analog multiplier for Active PFC chip, as shown in Figure 2, this analog multiplier is used for Active PFC chip, comprise module one, module two, module three, module four, wherein module one is prime differential amplifier, module two is active attenuator, and module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal.
Described prime differential amplifier comprises two PMOS MP1 and MP2, three NMOS tube MN1, MN2 and MN3, crossing current source I, two resistance R1 and R2, and two PNP type triode QP1 and QP2; The source electrode of PMOS MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS MP1 and drain interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS MP2 connects the emitter of PNP type triode QP1 on the one hand by resistance R1, connect the emitter of PNP type triode QP2 on the other hand by resistance R2; The base stage of PNP type triode QP1 inputs the first input signal VCOMP, the base stage input offset voltage VB of PNP type triode QP2; The source ground GND of NMOS tube MN1, MN2 and MN3, the gate interconnection of NMOS tube MN1 and MN2, the grid of NMOS tube MN1 and drain interconnection also connect the collector electrode of PNP type triode QP1, the drain electrode of NMOS tube MN2 and MN3 connects the collector electrode of PNP type triode QP2, the grid of NMOS tube MN3 and drain interconnection.
Described active attenuator comprises a PMOS MP3, two NPN type triode QN1 and QN2, two PNP type triode QP3 and QP4, five resistance R3, R4, R5, R6 and R7; The source electrode of PMOS MP3 meets supply voltage VDD, and its grid connects the grid of PMOS MP1 and MP2 in prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 sequentially passes through resistance R3 and R6 ground connection GND on the one hand, is connect the emitter of PNP type triode QP3 on the other hand by resistance R4; The base stage of PNP type triode QP3 is by resistance R6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of PNP type triode QP4 by resistance R5, the base stage of PNP type triode QP4 meets the second input signal VMULT by resistance R7, the grounded collector GND of PNP type triode QP3 and QP4.
Described second level differential amplifier comprises three PNP type triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS tube MN4 also comprises two resistance R8 and R9; The emitter of PNP type triode QP5 meets supply voltage VDD by resistance R8, the emitter of PNP type triode QP6 meets supply voltage VDD by resistance R9, the base stage interconnection of PNP type triode QP5 and QP6, the collector electrode of PNP type triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of PNP type triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of PNP type triode QP9 connects the base stage of PNP type triode QP5 and QP6, and its base stage connects the collector electrode of PNP type triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 connects the emitter of NPN type triode QN1 in active attenuator, and the base stage of NPN type triode QN4 connects the emitter of NPN type triode QN2 in active attenuator; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS tube MN4 jointly, and the grid of NMOS tube MN4 connects the grid of NMOS tube MN3 in prime differential amplifier, the source ground GND of NMOS tube MN4.
The output circuit that described current signal is converted into voltage signal comprises three PNP type triode QP7, QP8 and QP10, and three resistance R11, R12 and R13 also comprise a filter capacitor CL, the emitter of PNP type triode QP7 meets supply voltage VDD by resistance R11, the emitter of PNP type triode QP8 meets supply voltage VDD by resistance R12, the base stage interconnection of PNP type triode QP7 and QP8, the base stage of PNP type triode QP8 and collector electrode interconnect and connect the emitter of PNP type triode QP10, the base stage of PNP type triode QP10 connects the collector electrode of PNP type triode QP6 in the collector electrode of PNP type triode QP7 and second level differential amplifier, the collector electrode of PNP type triode QP10 passes through the parallel circuits ground connection GND of resistance R13 and filter capacitor CL, the collector electrode of PNP type triode QP10 exports the output signal VOUT of whole analog multiplier.
The invention has the beneficial effects as follows: compared to conventional P FC multiplier circuit, as shown in Fig. 2 module two, the present invention adopts active attenuator, and in active attenuator, introduce negative feedback, in module three, P type triode emitter-base bandgap grading introduces resistance respectively, and adopt β helper structure, said structure reduces the nonlinearity erron of multiplier greatly.
Accompanying drawing explanation
Fig. 1 is analog multiplier circuit schematic diagram provided by the invention.
Fig. 2 is analog multiplier circuit structure chart provided by the invention.
Fig. 3 is analog multiplier circuit principle schematic provided by the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is further illustrated.
Analog multiplier circuit provided by the invention as shown in Figure 1.
The analog multiplier provided of the present invention, as shown in Figure 2, this analog multiplier is used for Active PFC chip, comprise module one, module two, module three, module four, wherein module one is prime differential amplifier, module two is active attenuator, and module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal.
Described prime differential amplifier comprises two PMOS MP1 and MP2, three NMOS tube MN1, MN2 and MN3, crossing current source I, two resistance R1 and R2, and two PNP type triode QP1 and QP2; The source electrode of PMOS MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS MP1 and drain interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS MP2 connects the emitter of PNP type triode QP1 on the one hand by resistance R1, connect the emitter of PNP type triode QP2 on the other hand by resistance R2; The base stage of PNP type triode QP1 inputs the first input signal VCOMP, the base stage input offset voltage VB of PNP type triode QP2; The source ground GND of NMOS tube MN1, MN2 and MN3, the gate interconnection of NMOS tube MN1 and MN2, the grid of NMOS tube MN1 and drain interconnection also connect the collector electrode of PNP type triode QP1, the drain electrode of NMOS tube MN2 and MN3 connects the collector electrode of PNP type triode QP2, the grid of NMOS tube MN3 and drain interconnection.
Described active attenuator comprises a PMOS MP3, two NPN type triode QN1 and QN2, two PNP type triode QP3 and QP4, five resistance R3, R4, R5, R6 and R7; The source electrode of PMOS MP3 meets supply voltage VDD, and its grid connects the grid of PMOS MP1 and MP2 in prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 sequentially passes through resistance R3 and R6 ground connection GND on the one hand, is connect the emitter of PNP type triode QP3 on the other hand by resistance R4; The base stage of PNP type triode QP3 is by resistance R6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of PNP type triode QP4 by resistance R5, the base stage of PNP type triode QP4 meets the second input signal VMULT by resistance R7, the grounded collector GND of PNP type triode QP3 and QP4.
Described second level differential amplifier comprises three PNP type triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS tube MN4 also comprises two resistance R8 and R9; The emitter of PNP type triode QP5 meets supply voltage VDD by resistance R8, the emitter of PNP type triode QP6 meets supply voltage VDD by resistance R9, the base stage interconnection of PNP type triode QP5 and QP6, the collector electrode of PNP type triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of PNP type triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of PNP type triode QP9 connects the base stage of PNP type triode QP5 and QP6, and its base stage connects the collector electrode of PNP type triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 connects the emitter of NPN type triode QN1 in active attenuator, and the base stage of NPN type triode QN4 connects the emitter of NPN type triode QN2 in active attenuator; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS tube MN4 jointly, and the grid of NMOS tube MN4 connects the grid of NMOS tube MN3 in prime differential amplifier, the source ground GND of NMOS tube MN4.
The output circuit that described current signal is converted into voltage signal comprises three PNP type triode QP7, QP8 and QP10, and three resistance R11, R12 and R13 also comprise a filter capacitor CL, the emitter of PNP type triode QP7 meets supply voltage VDD by resistance R11, the emitter of PNP type triode QP8 meets supply voltage VDD by resistance R12, the base stage interconnection of PNP type triode QP7 and QP8, the base stage of PNP type triode QP8 and collector electrode interconnect and connect the emitter of PNP type triode QP10, the base stage of PNP type triode QP10 connects the collector electrode of PNP type triode QP6 in the collector electrode of PNP type triode QP7 and second level differential amplifier, the collector electrode of PNP type triode QP10 passes through the parallel circuits ground connection GND of resistance R13 and filter capacitor CL, the collector electrode of PNP type triode QP10 exports the output signal VOUT of whole analog multiplier.
Circuit working mechanism of the present invention is as follows:
In module one (prime differential amplifier), PNP type triode QP1 and QP2 forms a differential pair, and PMOS MP2 mirror image MP1 electric current, provide differential pair current offset, resistance R1 and R2 is as the load of differential pair.QP1 and QP2 is identical triode, V cOMP-V b> 0, according to derivation, nMOS tube MN1 and MN2 forms current mirror, therefore I c2-I c1=I 1.
Multiplier is normally worked, and two applied signal voltages must be less than 2V t, greatly will reduce input voltage range like this, also just greatly limit circuit application.In order to expand the input range of input voltage, input voltage must be carried out linear attenuation, the input voltage after decay being met and is less than 2V t, thus can multiplication function be realized.Therefore, a voltage attenuation circuit is added at another input of multiplier.Voltage attenuation circuit is as shown in module in Fig. 3 two (active attenuator).QN1 and QN2 is just the same for NPN type triode, and PNP type triode QP3 and QP4 is also just the same, and the electric current of PMOS MP3 mirror-image constant flow source I provides current offset, the equal (R of resistance of resistance R4 and R5 for circuit 4=R 5), the relational expression of the first input signal VCOMP and output voltage Vid is: arrangement can obtain: can find out thus, as long as adjust the value of R4 or I, just can obtain input voltage and well decay.Add resistance R3 and negative feedback is introduced to the active attenuation of voltage, well improve the linearity of voltage attenuation circuit.
Equal (the R of resistance of resistance R8 and R9 in module three (second level differential amplifier) 8=R 9), PNP type triode QP5 and QP6 is just the same, and the two and QP9 form β helper structure, reduces the impact of β.NPN type triode QN3 and QN4 is also just the same, the electric current of MN3 in NMOS tube MN4 mirror module one (prime differential amplifier), I eE=I 1, provide tail current to be biased to cascode differential pair, and V id> 0, in like manner, and I c4-I c3=I 2.
In module four (current signal is converted into the output circuit of voltage signal), the collector current of PNP type triode QP8 mirror image QP7, the electric current flowing through QP10 collector electrode is approximately equal to I c8, i.e. I c8=I c7=I 2, and V oUT=I c8r 13.
In sum, arrangement obtains the size of suitable adjustment R4, I2, I3 can obtain suitable output voltage gain, and the negative feedback that the present invention adopts, β helper structure, load resistance reduces the nonlinearity erron of multiplier all greatly.
Those of ordinary skill in the art will appreciate that, embodiment described here is to help reader understanding's principle of the present invention, should be understood to that the protection range invented is not limited to so special statement and embodiment.Everyly make various possible equivalent replacement or change according to foregoing description, be all considered to belong to the protection range of claim of the present invention.

Claims (1)

1. the analog multiplier for Active PFC chip, comprise module one, module two, module three, module four, wherein module one is prime differential amplifier, module two is active attenuator, module three is second level differential amplifier, and module four is converted into the output circuit of voltage signal for current signal;
Described prime differential amplifier comprises two PMOS MP1 and MP2, three NMOS tube MN1, MN2 and MN3, crossing current source I, two resistance R1 and R2, and two PNP type triode QP1 and QP2; The source electrode of PMOS MP1 and MP2 meets supply voltage VDD, its gate interconnection; The grid of PMOS MP1 and drain interconnection, and by constant-current source I ground connection GND; The drain electrode of PMOS MP2 connects the emitter of PNP type triode QP1 on the one hand by resistance R1, connect the emitter of PNP type triode QP2 on the other hand by resistance R2; The base stage of PNP type triode QP1 inputs the first input signal VCOMP, the base stage input offset voltage VB of PNP type triode QP2; The source ground GND of NMOS tube MN1, MN2 and MN3, the gate interconnection of NMOS tube MN1 and MN2, the grid of NMOS tube MN1 and drain interconnection also connect the collector electrode of PNP type triode QP1, the drain electrode of NMOS tube MN2 and MN3 connects the collector electrode of PNP type triode QP2, the grid of NMOS tube MN3 and drain interconnection;
Described active attenuator comprises a PMOS MP3, two NPN type triode QN1 and QN2, two PNP type triode QP3 and QP4, five resistance R3, R4, R5, R6 and R7; The source electrode of PMOS MP3 meets supply voltage VDD, and its grid connects the grid of PMOS MP1 and MP2 in prime differential amplifier, and its drain electrode connects base stage and the collector electrode of two NPN type triode QN1 and QN2 simultaneously; The emitter of NPN type triode QN1 sequentially passes through resistance R3 and R6 ground connection GND on the one hand, is connect the emitter of PNP type triode QP3 on the other hand by resistance R4; The base stage of PNP type triode QP3 is by resistance R6 ground connection GND; The emitter of NPN type triode QN2 connects the emitter of PNP type triode QP4 by resistance R5, the base stage of PNP type triode QP4 meets the second input signal VMULT by resistance R7, the grounded collector GND of PNP type triode QP3 and QP4;
Described second level differential amplifier comprises three PNP type triode QP5, QP6 and QP9, two NPN type triode QN3 and QN4, and a NMOS tube MN4 also comprises two resistance R8 and R9; The emitter of PNP type triode QP5 meets supply voltage VDD by resistance R8, the emitter of PNP type triode QP6 meets supply voltage VDD by resistance R9, the base stage interconnection of PNP type triode QP5 and QP6, the collector electrode of PNP type triode QP5 connects the collector electrode of NPN type triode QN3, and the collector electrode of PNP type triode QP6 connects the collector electrode of NPN type triode QN4; The emitter of PNP type triode QP9 connects the base stage of PNP type triode QP5 and QP6, and its base stage connects the collector electrode of PNP type triode QP5 and NPN type triode QN3, its grounded collector GND; The base stage of NPN type triode QN3 connects the emitter of NPN type triode QN1 in active attenuator, and the base stage of NPN type triode QN4 connects the emitter of NPN type triode QN2 in active attenuator; The emitter of NPN type triode QN3 and QN4 connects the drain electrode of NMOS tube MN4 jointly, and the grid of NMOS tube MN4 connects the grid of NMOS tube MN3 in prime differential amplifier, the source ground GND of NMOS tube MN4;
The output circuit that described current signal is converted into voltage signal comprises three PNP type triode QP7, QP8 and QP10, and three resistance R11, R12 and R13 also comprise a filter capacitor CL, the emitter of PNP type triode QP7 meets supply voltage VDD by resistance R11, the emitter of PNP type triode QP8 meets supply voltage VDD by resistance R12, the base stage interconnection of PNP type triode QP7 and QP8, the base stage of PNP type triode QP8 and collector electrode interconnect and connect the emitter of PNP type triode QP10, the base stage of PNP type triode QP10 connects the collector electrode of PNP type triode QP6 in the collector electrode of PNP type triode QP7 and second level differential amplifier, the collector electrode of PNP type triode QP10 passes through the parallel circuits ground connection GND of resistance R13 and filter capacitor CL, the collector electrode of PNP type triode QP10 exports the output signal VOUT of whole analog multiplier.
CN201310080944.XA 2013-03-14 2013-03-14 A kind of analog multiplier for Active PFC chip Expired - Fee Related CN103199852B (en)

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CN105991127B (en) 2015-01-27 2018-11-13 意瑞半导体（上海）有限公司 Circuit of power factor correction and multiplier
CN107092297B (en) * 2017-06-13 2019-04-16 成都芯进电子有限公司 Second order compensation band-gap reference circuit for signal amplifier
CN211653633U (en) * 2019-07-08 2020-10-09 神亚科技股份有限公司 Multiplier device
CN114285385B (en) * 2022-02-21 2022-06-03 成都芯翼科技有限公司 Offset circuit of operational amplifier input current

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