CN103199540B - Low-voltage reactive compensation thyristor switch capacitor compensation device and compensation method thereof - Google Patents

Abstract

The invention relates to a low-voltage reactive compensation thyristor switch capacitor compensation device and a compensation method thereof. The compensation device comprises a sampling module, a calculating module, a searching module and a control module, wherein the sampling module is used for sampling current and voltage on a low-voltage bus to acquire the sampled current and the sampled voltage in the Kth time and the (K+1)th time, the K and the K+1 are sampling points for current and voltage, the calculating module is used for calculating compensated reactive power according to the sampled current and the sampled voltage in the Kth time and the (K+1)th time, the searching module is used for searching the best compensation capacitor assembly switch in a circulation mode according to the reactive power, the control module is used for outputting at least one switch electric level control signal to control a corresponding thyristor switch to be on according to the best compensation capacitor assembly, a corresponding compensation capacitor is communicated with the low-voltage bus, the best compensation capacitor assembly is communicated with the low-voltage bus, and the purpose of compensating reactive power of the low-voltage bus is achieved. The low-voltage reactive compensation thyristor switch capacitor compensation device has the advantages of being quick in response. The invention further relates to the compensation method of the compensation device.

Description

Low-pressure reactive compensation thyristor switch capacitor compensation device and compensation method thereof

Technical field

The present invention relates to reactive compensation controlling device and compensating control method thereof, particularly relate to low-pressure reactive compensation thyristor switch capacitor compensation device and compensation method thereof.

Background technology

Traditional TSC(thyristor series capacitor) the idle algorithmic method of reactive compensation system still rests on early stage root mean square algorithm, advanced any use Phase-shifting algorithm method, in recent years also have and adopt Fu formula algorithm, and these algorithmic methods at least all need a cycle and algorithm is complicated, take control system resource many, therefore the response time is slow, and under idle frequent sudden change environment, compensation speed does not reach requirement (as arc light welding machine etc.).In order to improve the TSC(thyristor series capacitor that response speed has) controller often adopts expensive DSP control chip and high-end 16 or 32 single-chip microcomputers to design TSC(thyristor series capacitor) controller, turn increase cost and maintenance difficulties like this and manufacture difficulty.

Summary of the invention

In view of this, the present invention is necessary to provide preferably low-pressure reactive compensation thyristor switch capacitor compensation device and the compensation method thereof of a kind of response speed.

The present invention is achieved in that a kind of low-pressure reactive compensation thyristor switch capacitor compensation device, and it is applied in low-pressure reactive compensation thyristor series capacitor bucking-out system, and this bucking-out system comprises:

The idle algorithmic controller of two sampled points, it comprises current sample input, voltage sample input and multiple switching level output end, wherein, current sample input and low-voltage bus bar are electrically connected and the electric current of this low-voltage bus bar of sampling, and voltage sample input and low-voltage bus bar are electrically connected and the voltage of this low-voltage bus bar of sampling;

Multiple thyristor switch, each thyristor switch comprises control end, first input end, the second input, the first output and the second output, wherein, this control end is electrically connected at this switching level output end, and this first, second input is all electrically connected at this low-voltage bus bar;

Multiple choke, its one end is electrically connected at multiple second output respectively;

Multiple building-out capacitor, its one end is electrically connected the other end of the plurality of choke respectively, and is also electrically connected at multiple first output respectively, the other end electrical ground of the plurality of building-out capacitor;

Wherein, this compensation arrangement is embedded in the idle algorithmic controller of this two sampled point, and this compensation arrangement comprises:

Sampling module, its electric current, voltage on low-voltage bus bar of sampling, obtain the K time and the K+1 time sampled voltage, electric current, wherein, K and K+1 refers to the sampled point of before and after voltage and current twice;

Computing module, it is for calculating according to the K time and the K+1 time sampled voltage, galvanometer the idle amount needing to compensate;

Search module, it is for the building-out capacitor combination switching according to this idle amount circulation searching the best;

Control module, it combines for the building-out capacitor according to the best, export the conducting that at least one switching level controling signal controls corresponding thyristor switch, corresponding building-out capacitor is communicated with low-voltage bus bar, realize best building-out capacitor combination to be communicated with low-voltage bus bar, reach the object compensating the idle amount of low-voltage bus bar.

As the further improvement of such scheme, this computing module also comprises:

Definition module, it is u=U for defining voltage and current expression formula _msin ω t, i=I _msin (ω t-θ), then the K time and the K+1 time sampled voltage, electric current are respectively u _k=U _msin ω t _k, i _k=I _msin (ω t _k-θ); u _k+1=U _msin ω t _k+1=U _msin (ω t _k+ ω T _s), i _k+1=I _msin (ω t _k+1-θ)=I _msin (ω t _k+ ω T _s-θ);

Be multiplied module, and it is for by mutually multiplied with the K+1 time sample rate current for the K time sampled voltage $u_k{i}_{k+1}=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ , also for by mutually multiplied with the K time sample rate current for the K+1 time sampled voltage: $u_{k+1}{i}_k=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ ；

Cancellation module, it is for by this cancellation of two phase multipliers and t _kcontinuous item, obtains: $U_m{I}_m\cos \mathrm{\θ}=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-(u_k{i}_{k+1}+u_{k+1}{i}_k)\cos \mathrm{\ω}{T}_S}{{\sin }^2\mathrm{\ω}{T}_s}$ (1 formula), $U_m{I}_m\sin \mathrm{\θ}=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (2 formula);

Equivalent modules, it is for being P=U according to the single-phase active power of electrical network _mi _mcos θ, reactive power is Q=U _mi _msin θ, is write as (1 formula) and (2 formula) equivalence: (3 formula), $Q=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (4 formula);

Two sampled points calculate idle module, and it is for according to ω T _sduring=pi/2, cos ω T _s=0, sin ω T _s=1, will gain merit with idle computing formula is that (3 formula) and (4 formula) just becomes: P=u _ki _k+ u _k+1i _k+1, Q=u _ki _k+1-u _k+1i _k(5 formula), wherein, P is active power, and Q is that reactive power is the idle amount needing to compensate.

The present invention also provides the compensation method of a kind of low-pressure reactive compensation thyristor series capacitor, and it is applied in low-pressure reactive compensation thyristor series capacitor bucking-out system, and this bucking-out system comprises:

The idle algorithmic controller of two sampled points, it comprises current sample input, voltage sample input and multiple switching level output end, wherein, current sample input and low-voltage bus bar are electrically connected and the electric current of this low-voltage bus bar of sampling, and voltage sample input and low-voltage bus bar are electrically connected and the voltage of this low-voltage bus bar of sampling;

Multiple thyristor switch, each thyristor switch comprises control end, first input end, the second input, the first output and the second output, wherein, this control end is electrically connected at this switching level output end, and this first, second input is all electrically connected at this low-voltage bus bar;

Multiple choke, its one end is electrically connected at multiple second output respectively;

Multiple building-out capacitor, its one end is electrically connected the other end of the plurality of choke respectively, and is also electrically connected at multiple first output respectively, the other end electrical ground of the plurality of building-out capacitor;

Wherein, this compensation method comprises the following steps:

Electric current, voltage on sampling low-voltage bus bar, obtain the K time and the K+1 time sampled voltage, electric current, wherein, K and K+1 refers to the sampled point of before and after voltage and current twice;

The idle amount needing to compensate is calculated according to the K time and the K+1 time sampled voltage, galvanometer;

According to the building-out capacitor combination switching of this idle amount circulation searching the best;

Building-out capacitor according to the best combines, export the conducting that at least one switching level controling signal controls corresponding thyristor switch, corresponding building-out capacitor is communicated with low-voltage bus bar, realizes best building-out capacitor combination and be communicated with low-voltage bus bar, reach the object compensating the idle amount of low-voltage bus bar.

As the further improvement of such scheme, this calculation procedure is further comprising the steps of:

Definition voltage and current expression formula is u=U _msin ω t, i=I _msin (ω t-θ), then the K time and the K+1 time sampled voltage, electric current are respectively u _k=U _msin ω t _k, i _k=I _msin (ω t _k-θ); u _k+1=U _msin ω t _k+1=U _msin (ω t _k+ ω T _s), i _k+1=I _msin (ω t _k+1-θ)=I _msin (ω t _k+ ω T _s-θ);

By mutually multiplied with the K+1 time sample rate current for the K time sampled voltage $u_k{i}_{k+1}=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ , also for by mutually multiplied with the K time sample rate current for the K+1 time sampled voltage: $u_{k+1}{i}_k=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ ；

By this cancellation of two phase multipliers and t _kcontinuous item, obtains: $U_m{I}_m\cos \mathrm{\θ}=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-(u_k{i}_{k+1}+u_{k+1}{i}_k)\cos \mathrm{\ω}{T}_S}{{\sin }^2\mathrm{\ω}{T}_s}$ (1 formula), $U_m{I}_m\sin \mathrm{\θ}=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (2 formula);

P=U according to the single-phase active power of electrical network _mi _mcos θ, reactive power is Q=U _mi _msin θ, is write as (1 formula) and (2 formula) equivalence: (3 formula), $Q=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (4 formula);

According to ω T _sduring=pi/2, cos ω T _s=0, sin ω T _s=1, will gain merit with idle computing formula is that (3 formula) and (4 formula) just becomes: P=u _ki _k+ u _k+1i _k+1, Q=u _ki _k+1-u _k+1i _k(5 formula), wherein, P is active power, and Q is that reactive power is the idle amount needing to compensate.

The present invention can implementation algorithm and control response time within a cycle, improve TSC(thyristor series capacitor) controller cost performance and reactive compensation system dynamic response time and stability.

Accompanying drawing explanation

The structural representation of the low-pressure reactive compensation thyristor series capacitor bucking-out system of the low-pressure reactive compensation thyristor switch capacitor compensation device that Fig. 1 provides for application better embodiment of the present invention.

Fig. 2 is the structural representation of the idle algorithmic controller of two sampled points of Fig. 1 mesolow reactive power compensation thyristor series capacitor bucking-out system.

Fig. 3 is the structural representation of the thyristor switch of Fig. 1 mesolow reactive power compensation thyristor series capacitor bucking-out system.

The pointer definition figure of the low-pressure reactive compensation thyristor switch capacitor compensation device that Fig. 4 provides for better embodiment of the present invention.

The sampling curve schematic diagram of the low-pressure reactive compensation thyristor switch capacitor compensation device that Fig. 5 provides for better embodiment of the present invention.

Primary symbols illustrates: the idle algorithmic controller 1 of two sampled points, thyristor switch 2, choke 3, building-out capacitor 4, low-voltage bus bar 5, voltage and current sampling circuit 11, modulus shaping circuit 12, processor 13, analog-to-digital conversion interface 14, HMI interface 15, DO interface 16, synchronous circuit 21, bidirectional triode thyristor 22, zero crossing circuitry 210, light-emitting diode 211, trigger controllable silicon 212.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Refer to Fig. 1, the structural representation of the low-pressure reactive compensation thyristor series capacitor bucking-out system of its low-pressure reactive compensation thyristor switch capacitor compensation device provided for application better embodiment of the present invention, low-pressure reactive compensation thyristor series capacitor bucking-out system comprises the idle algorithmic controller 1 of two sampled points, thyristor switch 2, choke 3, building-out capacitor 4.The quantity of thyristor switch 2, choke 3, building-out capacitor 4 is corresponding, can be multiple, in present embodiment, all be illustrated for one for convenience of explanation.

The idle algorithmic controller 1 of two sampled points comprises current sample input, voltage sample input and switching level output end, wherein, current sample input and low-voltage bus bar 5 are electrically connected and the electric current of this low-voltage bus bar 5 of sampling, and voltage sample input and low-voltage bus bar 5 are electrically connected and the voltage of this low-voltage bus bar 5 of sampling.

Incorporated by reference to Fig. 2, the idle algorithmic controller 1 of two sampled points comprises voltage and current sampling circuit 11, modulus shaping circuit 12(AD shaping circuit) and processor 13.This processor 13 is provided with analog-to-digital conversion interface 14(AD and changes 12Bit), HMI interface 15 and DO interface 16.This voltage is connected with low-voltage bus bar 5 with one end of current sampling circuit 11, and form current sample input, voltage sample input, the other end of this voltage and current sampling circuit 11 is electrically connected at this analog-to-digital conversion rear port 14 via this modulus shaping circuit 12.This DO interface 16 is electrically connected at thyristor switch 2, and form switching level output end, when thyristor switch 2 is multiple, this DO interface 16 just has multiple switching level output end to be connected with multiple thyristor switch 2.HMI interface 15 is menu display and input through keyboard mainly, plays the effect of man-machine interaction.

Thyristor switch 2 comprises control end, first input end, the second input, the first output and the second output, and wherein, this control end is electrically connected at this switching level output end, and this first, second input is all electrically connected at this low-voltage bus bar 5.

One end of choke 3 is electrically connected at this second output; One end of building-out capacitor 4 is electrically connected the other end of this choke 3, and is also electrically connected at this first output, the other end electrical ground of this building-out capacitor 4.

In the present embodiment, this thyristor switch 2 comprises synchronous circuit 21 and bidirectional triode thyristor 22, this control end, this first input end, the first output are separately positioned on this synchronous circuit 21, this synchronous circuit 21 is also electrically connected at the control pole of this bidirectional triode thyristor 22, and this second input and this second output are respectively the constrained input of this bidirectional triode thyristor 22.

This synchronous circuit 21 can adopt zero cross fired chip, as zero cross fired chip MOC3083.Equivalent electric circuit design can certainly be adopted, as shown in Figure 3.As in Fig. 3, this synchronous circuit 21 comprises zero crossing circuitry 210, light-emitting diode 211 and triggers controllable silicon 212.The input of this zero crossing circuitry 210, output and sampling be electrically connected at respectively this triggering controllable silicon 212 input, control pole and output, the anode of this light-emitting diode 211 is electrically connected at power supply (not shown), negative electrode and this switching level output end of this light-emitting diode 211 are electrically connected, this light-emitting diode 211 triggers this triggering controllable silicon 212 when luminescence, this triggering controllable silicon 212 be input as this first input end, the output of this triggering controllable silicon 212 is this first output and is also electrically connected at the control pole of this bidirectional triode thyristor 22.

This compensation arrangement of the present invention is be embedded in the software program in the idle algorithmic controller 1 of this two sampled point, this compensation arrangement comprises: sampling module, its electric current, voltage for sampling on low-voltage bus bar 5, obtain the K time and the K+1 time sampled voltage, electric current, wherein, K and K+1 refers to the sampled point of before and after voltage and current twice; Computing module, it is for calculating according to the K time and the K+1 time sampled voltage, galvanometer the idle amount needing to compensate; Search module, it is for combining switching according to the building-out capacitor 4 of this idle amount circulation searching the best; Control module, it combines for the building-out capacitor 4 according to the best, export the conducting that at least one switching level controling signal controls corresponding thyristor switch 2, corresponding building-out capacitor 4 is communicated with low-voltage bus bar 5, realize best building-out capacitor 4 combination to be communicated with low-voltage bus bar 5, reach the object compensating the idle amount of low-voltage bus bar 5.

At present in quality of power supply Arithmetic for Reactive Power Compensation, adopt the algorithm of compensating reactive power to have the instantaneous reactive algorithm etc. of root mean square formula algorithm, digital phase shift, Fu's formula algorithm (Fourior) and current trend, list the sampled point computing formula of these algorithms below respectively:

1), root mean square formula algorithm: $U=\sqrt{\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{U}_i^2\left(n\right)}$ ； $I=\sqrt{\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{I}_i^2\left(n\right)}$ ； $P=\frac{1}{N}\underset{n=1}{\overset{N}{\mathrm{\Σ}}}{U}_i\left(n\right)I_i\left(n\right)$ ；S=UI； 。This algorithm resource of occupying consuming time is many, has error, seldom uses in reality.

2), Phase-shifting algorithm: .The i.e. voltage of delayed 90 ° and the product of K primary current.Algorithm conventional at present, sampling number is the integral multiple of 4, at least one cycle.

3), Fu's formula algorithm: $U_{\mathrm{RE}}\left(K\right)=\frac{1}{N}2\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}U\left(i\right)\sin \frac{2\mathrm{kin}}{N}$ ； $U_{\mathrm{IM}}\left(K\right)=\frac{1}{N}2\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}U\left(i\right)\cos \frac{2\mathrm{kin}}{N}$ ； $I_{\mathrm{RE}}\left(K\right)=\frac{1}{N}2\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}I\left(i\right)\sin \frac{2\mathrm{kin}}{N}$ ； $I_{\mathrm{IM}}\left(K\right)=\frac{1}{N}2\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}I\left(i\right)\cos \frac{2\mathrm{kin}}{N}$ ； $Q_k=\frac{2}{N^2}(U_{\mathrm{IM}}\left(K\right)*I_{\mathrm{RE}}\left(K\right)-U_{\mathrm{RE}}\left(K\right)*I_{\mathrm{IM}}\left(K\right))$ ； $Q=\underset{k=0}{\overset{N/2}{\mathrm{\Σ}}}{Q}_k$ 。Very loaded down with trivial details, take a lot of resource, active power filtering (APF) and reacance generator (SVG) have application.

4), instantaneous reactive algorithm: $Q=\frac{1}{\sqrt{3}}[(E_b-E_c)*I_a+(E_c-E_a)*I_b+(E_a-E_b)*I_c]$ ?。Wherein E _a, E _b, E _cbe through CLAK-PARK and convert the value obtained, reacance generator (SVG) has application.

Low-pressure reactive compensation thyristor switch capacitor compensation device of the present invention adopts the idle algorithm of two sampled points in the idle algorithmic controller 1:Q=u of two sampled points _ki _k+1-u _k+1i _k.By idle (Q) listed above computing formula, can see that the idle algorithm of two sampled points calculates brief and concise, and the computing formula meaning understands, voltage (U) and electric current (I) K and K+1 that drop just refers to the sampled point of before and after voltage and current twice.

One, the step of two sampled point algorithms is as follows:

Definition voltage and current expression formula is u=U _msin ω t; i=I _msin (ω t-θ); Then the K time and the K+1 time sampled voltage electric current are respectively u _k=U _msin ω t _k; i _k=I _msin (ω t _k-θ); u _k+1=U _msin ω t _k+1=U _msin (ω t _k+ ω T _s); i _k+1=I _msin (ω t _k+1-θ)=I _msin (ω t _k+ ω T _s-θ);

Then by mutually multiplied with the K+1 time sample rate current for the K time sampled voltage: $u_k{i}_{k+1}=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ ; By mutually multiplied with the K time sample rate current for the K+1 time sampled voltage: $u_{k+1}{i}_k=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})]$ ；

By this cancellation of two phase multipliers and t _kcontinuous item, has:

$U_m{I}_m\cos \mathrm{\θ}=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-(u_k{i}_{k+1}+u_{k+1}{i}_k)\cos \mathrm{\ω}{T}_S}{{\sin }^2\mathrm{\ω}{T}_s}$ (1 formula);

$U_m{I}_m\sin \mathrm{\θ}=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (2 formula);

By with up conversion, the single-phase active power of electrical network is P=U _micos θ; Reactive power is Q=U _mi _msin θ.So (1 formula) and (2 formula) can be write as:

$P=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-\left({u_k{i}_{k+1}+u}_{k+1}{i}_k\right)\cos \mathrm{\ω}{T}_S}{{\sin }^2\mathrm{\ω}{T}_s}$ (3 formula); $Q=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2\mathrm{\ω}{T}_s}$ (4 formula).

In order to make calculating more simple, make ω T _sduring=pi/2, such cos ω T _s=0, sin ω T _s=1, meritorious and idle computing formula i.e. (3 formula) and (4 formula) just becomes:

P=u _ki _k+ u _k+1i _k+1; Q=u _ki _k+1-u _k+1i _k(5 formula).(5 formula) is exactly that final two sampled points calculate idle algorithmic formula like this.

In sum, the idle algorithmic controller 1 of two sampled points is according to the K time and the K+1 time sampled voltage, electric current, just can calculate reactive power compensation amount Q, the idle algorithmic controller of two sampled points 1 controls the output of one or more switching level and sends level signal, control the conducting of one or more building-out capacitor 4, realize corresponding reactive power compensation amount Q.

Two, the software simulating of the idle algorithm of two sampled points:

In order to accomplish the computational methods of (5 formula), only current sampled point and the sampled point in 1/4 cycle 2 need be carried out calculating in practical application, this also easily realizes in practice.A kind of concrete methods of realizing program is as follows below: define the array SampPoint [50] that is deposited sampled data, this is 24 sub-samplings, and sampled point is 25, deposits the data of 2 cycles, and sampled point is exactly 50, so array length is 50.Defining one, two pointers is again the interlude that current sampling point pointer CurrentPointPtr points to sampling array SampPiont [50], and one is that sampling array pointer SampPointPtr points to sampling array.As shown in Figure 4.

Each sampling data SampPointPtr and CurentPointPtr pointer value increase by one, and 24 later pointer values of sampling revert to original position.When calculating idle amount (Q), the array value utilizing current CurrentPointPtr to point to, moves forward 24/2=6 with CurrentPointPtr-6 and adopts the value a little pointed to calculate.For a sinusoidal cycle with 24 times sampling, move forward 6 sampled points be just in time phase shift pi/2 (90 °) as shown in Figure 5.

Below just for the A phase single supply in a three phase network, sample 24 times, by the electric current and voltage data of sampling stored in SampPoint array, suppose first sampled voltage, then sample rate current, represent voltage with U, I represents electric current, then array is deposited 24 sampled datas it is as shown in the table:

U0

I0

U1

I1

。。。。。。。

U24

I24

U0, I0 represent first time sampled value, and U1, I1 represent second time sampled value ... .. U24, I24 represent the 24th sampled value.

The C code realized by this array store data form is as follows:

Because the voltage in program (U) is the result that maximum is multiplied with electric current (I), and idle (Q) in normalized form is voltage (U) is multiplied with the effective value of electric current (I), so idle (the Q)=Q/2 of actual value, thus calculates the idle amount of current electric grid.

The present invention is to TSC(thyristor series capacitor) reactive power compensator principle and realization be further detailed.

The idle algorithmic controller 1 of two sampled points is by the current-voltage sampling on low-voltage bus bar 5, the idle amount needing to compensate is calculated through the idle algorithmic controller of two sampled points 1, the building-out capacitor 4 of circulation searching the best combines switching, then the idle algorithmic controller 1 of two sampled points exports the conducting of switching Automatic level control thyristor switch 2, compensation building-out capacitor 4 be communicated with low-voltage bus bar 5 or disconnect, reaching the object compensating the idle amount of low-voltage bus bar 5.Introduce TSC(thyristor series capacitor in detail below) System Working Principle and structure.

1, thyristor switch and choke and capacitive part

Thyristor switch 2, choke 3 and building-out capacitor 4 are TSC(thyristor series capacitors) active part of bucking-out system, Main Function is to provide the reactive capability that network system needs to compensate.Thyristor switch 2 is a kind of operating passing zero switches, the triggering level height sent according to the idle algorithmic controller of two sampled points is on network wave zero crossing place throws or excision, choke contains that switching is instantaneously to the rush of current of building-out capacitor 4, and building-out capacitor 4 is to provide compensation capacity.

Wherein, thyristor switch 2 comprises zero cross fired chip MOC3083(red boxes) and the bidirectional triode thyristor 22 of Xi Menkang.The operation principle of thyristor switch 2 is: inner triggering controllable silicon 212 two ends of zero cross fired chip (MOC3083) connect low-voltage bus bar terminal voltage and capacitance terminal voltage respectively and the zero crossing circuitry sampled voltage of inside also from the voltage at these two ends, such guarantee thyristor switch 2 controls triggering level and locates conducting or shutoff when receiving the signal that controller is sent at the zero point of voltage, avoids the impact of big current to electric capacity.

2, the idle algorithmic controller part of two sampled points

Voltage and current sampling circuit 11 form sample circuit primarily of current transformer and voltage transformer, instrument transformer all adopts current mode instrument transformer TV19E and TA12 of Yao Hua Dechang company, use TV19E sampled voltage signal, use TA12 sampled current signals, two instrument transformer input current scopes are 0-5MA, and exporting maximum voltage is 2.5v.AD shaping circuit is the signal output voltage lifting 2.5v of instrument transformer being become 0-5V, and to meet the parameter request of the inner AD of single-chip microcomputer, the main TL064 amplifier chip that uses completes this function.Processor 13 adopts the C8051F580 single-chip microcomputer of the SILICON company of 8 C51 kernels of low side, 12 bit A/D converters that AD conversion uses this single-chip microcomputer to carry.This single-chip microcomputer work clock is up to 50MHZ, sample frequency is up to 3MHZ, single-chip microcomputer completes the idle algorithm of two sampled points and calculates the current idle amount needing to compensate, then adopt circulation to select the method for electric capacity to carry out switching capacitance according to the current idle amount single-chip microcomputer calculated, reach the object that compensation network is idle.DO interface 16 module provides 18 road output ports altogether, have employed Darlington pipe UN2003 chip and provides interface to export, and export the voltage signal of 12V to improve driving force.HMI interface 15 module is menu display and input through keyboard mainly, plays the effect of man-machine interaction.

Whole two sampled point idle algorithmic controller design is controlling to compare with controller existing on market under quick and stable prerequisite have hardware simple and clear in a word, and software algorithm is simple, with low cost, the feature that cost performance is high.

Obviously, those skilled in the art can carry out various change and modification to low-pressure reactive compensation thyristor switch capacitor compensation device of the present invention and not depart from the spirit and scope of the present invention.Like this, if belong within the scope of the claims in the present invention and equivalent technologies thereof to these amendments of the present invention and modification, then the present invention is also intended to comprise these change and modification.

Claims (2)

1. a low-pressure reactive compensation thyristor switch capacitor compensation device, it is applied in low-pressure reactive compensation thyristor series capacitor bucking-out system, and this bucking-out system comprises:

The idle algorithmic controller of two sampled points, it comprises current sample input, voltage sample input and multiple switching level output end, wherein, current sample input and low-voltage bus bar are electrically connected and the electric current of this low-voltage bus bar of sampling, and voltage sample input and low-voltage bus bar are electrically connected and the voltage of this low-voltage bus bar of sampling;

Multiple thyristor switch, each thyristor switch comprises control end, first input end, the second input, the first output and the second output, wherein, this control end is electrically connected at this switching level output end, and this first, second input is all electrically connected at this low-voltage bus bar;

Multiple choke, its one end is electrically connected at multiple second output respectively;

Multiple building-out capacitor, its one end is electrically connected the other end of the plurality of choke respectively, and is also electrically connected at multiple first output respectively, the other end electrical ground of the plurality of building-out capacitor;

It is characterized in that, this compensation arrangement is embedded in the idle algorithmic controller of this two sampled point, and this compensation arrangement comprises:

Sampling module, its electric current, voltage on low-voltage bus bar of sampling, obtain the K time and the K+1 time sampled voltage, electric current, wherein, K and K+1 refers to the sampled point of before and after voltage and current twice;

Computing module, it is for calculating according to the K time and the K+1 time sampled voltage, galvanometer the idle amount needing to compensate;

Search module, it is for the building-out capacitor combination switching according to this idle amount circulation searching the best;

Control module, it combines for the building-out capacitor according to the best, export the conducting that at least one switching level controling signal controls corresponding thyristor switch, corresponding building-out capacitor is communicated with low-voltage bus bar, realize best building-out capacitor combination to be communicated with low-voltage bus bar, reach the object compensating the idle amount of low-voltage bus bar, this computing module also comprises:

Definition module, it is u=U for defining voltage and current expression formula _msin ω t, i=I _msin (ω t-θ), then the K time and the K+1 time sampled voltage, electric current are respectively u _k=U _msin ω t _k, i _k=I _msin (ω t _k-θ); u _k+1=U _msin ω t _k+1=U _msin (ω t _k+ ω T _s), i _k+1=I _msin (ω t _k+1-θ)=I _msin (ω t _k+ ω T _s-θ);

Be multiplied module, and it is for by mutually multiplied with the K+1 time sample rate current for the K time sampled voltage $u_k{i}_{k+1}=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})],$ Also for by mutually multiplied with the K time sample rate current for the K+1 time sampled voltage: $u_{k+1}{i}_k=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}+{\mathrm{\ωT}}_s)-\cos (2{\mathrm{\ωt}}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})];$

Cancellation module, it is for by this cancellation of two phase multipliers and t _kcontinuous item, obtains: $U_m{I}_m\cos \mathrm{\θ}=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-(u_k{i}_{k+1}+u_{k+1}{i}_k)\cos {\mathrm{\ωT}}_S}{{\sin }^2{\mathrm{\ωT}}_s}$ (1 formula), $U_m{I}_m\sin \mathrm{\θ}=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2{\mathrm{\ωT}}_s}$ (2 formula);

Equivalent modules, it is P=U for the single-phase active power according to electrical network _mi _mcos θ, reactive power is Q=U _mi _msin θ, is write as (1 formula) and (2 formula) equivalence: (3 formula), $Q=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2{\mathrm{\ωT}}_s}$ (4 formula);

Two sampled points calculate idle module, and it is for according to ω T _sduring=pi/2, cos ω T _s=0, sin ω T _s=1, will gain merit with idle computing formula is that (3 formula) and (4 formula) just becomes: P=u _ki _k+ u _k+1i _k+1, Q=u _ki _k+1-u _k+1i _k(5 formula), wherein, P is active power, and Q is that reactive power is the idle amount needing to compensate.

2. a low-pressure reactive compensation thyristor series capacitor compensation method, it is applied in low-pressure reactive compensation thyristor series capacitor bucking-out system, and this bucking-out system comprises the following steps:

The idle algorithmic controller of two sampled points, it comprises current sample input, voltage sample input and multiple switching level output end, wherein, current sample input and low-voltage bus bar are electrically connected and the electric current of this low-voltage bus bar of sampling, and voltage sample input and low-voltage bus bar are electrically connected and the voltage of this low-voltage bus bar of sampling;

Multiple thyristor switch, each thyristor switch comprises control end, first input end, the second input, the first output and the second output, wherein, this control end is electrically connected at this switching level output end, and this first, second input is all electrically connected at this low-voltage bus bar;

Multiple choke, its one end is electrically connected at multiple second output respectively;

Multiple building-out capacitor, its one end is electrically connected the other end of the plurality of choke respectively, and is also electrically connected at multiple first output respectively, the other end electrical ground of the plurality of building-out capacitor;

It is characterized in that, this compensation method comprises:

Electric current, voltage on sampling low-voltage bus bar, obtain the K time and the K+1 time sampled voltage, electric current, wherein, K and K+1 refers to the sampled point of before and after voltage and current twice;

The idle amount needing to compensate is calculated according to the K time and the K+1 time sampled voltage, galvanometer;

According to the building-out capacitor combination switching of this idle amount circulation searching the best;

Building-out capacitor according to the best combines, export the conducting that at least one switching level controling signal controls corresponding thyristor switch, corresponding building-out capacitor is communicated with low-voltage bus bar, realize best building-out capacitor combination to be communicated with low-voltage bus bar, reach the object compensating the idle amount of low-voltage bus bar, this calculation procedure is further comprising the steps of:

Definition voltage and current expression formula is u=U _msin ω t, i=I _msin (ω t-θ), then the K time and the K+1 time sampled voltage, electric current are respectively u _k=U _msin ω t _k, i _k=I _msin (ω t _k-θ); u _k+1=U _msin ω t _k+1=U _msin (ω t _k+ ω T _s), i _k+1=I _msin (ω t _k+1-θ)=I _msin (ω t _k+ ω T _s-θ);

By mutually multiplied with the K+1 time sample rate current for the K time sampled voltage $u_k{i}_{k+1}=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}-\mathrm{\ω}{T}_s)-\cos (2\mathrm{\ω}{t}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})],$ Also for by mutually multiplied with the K time sample rate current for the K+1 time sampled voltage: $u_{k+1}{i}_k=\frac{U_m{I}_m}{2}[\cos (\mathrm{\θ}+{\mathrm{\ωT}}_s)-\cos (2{\mathrm{\ωt}}_k+\mathrm{\ω}{T}_s-\mathrm{\θ})];$

By this cancellation of two phase multipliers and t _kcontinuous item, obtains: $U_m{I}_m\cos \mathrm{\θ}=\frac{u_k{i}_k+u_{k+1}{i}_{k+1}-(u_k{i}_{k+1}+u_{k+1}{i}_k)\cos {\mathrm{\ωT}}_S}{{\sin }^2{\mathrm{\ωT}}_s}$ (1 formula), $U_m{I}_m\sin \mathrm{\θ}=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2{\mathrm{\ωT}}_s}$ (2 formula);

Single-phase active power according to electrical network is P=U _mi _mcos θ, reactive power is Q=U _mi _msin θ, is write as (1 formula) and (2 formula) equivalence: (3 formula), $Q=\frac{u_k{i}_{k+1}-u_{k+1}{i}_k}{{\sin }^2{\mathrm{\ωT}}_s}$ (4 formula);

According to ω T _sduring=pi/2, cos ω T _s=0, sin ω T _s=1, will gain merit with idle computing formula is that (3 formula) and (4 formula) just becomes: P=u _ki _k+ u _k+1i _k+1, Q=u _ki _k+1-u _k+1i _k(5 formula), wherein, P is active power, and Q is that reactive power is the idle amount needing to compensate.