CN105281345A - Cascade connection seven-level static synchronous compensator based on LADRC and control method - Google Patents

Abstract

A cascade connection seven-level static synchronous compensator based on LADRC is characterized in that the cascade connection seven-level static synchronous compensator comprises a main circuit module, a DSP control module, a detecting module and an IGBT driving module; the control method of the cascade connection seven-level static synchronous compensator comprises: detecting, converting, comparing, producing and controlling signals; the advantages are that the structure is simple; the control is simple; the stability is good; and the control accuracy is high.

Description

Based on cascade seven level static synchronization compensator and the control method of LADRC

(1) technical field

The invention belongs to power system reactive power compensation field, relate to a kind of cascade seven level static synchronization compensator (STATCOM) of controlling based on LADRC (LinearActiveDisturbanceRejectionControl---linear active disturbance rejection controls) and control method.

(2) background technology

Power industry, as mainstay of the national economy industry, is the field of STATCOM extensive use.STATCOM can realize the object quickly and smoothly absorbing perception and capacitive reactive power in electric power system, and it has starting without advantages such as impacting, regulate continuously, respond fast, floor space is little.

Common STATCOM is existed that output harmonic wave content is large, switching device capacity and the problem such as electric pressure is limited.As improvement, cascade connection multi-level technical scheme can be used, this scheme decreases the output of harmonic wave by many level method, use cascade system simultaneously, reduce electric pressure and capacity requirement that single switch device bears, defining the modular construction being easy to control respectively in addition, is more perfect large capacity STATCOM solution.

Whether the control strategy of STATCOM directly affects the dynamic response of system and reactive power can be provided rapidly, continuously to support with systems stabilisation voltage.Mostly current control strategy is traditional PID control, and electric power system belongs to strong nonlinearity object, and thus its range of application will be very limited.As development and the extension of PID, automatic disturbance rejection controller (ADRC) is through having facts have proved that it still has good control precision under strong nonlinearity and uncertain large disturbances for many years, but ADRC technology is also faced with the problem that controling parameters is many, regulate complexity simultaneously.For the ease of field technician's debugging, thus promoted widely, LADRC arises at the historic moment, and it uses linear function to instead of the nonlinear function of ADRC.While obtaining same control effects, further simplify controling parameters, reduce the complexity of debugging.

(3) summary of the invention

The object of the present invention is to provide a kind of cascade seven level static synchronization compensator based on LADRC and control method, it adopts cascade seven electrical level inverter being applicable to large capacity STATCOM to be main circuit structure, and utilize high performance signal processor (DSP) and flexibly linear active disturbance rejection control technology to obtain high-precision control effects, substantially increase rapidity and the robustness of system, improve the reactive power compensation response speed of system to the full extent, ensure that the quality of power supply.

Technical scheme of the present invention: a kind of cascade seven level static synchronization compensator based on LADRC, is characterized in that it comprises main circuit module, DSP control module, detection module, IGBT drive module; Wherein said detection module input is connected with main circuit by current transformer (CT), and gather three-phase voltage, electric current, phase signal, its output is connected with DSP control module; Described DSP control module output connects IGBT drive module input; Described IGBT drive module output connects main circuit module.

Above-mentioned said main circuit module is often in series by three H-bridge unit, described H-bridge unit is formed in parallel by two brachium pontis I, II and a DC bus capacitor C, described brachium pontis I is in series by after IGBT pipe T1, T2 and diode D1, D2 respectively inverse parallel, and described brachium pontis II is in series by after IGBT pipe T3, T4 and diode D3, D4 respectively inverse parallel.

Above-mentioned said DSP control module by A/D sampling unit, Main Control Unit, external interface unit, extend out memory cell and form.Wherein said A/D sampling unit input is connected with detection module, and output signal is connected with Main Control Unit; Described Main Control Unit is connected with outside output interface unit; Described outside output interface unit is connected with IGBT drive module; And described Main Control Unit also with extend out memory cell and become in being bi-directionally connected.

The described high accuracy chip AD7705 being adopted sigma-delta A/D technology by the employing of A/D sampling unit with 16 A/D converters.

Described Main Control Unit adopts 32 of TI company production to be floating-point signal processor TMS320C28335.

Described external interface unit adopts transistor output photoelectric coupler TLP512.

The described memory cell that extends out adopts 512K, and the flash of 16 stores core SST39VF800.

Described detection module is made up of three-phase current on line side detecting unit, threephase load current detecting unit, DC voltage detecting unit, phase detection unit.Described three-phase current on line side detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described threephase load current detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described DC voltage detecting unit input is connected with main circuit module, and output is connected with DSP control module; Described phase detection unit is connected with main circuit module by phase-locked loop, and output is connected with DSP control module.

Described IGBT drive module is made up of triangular wave generating unit and comparator unit.Described triangular-wave generator unit output connects comparator unit; Described comparator unit input connects DSP control module simultaneously, and output connects main circuit module.

Described triangular-wave generator unit adopts high frequency accurate function signal generator chip MAX038.

Described comparator unit adopts four tunnels independently voltage comparator chip LM339.

Based on a control method for cascade seven level static synchronization compensator of LADRC, it is characterized in that it comprises the following steps:

(1) the i of the threephase load current detecting unit output of detection module _la, i _lb, i _lcenter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, produces idle instruction current i through Park Transformation _qref.

(2) the direct voltage U of each H-bridge unit of the DC voltage detecting unit output of detection module _dc1-U _dc6enter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, respectively with system dc side voltage setting value U _refafter relatively forming error signal, produce meritorious instruction current i through adjuster _dref.

(3) meritorious instruction current i _drefwith idle instruction current i _qrefafter carrying out LADRC algorithm process respectively through the Main Control Unit of DSP control module, form that STATCOM is meritorious, reactive voltage output instruction signal U _cd, U _cq.

(4) the system phase angle θ, the DC voltage set point U that are exported by the phase detection unit of detection module _ref, meritorious, idle command signal U _cd, U _cq, go out through the Main Control Unit mathematical computations of DSP control module the modulation ratio M and phase angle [alpha] that PWM exports, stored in the outside extension storage unit of DSP control module, and export three-phase PWM modulation signal via the external interface unit of DSP control module.

(5) PWM modulation signal enters the comparator unit of IGBT drive module, after comparing, produces main circuit IGBT drive singal, by the size regulating Duty ratio control STATCOM to export reactive current with the triangular wave generating unit of IGBT drive module.Thus carry out the control of reactive power compensating.

Operation principle of the present invention:

(1) cascade 7 level static synchronization compensator main circuit module design, is illustrated in figure 2 cascade 7 level static synchronization compensator main circuit topological structure figure.It is often in series by three H-bridge unit, described H-bridge unit is formed in parallel by two brachium pontis I, II and a DC bus capacitor C, described brachium pontis I is in series by after IGBT pipe T1, T2 and diode D1, D2 respectively inverse parallel, and described brachium pontis II is in series by after IGBT pipe T3, T4 and diode D3, D4 respectively inverse parallel.Be illustrated in figure 3 the structure chart of one of them H-bridge unit.The IGBT of the same brachium pontis of synchronization can not conducting simultaneously, otherwise DC bus capacitor will occur the situation of short circuit.Control in the drive singal of the IGBT of same brachium pontis, T1, T2 triggering signal is contrary, and T3, T4 triggering signal is contrary, adds the afterflow effect of diode, overall power unit has three major types 8 kinds of operating states, and three classes comprise power stage, afterflow, idle feedback states.The IGBT conducting at power stage and diagonal angle, by energy inversion to AC; Idle feedback is, by two anti-paralleled diodes at diagonal angle, the quadergy of AC is fed back to DC side; Afterflow conducting be an IGBT and feedback diode, this process does not have energy transferring.

(2) DSP control module circuit design: adopt 2 to be floating-point signal processor TMS320C28335, be convenient to the realization of detection and load control algorithm; A/D sampling A/D chip adopts 16 A/D converters to adopt the high accuracy chip AD7705 of sigma-delta A/D technology, can at a high speed, gather the signal such as three-phase current, system phase accurately; External interface adopts photoelectrical coupler TLP512, on the basis of protection governor circuit, well controls ancillary equipment; Extend out memory cell and adopt 512K, the flash of 16 stores core SST39VF800 and stores the key results detecting electric current, phase signal and control algolithm, in order to calling.

(3) linear active disturbance rejection Controller gain variations: CONTROLLER DESIGN will be started with from STATCOM Mathematical Modeling.According to instantaneous power theory, the instantaneous active that STATCOM and electrical network exchange and reactive power are:

$\left\{\begin{array}{c}p\left(t\right)=u_{sd}\left(t\right)i_d\left(t\right)+u_{sq}\left(t\right)i_q\left(t\right)\\ q\left(t\right)=u_{sq}\left(t\right)i_d\left(t\right)-u_{sd}\left(t\right)i_q\left(t\right)\end{array}\right.$

By $\left[\begin{array}{c}{u}_{sd}\\ u_{sq}\end{array}\right]=\sqrt{3}{u}_s\left[\begin{array}{c}1\\ 0\end{array}\right],$ Then

$\left\{\begin{array}{c}p\left(t\right)=\sqrt{3}u{i}_d\left(t\right)\\ q\left(t\right)=-\sqrt{3}{u}_{sd}\left(t\right)i_q\left(t\right)\end{array}\right.$

As can be seen from the above equation, i is regulated _qjust can the control STATCOM reactive power that sends or absorb, in like manner, regulate i _dcan adjusting device and system active power exchange.

Carry out Laplace transformation to above formula to obtain:

$LS\left[\begin{array}{c}{I}_d\left(s\right)\\ I_q\left(s\right)\end{array}\right]=\left[\begin{array}{cc}-R& \mathrm{\ω}L\\ -\mathrm{\ω}L& -R\end{array}\right]\left[\begin{array}{c}{I}_d\left(s\right)\\ I_q\left(s\right)\end{array}\right]+\left[\begin{array}{c}{U}_{sd}\left(s\right)\\ U_{sq}\left(s\right)\end{array}\right]-\left[\begin{array}{c}{U}_{cd}\left(s\right)\\ U_{cq}\left(s\right)\end{array}\right]$

Can obviously find out from above formula, active current i _dwith reactive current i _qthere is obvious coupled relation.Control the i of active current _dchange can affect i simultaneously _qchange, vice versa.

Linear extended state observer (LESO) in LADRC has good effect for coupled system, the internal disturbance of coupling terms as system can be observed out, to reach the object of decoupling zero, namely

$\left\{\begin{array}{c}L\frac{{\mathrm{di}}_d}{dt}={\mathrm{\ωLi}}_q+U_{sd}-R\·i_d-U_{cd}\\ L\frac{{\mathrm{di}}_q}{dt}=-{\mathrm{\ωLi}}_d+U_{sq}-R\·i_q-U_{cq}\end{array}\right.$

If ω _d'=ω Li _q+ U _sd, ω _q'=-ω Li _d+ U _sqthen be transformed to:

$\left\{\begin{array}{c}L\frac{{\mathrm{di}}_d}{dt}={{\mathrm{\ω}}_d}^{\′}-R\·i_d-U_{cd}\\ L\frac{{\mathrm{di}}_q}{dt}={{\mathrm{\ω}}_q}^{\′}-R\·i_q-U_{cq}\end{array}\right.$

By supposing above can find out, if by ω _d' and ω _q' as internal system disturbance, so active current i _dwith reactive current i _qonly relevant with the physical quantity of itself, no longer there is the relation of coupling, thus achieve decoupling zero.

Based on above equation, design two close cycles STATCOM controller (see Fig. 4), outer shroud direct current voltage regulator adopts pi regulator, for generation of active current command signal i _dref, inner ring is respectively for d, q axle design single order LADRC.For q axle, selection controlled quentity controlled variable is the q axle component U of STATCOM output voltage _cq, object is to make STATCOM absorb rapidly or export reactive current, follows the tracks of the command signal i that link after testing obtains fast _qref.

First need design second order LESO as follows:

$\left\{\begin{array}{c}{\stackrel{\·}{z}}_1=z_2-{\mathrm{\β}}_1(z_1-i_q)+b_0{U}_{cq}\\ {\stackrel{\·}{z}}_2=-{\mathrm{\β}}_2(z_1-i_q)\end{array}\right.$

Wherein observer variable z ₁follow the tracks of i _qsignal, z ₂follow the tracks of all neutral signals, comprise inside (coupled relation, Parameters variation etc.) and the external disturbance of system.

Next designs LSEF, that is:

U _cq0＝k _p(i _ref-z ₁)

Get controlled quentity controlled variable U _cqdisturbance compensation amount:

$U_{cq}=\frac{(-z_2+U_{cq0})}{b_0}$

Use DSP to realize control algolithm, see flow chart (Fig. 5).

Superiority of the present invention is: adopt cascade seven electrical level inverter being applicable to large capacity STATCOM to be main circuit structure, and utilize high performance signal processor (DSP) and flexibly linear active disturbance rejection control technology to obtain high-precision control effects, substantially increase rapidity and the robustness of system, improve the reactive power compensation response speed of system to the full extent, ensure that the quality of power supply.

(4) accompanying drawing explanation

The structured flowchart of Fig. 1 a kind of cascade seven level static synchronization compensator based on LADRC involved by the present invention.

Fig. 2 is a kind of based on the main circuit module topological diagram in cascade seven level static synchronization compensator of LADRC involved by the present invention.

Fig. 3 is a kind of based on H-bridge unit structure chart in the main circuit module in cascade seven level static synchronization compensator of LADRC involved by the present invention.

The transfer function figure of Fig. 4 a kind of cascade seven level static synchronization compensator control method based on LADRC involved by the present invention.

Fig. 5 is a kind of involved by the present invention program flow diagram of the cascade seven level static synchronization compensator control method based on LADRC.

(5) embodiment:

Embodiment: a kind of cascade seven level static synchronization compensator (see Fig. 1) based on LADRC, is characterized in that it comprises main circuit module, DSP control module, detection module, IGBT drive module; Wherein said detection module input is connected with main circuit by current transformer (CT), and gather three-phase voltage, electric current, phase signal, its output is connected with DSP control module; Described DSP control module output connects IGBT drive module input; Described IGBT drive module output connects main circuit module.

Above-mentioned said main circuit module is often in series by three H-bridge unit, described H-bridge unit is formed in parallel by two brachium pontis I, II and a DC bus capacitor C, described brachium pontis I is in series by after IGBT pipe T1, T2 and diode D1, D2 respectively inverse parallel, and described brachium pontis II is in series by after IGBT pipe T3, T4 and diode D3, D4 respectively inverse parallel.

Above-mentioned said DSP control module by A/D sampling unit, Main Control Unit, external interface unit, extend out memory cell and form.Wherein said A/D sampling unit input is connected with detection module, and output signal is connected with Main Control Unit; Described Main Control Unit is connected with outside output interface unit; Described outside output interface unit is connected with IGBT drive module; And described Main Control Unit also with extend out memory cell and become in being bi-directionally connected.

The described high accuracy chip AD7705 being adopted sigma-delta A/D technology by the employing of A/D sampling unit with 16 A/D converters.

Described Main Control Unit adopts 32 of TI company production to be floating-point signal processor TMS320C28335.

Described external interface unit adopts transistor output photoelectric coupler TLP512.

The described memory cell that extends out adopts 512K, and the flash of 16 stores core SST39VF800.

Above-mentioned said detection module is made up of three-phase current on line side detecting unit, threephase load current detecting unit, DC voltage detecting unit, phase detection unit.Described three-phase current on line side detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described threephase load current detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described DC voltage detecting unit input is connected with main circuit module, and output is connected with DSP control module; Described phase detection unit is connected with main circuit module by phase-locked loop, and output is connected with DSP control module.

Above-mentioned said IGBT drive module is made up of triangular wave generating unit and comparator unit.Described triangular-wave generator unit output connects comparator unit; Described comparator unit input connects DSP control module simultaneously, and output connects main circuit module.

Described triangular-wave generator unit adopts high frequency accurate function signal generator chip MAX038.

Described comparator unit adopts four tunnels independently voltage comparator chip LM339.

Based on a control method for cascade seven level static synchronization compensator of LADRC, it is characterized in that it comprises the following steps:

(1) the i of the threephase load current detecting unit output of detection module _la, i _lb, i _lcenter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, produces idle instruction current i through Park Transformation _qref.

(2) the direct voltage U of each H-bridge unit of the DC voltage detecting unit output of detection module _dc1-U _dc6enter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, respectively with system dc side voltage setting value U _refafter relatively forming error signal, produce meritorious instruction current i through adjuster _dref.

(3) meritorious instruction current i _drefwith idle instruction current i _qrefafter carrying out LADRC algorithm process respectively through the Main Control Unit of DSP control module, form that STATCOM is meritorious, reactive voltage output instruction signal U _cd, U _cq.

(4) the system phase angle θ, the DC voltage set point U that are exported by the phase detection unit of detection module _ref, meritorious, idle command signal U _cd, U _cq, go out through the Main Control Unit mathematical computations of DSP control module the modulation ratio M and phase angle [alpha] that PWM exports, stored in the outside extension storage unit of DSP control module, and export three-phase PWM modulation signal via the external interface unit of DSP control module.

(5) PWM modulation signal enters the comparator unit of IGBT drive module, after comparing, produces main circuit IGBT drive singal, by the size regulating Duty ratio control STATCOM to export reactive current with the triangular wave generating unit of IGBT drive module.Thus carry out the control of reactive power compensating.

Claims (9)

1., based on cascade seven level static synchronization compensator of LADRC, it is characterized in that it comprises main circuit module, DSP control module, detection module, IGBT drive module; Wherein said detection module input is connected with main circuit by current transformer, and gather three-phase voltage, electric current, phase signal, its output is connected with DSP control module; Described DSP control module output connects IGBT drive module input; Described IGBT drive module output connects main circuit module.

2. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 1, it is characterized in that described main circuit module is often in series by three H-bridge unit, described H-bridge unit is formed in parallel by two brachium pontis I, II and a DC bus capacitor C, described brachium pontis I is in series by after IGBT pipe T1, T2 and diode D1, D2 respectively inverse parallel, and described brachium pontis II is in series by after IGBT pipe T3, T4 and diode D3, D4 respectively inverse parallel.

3. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 1, it is characterized in that described DSP control module by A/D sampling unit, Main Control Unit, external interface unit, extend out memory cell and form; Wherein said A/D sampling unit input is connected with detection module, and output signal is connected with Main Control Unit; Described Main Control Unit is connected with outside output interface unit; Described outside output interface unit is connected with IGBT drive module; And described Main Control Unit also with extend out memory cell and become in being bi-directionally connected.

4. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 3, is characterized in that describedly being adopted the high accuracy chip AD7705 adopting sigma-delta A/D technology with 16 A/D converters by A/D sampling unit.

5. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 3, it is characterized in that described Main Control Unit adopts TI company to produce 32 is floating-point signal processor TMS320C28335; Described external interface unit adopts transistor output photoelectric coupler TLP512; The described memory cell that extends out adopts 512K, and the flash of 16 stores core SST39VF800.

6. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 1, is characterized in that described detection module is made up of three-phase current on line side detecting unit, threephase load current detecting unit, DC voltage detecting unit, phase detection unit.Described three-phase current on line side detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described threephase load current detecting unit input is connected with main circuit module by CT, and output is connected with DSP control module; Described DC voltage detecting unit input is connected with main circuit module, and output is connected with DSP control module; Described phase detection unit is connected with main circuit module by phase-locked loop, and output is connected with DSP control module.

7. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 1, is characterized in that described IGBT drive module is made up of triangular wave generating unit and comparator unit.Described triangular-wave generator unit output connects comparator unit; Described comparator unit input connects DSP control module simultaneously, and output connects main circuit module.

8. a kind of cascade seven level static synchronization compensator based on LADRC according to claim 7, is characterized in that described triangular-wave generator unit adopts high frequency accurate function signal generator chip MAX038; Described comparator unit adopts four tunnels independently voltage comparator chip LM339.

9., based on a control method for cascade seven level static synchronization compensator of LADRC, it is characterized in that it comprises the following steps:

(1) the i of the threephase load current detecting unit output of detection module _la, i _lb, i _lcenter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, produces idle instruction current i through Park Transformation _qref;

(2) the direct voltage U of each H-bridge unit of the DC voltage detecting unit output of detection module _dc1-U _dc6enter the A/D sampling unit of DSP control module, sampled result enters the Main Control Unit of DSP control module, respectively with system dc side voltage setting value U _refafter relatively forming error signal, produce meritorious instruction current i through adjuster _dref;

(3) meritorious instruction current i _drefwith idle instruction current i _qrefafter carrying out LADRC algorithm process respectively through the Main Control Unit of DSP control module, form that STATCOM is meritorious, reactive voltage output instruction signal U _cd, U _cq;

(4) the system phase angle θ, the DC voltage set point U that are exported by the phase detection unit of detection module _ref, meritorious, idle command signal U _cd, U _cq, go out through the Main Control Unit mathematical computations of DSP control module the modulation ratio M and phase angle [alpha] that PWM exports, stored in the outside extension storage unit of DSP control module, and export three-phase PWM modulation signal via the external interface unit of DSP control module;

(5) PWM modulation signal enters the comparator unit of IGBT drive module, after comparing, produces main circuit IGBT drive singal, by the size regulating Duty ratio control STATCOM to export reactive current with the triangular wave generating unit of IGBT drive module; Thus carry out the control of reactive power compensating.