CN103176930A - Input/output (I/O) framework expanding method based on standard PCIe upstream port - Google Patents
Input/output (I/O) framework expanding method based on standard PCIe upstream port Download PDFInfo
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Abstract
The invention provides an input/output (I/O) framework expanding method based on a standard PCIe upstream port. Layering multistage bus expansion of the standard PCIe upstream port is used. A PCIe bus is arranged in a first stage, a PCI bus is arranged in a second stage, and a traditional bus is arranged in a third stage, wherein a basis input/output system (BIOS) is arranged in the traditional bus in a hanging mode. Initial configuration required by an SW processor and initial execution codes required by the SW processor are injected through a synchronous serial access out of a band, the initial execution codes achieve access configuration of a traditional device through only once depth-first enumeration, and the SW processor is enabled to rapidly obtain contents of the BIOS. Non-maskable interruption can be sent to a central processing unit (CPU) through the synchronous serial access out of the band, and be used for the aims of waking-up in a sleep state and the like.
Description
Technical field
The present invention relates to relate to computing machine and the communications field, specifically, the present invention relates to a kind of IO expansion framework method based on Standard PC Ie uplink port.
Background technology
At present, based on the system of X 86 processor, use proprietary system bus, as the QPI bus of Intel and the HT bus of AMD, legacy equipment is articulated on the extended DMI of system bus or A-Link, and the PCIe/PCI bridgt circuit also hangs on system bus, and logical relation as shown in Figure 1.
X 86 processor A1 can access legacy equipment (comprising BIOS) A3 once powering on, pass through PCIe/PCI bridge A2 PCI allocation e/PCI path and equipment in the BIOS implementation.
But Shen prestige processor does not use the proprietary system bus of offshore company, but will utilize external units numerous on market, with regard to the integrated PCIe root complex of standard, does not directly articulate the interface of legacy equipment.Shen prestige processor can't accomplish to access once powering on legacy equipment.
Summary of the invention
The problem that the present invention solves is based on I/O scaling problem and the processor electrifying startup problem of the system of Shen prestige processor.
In order to address the above problem, according to the present invention, a kind of IO expansion framework method based on Standard PC Ie uplink port for Shen prestige processor is provided, it comprises: carry out the expansion of layered multi-stage bus, wherein the root of multistage bus is the Standard PC Ie interface of Shen prestige processor, processor provides band outer serial ports, determines bus from the distance of processor according to the height of bus bandwidth, and the BIOS chip is hung over farthest place; Carry out initial configuration and the original execution code of Shen prestige processor hardware, by being injected in the internal register and instruction cache of Shen prestige processor with outer serial ports, complete the startup configuration of processor, make processor carry out start-up code; Complete the training of depositing control and the initialization of main memory by the original execution code of Shen prestige processor, and the enumeration operation by the depth-first of a PCI equipment, complete Shen prestige processor to the structure of BIOS access path, can realize thus carrying out fast bios code.
Be with outer serial ports based on common clock, data transmit-receive speed is up to 25Mbps, and the data transmit-receive of system end can be chosen in rising edge or the negative edge of clock, man-to-man transmitted in both directions mode; Under deep sleep, the PCIe uplink port quits work, and the interruption that is used for waking up makes processor release deep sleep by be delivered to the interruptable controller of Shen prestige processor with guest performer's oral instructions.
Preferably, legacy equipment is articulated on processor bus farthest, by the configuration of bus arbitration priority at different levels.Thereby, guarantee that equipment at different levels are at the quality of service requirement of the aspects such as bandwidth, delay.
Preferably, the original execution code includes PCI device enumeration function, is used for conventional I/O allocation of space to first next stage bus.
Preferably, be with outer serial ports to adopt synchronous Physical layer, and the phase relation of clock and data can join at system end, link layer does not have strict sequential requirement with the form transmission of bag between request and response.
Preferably, the transmission of the bag of link layer is continuously, can not suspend, with beginning and the length of specific command code and answer code sign bag.
Preferably, interrupt using a specific command code and packet format, pass to processor in the mode of wrapping.
Preferably, according to the needs of real system, strengthen or weaken the ability of certain grade of bus locking equipment wherein.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention, more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the logical relation of legacy equipment.
Fig. 2 is a kind of embodiment schematic diagram of I/O expansion framework method of the present invention;
Fig. 3 is a kind of embodiment schematic diagram of I/O expansion framework method of the present invention;
Fig. 4 is the another kind of embodiment schematic diagram of I/O expansion framework method of the present invention;
Fig. 5 is a kind of embodiment schematic diagram of system start method of the present invention;
Fig. 6 is a kind of embodiment schematic diagram of system wake-up method of the present invention.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
For solving the problems referred to above of prior art, at the I/O expansion framework method for the Shen Wei system provided by the invention, the layered multi-stage bus expansion of Application standard PCIe uplink port, the first order is the PCIe bus, the second level is pci bus, the third level is conventional bus, and wherein BIOS hangs under conventional bus; By injecting required initial configuration and the original execution code of Shen prestige processor with outer synchronous serial path, the original execution code only needs enumerating of a depth-first, the access passage of just having completed legacy equipment builds, and makes the Shen prestige processor can quick obtaining BIOS content; By with outer synchronous serial path, can send not to CPU that maskable interrupts, be used for the purpose such as wake up under sleep state.
Wherein, in the present invention, term " legacy equipment " refers to the miscellaneous equipment except processor in computing machine.
Further say, for solving the problems referred to above of prior art, the invention provides a kind of I/O expansion framework method based on Standard PC Ie uplink port, comprising:
Carry out the expansion of layered multi-stage bus, wherein the root of multistage bus is the Standard PC Ie interface of Shen prestige processor, processor also provides band outer serial ports, determine that according to the height of bus bandwidth bus from the distance of processor (namely, bus bandwidth is higher, from processor more close to), legacy equipment (comprising the BIOS chip) is articulated on processor bus farthest.By the configuration of bus arbitration priority at different levels, guarantee that equipment at different levels are at the quality of service requirement of the aspects such as bandwidth, delay; For example, hang over audio frequency on pci bus and broadcast the be rivals in a contest quality of service requirement of bandwidth and delay of device.Can according to the needs of real system, strengthen or weaken the ability of certain grade of bus locking equipment wherein.
Carry out initial configuration and the initial start code of Shen prestige processor hardware, by being injected in the internal register and instruction cache of Shen prestige processor with outer serial ports, complete the initial configuration of processor, make processor carry out the initial start code.
Shen prestige processor is completed the training of depositing control and the initialization of main memory by carrying out the initial start code, also include PCI device enumeration function in code, enumeration operation by the depth-first of a PCI equipment, give first next stage bus with conventional I/O allocation of space, complete Shen prestige processor to the structure of BIOS access path.The correct position of main memory got bios code by Shen prestige processor, then carries out bios code.
Under deep sleep, the PCIe uplink port quits work, and the interruption that is used for waking up makes processor release deep sleep by be delivered to the interruptable controller of Shen prestige processor with guest performer's oral instructions.
Be with the transmission of outer Serial Port Information, Physical layer is based on common clock, man-to-man duplex transmission mode, data transmit-receive speed is up to 25Mbps, the data transmit-receive of system end can be chosen in rising edge or the negative edge of clock, thereby adjusts the phase relation of clock and data, reduces the engine request of plate level; Link layer does not have strict sequential requirement with the form transmission of bag between request and response.The transmission of bag is continuously, can not suspend, with beginning and the length of special command code and answer code sign bag.Wake-up interrupts is used a special command code and packet format, passes to processor in the mode of wrapping.
By adopting above-mentioned configuration, the invention solves I/O scaling problem and processor electrifying startup problem based on the system of Shen prestige processor.
The below will describe specific embodiments of the invention, so that those skilled in the art can know specific implementation of the present invention.
Fig. 2 is a kind of embodiment schematic diagram of I/O expansion framework method of the present invention.
With reference to shown in Figure 2, comprise according to the IO expansion framework based on Standard PC Ie uplink port of one embodiment of the present invention: Shen prestige processor 101, main memory 102, PCIe switch 103, PCIe bridge 104, PCI bridge 105, maintenance module 106 and BIOS chip 107.
Wherein, Shen prestige processor 101 directly articulates main memory 102 and deposits control with integrated, and is connected with PCIe switch 103 with integration standard PCIe interface; In addition, Shen prestige processor 101 also can possess low speed serial ports (band is outer), in order to be connected with maintenance module 106;
The uplink port of PCIe switch 103 is connected with the PCIe interface of Shen prestige processor, and PCIe switch 103 can expand a plurality of PCIe ports, is used for connecting PCIe expansion slot or PCIe equipment, and each equipment need take a PCIe port;
The uplink port of PCIe bridge 104 is connected with PCIe switch 103, can expand the standard pci bus, articulates a plurality of loads such as pci expansion slot, PCI equipment on a pci bus;
The uplink port of PCI bridge 105 is connected with the PCIe bridge, can expand multiple conventional bus (for example LPC(Low Pin Count) bus, XBus(eXtended Bus) bus), be used for articulating legacy equipment, legacy equipment has relatively little address space, and the base address range of choice in these spaces is very little.
One end of maintenance module 106 is connected with the serial ports of Shen prestige processor (band is outer), and the other end hangs on conventional bus as legacy equipment, can carry out in-band communications with Shen prestige processor.The plug-in FlashROM chip of maintenance module.
FlashROM chip 107 is used for depositing initial configuration and the initial start code of Shen prestige processor, can also deposit the information such as UEFI BIOS, realizes the non-volatile memory of these information.
Fig. 3 is the schematic diagram of a kind of embodiment of I/O expansion framework method of the present invention.
With reference to shown in Figure 3, in an embodiment of I/O expansion framework method of the present invention, I/O expansion framework comprises: second generation Shen prestige processor (Shen Wei-2 processor) 201, DDR3 main memory 202,8PortPCIe switch 203, PCIe-to-PCI bridge 204, PCI-to-LPC bridge 205, maintenance module 206, FlashROM chip 207.
Wherein, Shen Wei-2 processor 201 integrated DDR3 deposit control, directly articulate DDR3 main memory 202; Integration standard PCIe Gen2X8 interface is connected with 8-Port PCIe Gen2 switch 203; And Shen Wei-2 processor 201 possesses low speed serial ports (band outer), is connected with maintenance module;
The uplink port of 8-Port PCIe Gen2 switch 203 is connected with the PCIe Gen2X8 interface of Shen prestige processor, the PCIe switch can expand 7 PCIe ports, be used for connecting PCIe expansion slot or PCIe equipment, each equipment need take a PCIe port (comprising PCIe-to-PCI bridge 204);
The uplink port of PCIe-to-PCI bridge 204 is connected with 8-Port PCIe Gen2 switch 203, expand standard 32-bit pci bus, article one, 4 above loads be can articulate at most on pci bus, pci expansion slot or PCI equipment (comprising PCI-to-LPC bridge 205) connected;
The uplink port of PCI-to-LPC bridge 205 is connected with pci bus, expands lpc bus, is used for articulating SIO(Super I/O), EC(Embedded Controller) etc. legacy equipment.
FlashROM chip 207 is connected with Mini-BMC+ maintenance module 206 by the SPI interface, is used for depositing the firmware of mini-BMC, deposits initial configuration and the information such as initial start code, BIOS of Shen prestige processor, realizes the non-volatile memory of these information.
Fig. 4 is the another kind of embodiment schematic diagram of I/O expansion framework method of the present invention.
With reference to shown in Figure 4, in another embodiment of I/O expansion framework method of the present invention, I/O expansion framework comprises second generation Shen prestige processor (Shen Wei-2 processor) 301, DDR3 main memory 302,6PortPCIe switch 303, PCIe-to-PCI bridge 304, PCIe equipment complex 305, PCI-to-LPC bridge 306, mini-BMC+ maintenance module 307, FlashROM chip 308, wherein
Shen Wei-2 processor 301, integrated DDR3 deposits control, directly articulates DDR3 main memory 302; Integration standard PCIe Gen2X8 interface is connected with 6-Port PCIe Gen2 switch 303; Possess low speed serial ports (band is outer), be connected with the mini-BMC+ maintenance module;
6-Port PCIe Gen2 switch 303, uplink port is connected with the PCIe Gen2X8 interface of Shen prestige processor, and the PCIe switch can expand 5 PCIe ports, is used for connecting PCIe expansion slot or PCIe equipment, and each equipment need take a PCIe port;
PCIe-to-PCI bridge 304, uplink port is connected with 6-Port PCIe Gen2 switch 303, expands standard 32-bit pci bus, can articulate at most 4 above loads on a pci bus, connects pci expansion slot or PCI equipment;
PCIe meets equipment 305, inner integrated a plurality of PCIe equipment, and uplink port is connected with 6-Port PCIeGen2 switch 303, expands the 32-bit local bus, articulates mini-BMC+ maintenance module 307;
PCI-to-LPC bridge 306, uplink port is connected with pci bus, expands lpc bus, is used for articulating SIO(Super I/O), EC(Embedded Controller), the legacy equipment such as TPM.
FlashROM chip 308 is connected with Mini-BMC+ maintenance module 307 by the SPI interface, is used for depositing the firmware of mini-BMC, deposits initial configuration and the information such as initial start code, BIOS of Shen prestige processor, realizes the non-volatile memory of these information.
Fig. 5 is a kind of embodiment schematic diagram of system start method of the present invention.
With reference to shown in Figure 5, a kind of embodiment of system start method of the present invention comprises: mini-BMC self check 401, and system configuration preserves 402, initial configuration Shen prestige processor 403, Shen prestige processor initialization 404, the BIOS path builds 405, gets BIOS and carries out 406.
The below will specifically describe each step.
Mini-BMC self check 401: power on rear (comprising standby power) carries out at first, comprises the self check of mini-BMC self-operating environment, and the detection of system configuration, in the situation that system possesses requirements for starting construction, carries out next step, and system configuration preserves 402;
System configuration is preserved 402:mini-BMC with some information that system goes into operation and needs, and is kept in Flash ROM, and next does not go on foot according to these information and executing to allow afterwards maintenance module, initial configuration Shen prestige processor 403;
Initial configuration Shen prestige processor 403: be under reset mode at Shen prestige processor, configure the parameter of all kinds of clock generators (as PLL), the mode of operation of processor, the Instruction Cache that even comprises processor inside, some configurations, control register, allow afterwards Shen prestige processor carry out next step, Shen prestige processor initialization 404;
Shen prestige processor initialization 404: after Shen prestige processor withdraws from reset mode, begin to carry out the code in Instruction Cache; Initialization internal register and Data Cache; Train depositing control, to determine to deposit the final configuration parameter of control; The initialization main memory, initialization PCIe interface; Carry out afterwards the BIOS path and build 405;
The BIOS path builds 405: according to the depth-first algorithm, carry out enumerating of PCIe/PCI equipment, give first next stage bus with conventional I/O allocation of space, legacy equipment is the first end-equipment in the tree-shaped institutional framework of pci bus that finds of this algorithm; Carry out afterwards and get BIOS and carry out 406;
Get BIOS and carry out 406: the register of Shen prestige processor by two conventional I of operation/O spaces obtains BIOS and some configuration informations in FlashROM, BIOS is put into specific main storage region, and build the more needed forms of BIOS operation with configuration information; Carry out afterwards BIOS, the startup of completion system.
With reference to shown in Figure 6, a kind of embodiment of system wake-up method of the present invention comprises: deep sleep 501, and wake events 502, maintenance breaks 503 is released sleep 504, the scene of resuming operation 505, normal operating condition 506.
The below will specifically describe each step.
Deep sleep 501: under this state, Shen prestige processor core (Core) is in reset mode, and its PCIe interface also quits work, and link disconnects, and only has the band external tapping of low speed still in work;
Wake events 502: under deep sleep, the PME(platform management event of generation) at first the interruption such as passes to maintenance module, and maintenance module is according to configuration (wake-up interrupts mask off code), determines which interruption can the wake up process device;
Maintenance breaks 503: after maintenance module is determined to want the wake up process device, send out to processor request---maintenance breaks request special by serial ports;
Release sleep 504: after Shen prestige processor was received the maintenance breaks request, PLL began to promote the core work frequency, and core is released reset mode afterwards, begins to carry out instruction;
Restoring scene 505: at first Shen prestige processor judges that whether the purpose of maintenance breaks is in order to wake up, then carry out the operation of a series of restoring scenes, recover the execution environment of the front process of sleep, process and cause the interrupt event that wakes up, processor enters normal operating condition 506 afterwards.
In addition, need to prove, unless otherwise indicated, otherwise the term in instructions " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing instructions, element, step etc., rather than are used for logical relation between each assembly of expression, element, step or ordinal relation etc.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (7)
1. the IO based on Standard PC Ie uplink port that is used for Shen prestige processor expands framework method, it is characterized in that comprising:
Carry out layered multi-stage bus expansion, wherein the root of multistage bus is the Standard PC Ie interface of Shen prestige processor, and processor provides band outer serial ports, determines bus from the distance of processor according to the height of bus bandwidth, and the BIOS chip is hung over farthest place;
Carry out initial configuration and the original execution code of Shen prestige processor hardware, by being injected in the internal register and instruction cache of Shen prestige processor with outer serial ports, complete the startup configuration of processor, make processor carry out start-up code;
Complete the training of depositing control and the initialization of main memory by the original execution code of Shen prestige processor, and the enumeration operation by the depth-first of a PCI equipment, Shen prestige processor completed to the structure of BIOS access path.
2. the IO expansion framework method based on Standard PC Ie uplink port according to claim 1, characterized by further comprising: legacy equipment is articulated on processor bus farthest, by the configuration of bus arbitration priority at different levels.
3. the IO expansion framework method based on Standard PC Ie uplink port according to claim 1 and 2, is characterized in that, the original execution code includes PCI device enumeration function, is used for conventional I/O allocation of space to first next stage bus.
4. the IO based on Standard PC Ie uplink port according to claim 1 and 2 expands framework method, it is characterized in that, be with outer serial ports to adopt synchronous Physical layer, and the phase relation of clock and data can be joined at system end, link layer does not have strict sequential requirement with the form transmission of bag between request and response.
5. the IO expansion framework method based on Standard PC Ie uplink port according to claim 4, is characterized in that, the transmission of the bag of link layer is continuously, can not suspend, with beginning and the length of specific command code and answer code sign bag.
6. the IO expansion framework method based on Standard PC Ie uplink port according to claim 1 and 2, characterized by further comprising: make and interrupt using a specific command code and packet format, pass to processor in the mode of wrapping.
7. the IO expansion framework method based on Standard PC Ie uplink port according to claim 1 and 2, characterized by further comprising: the ability that strengthens or weaken certain grade of bus locking equipment wherein.
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| CN108536643A (en) * | 2018-03-30 | 2018-09-14 | 西安微电子技术研究所 | A kind of high-performance calculation platform |
| CN111966624A (en) * | 2020-07-16 | 2020-11-20 | 芯发威达电子(上海)有限公司 | PCIe expansion method, system and storage medium thereof |
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| CN111966624A (en) * | 2020-07-16 | 2020-11-20 | 芯发威达电子(上海)有限公司 | PCIe expansion method, system and storage medium thereof |
| CN111966624B (en) * | 2020-07-16 | 2022-02-15 | 芯发威达电子(上海)有限公司 | PCIe expansion method, system and storage medium thereof |
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| CN114003170B (en) * | 2021-09-17 | 2024-03-19 | 方一信息科技（上海）有限公司 | FPGA-based Raid card driving method |
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