CN103176930B - A kind of IO based on Standard PC Ie uplink port expands framework method - Google Patents
A kind of IO based on Standard PC Ie uplink port expands framework method Download PDFInfo
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Abstract
The invention provides a kind of IO based on Standard PC Ie uplink port and expand framework method.Use the layered multi-stage bus extension of Standard PC Ie uplink port, the first order is PCIe bus, and the second level is pci bus, and the third level is conventional bus, under wherein BIOS hangs over conventional bus; By the initial configuration needed for the synchronous serial path injection Shen prestige processor outside band and original execution code, original execution code only needs enumerating of a depth-first, the access passage just completing legacy equipment builds, and makes Shen prestige processor can quick obtaining BIOS content; By the synchronous serial path outside band, not maskable interrupts can be sent to CPU, for objects such as waking up under sleep state.
Description
Technical field
The present invention relates to and relate to computing machine and the communications field, specifically, the present invention relates to a kind of IO based on Standard PC Ie uplink port and expand framework method.
Background technology
At present, based on the system of X 86 processor, use proprietary system bus, as the QPI bus of Intel and the HT bus of AMD, legacy equipment is articulated on DMI or A-Link that system bus extends, and PCIe/PCI bridgt circuit is also hung on the system bus, and logical relation as shown in Figure 1.
X 86 processor A1 can access legacy equipment (comprising BIOS) A3 once powering on, by PCIe/PCI bridge A2 PCI allocation e/PCI path and equipment in BIOS implementation.
But, the system bus that Shen prestige processor does not use offshore company proprietary, but external units numerous on market will be utilized, be just integrated with the PCIe root complex of standard, directly do not mount the interface of legacy equipment.Shen prestige processor cannot be accomplished to access legacy equipment once powering on.
Summary of the invention
The problem that the present invention solves is I/O scaling problem based on the system of Shen prestige processor and processor electrifying startup problem.
In order to solve the problem, according to the present invention, provide a kind of IO based on Standard PC Ie uplink port for Shen prestige processor and expand framework method, it comprises: carry out layered multi-stage bus extension, wherein the root of multi-level bus is the standard PCIe interface of Shen prestige processor, processor provides the serial ports outside band, determines the distance of bus from processor according to the height of bus bandwidth, BIOS chip is hung over place farthest; Perform the initial configuration of Shen prestige processor hardware and original execution code, by the internal register that is injected into Shen prestige processor with outer serial ports and instruction cache, complete the startup configuration of processor, make processor perform start-up code; Completed by the original execution code of Shen prestige processor and deposit the training of control and the initialization of main memory, and pass through the enumeration operation of PCI equipment depth-first, complete the structure of Shen prestige processor to BIOS access path, can realize thus performing bios code fast.
Be with outer serial ports based on common clock, data transmit-receive speed is up to 25Mbps, and the data transmit-receive of system end can be selected at the rising edge of clock or negative edge, man-to-man transmitted in both directions mode; Under deep sleep, PCIe uplink port quits work, and for the interruptable controller of interruption by being with guest performer's oral instructions to be delivered to Shen prestige processor waken up, makes processor release deep sleep.
Preferably, legacy equipment is articulated in from processor bus farthest, by the configuration of bus arbitration priority at different levels.Thus, ensure the quality of service requirement of equipment at different levels in bandwidth, delay etc.
Preferably, original execution code includes PCI device enumeration function, for giving first next stage bus by conventional I/O allocation of space.
Preferably, be with outer serial ports to adopt synchronous Physical layer, and the phase relation of clock and data can be joined at system end, link layer, with the transmission of the form of bag, does not have strict timing requirements between request and response.
Preferably, the transmission of the bag of link layer is continuous, can not suspend, the beginning of wrapping with specific command code and answer code mark and length.
Preferably, interrupt use specific command code and packet format, pass to processor in the mode of wrapping.
Preferably, according to the needs of real system, strengthen or weaken the ability of certain grade of bus locking equipment wherein.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the logical relation of legacy equipment.
Fig. 2 is a kind of embodiment schematic diagram that I/O of the present invention expands framework method;
Fig. 3 is a kind of embodiment schematic diagram that I/O of the present invention expands framework method;
Fig. 4 is the another kind of embodiment schematic diagram that I/O of the present invention expands framework method;
Fig. 5 is a kind of embodiment schematic diagram of present system starting method;
Fig. 6 is a kind of embodiment schematic diagram of present system awakening method.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
For solving the problems referred to above of prior art, expand in framework method at the I/O for Shen prestige system provided by the invention, use the layered multi-stage bus extension of Standard PC Ie uplink port, the first order is PCIe bus, the second level is pci bus, the third level is conventional bus, under wherein BIOS hangs over conventional bus; By the initial configuration needed for the synchronous serial path injection Shen prestige processor outside band and original execution code, original execution code only needs enumerating of a depth-first, the access passage just completing legacy equipment builds, and makes Shen prestige processor can quick obtaining BIOS content; By the synchronous serial path outside band, not maskable interrupts can be sent to CPU, for objects such as waking up under sleep state.
Wherein, in the present invention, term " legacy equipment " to refer in computing machine miscellaneous equipment in addition to processors.
Furthermore, for solving the problems referred to above of prior art, the invention provides a kind of I/O based on Standard PC Ie uplink port and expanding framework method, comprising:
Carry out layered multi-stage bus extension, wherein the root of multi-level bus is the standard PCIe interface of Shen prestige processor, processor also provides band outer serial ports, according to the height of bus bandwidth determine bus from processor distance (namely, bus bandwidth is higher, from processor more close to), legacy equipment (comprising BIOS chip) is articulated in from processor bus farthest.By the configuration of bus arbitration priority at different levels, ensure the quality of service requirement of equipment at different levels in bandwidth, delay etc.; Such as, the audio frequency hung in pci bus broadcast device be rivals in a contest bandwidth sum postpone quality of service requirement.According to the needs of real system, can strengthen or weaken the ability of certain grade of bus locking equipment wherein.
Perform the initial configuration of Shen prestige processor hardware and initial boot code, by the internal register that is injected into Shen prestige processor with outer serial ports and instruction cache, complete the initial configuration of processor, make processor perform initial boot code.
Shen prestige processor is completed by execution initial boot code and deposits the training of control and the initialization of main memory, PCI device enumeration function is also included in code, by the enumeration operation of PCI equipment depth-first, give first next stage bus by conventional I/O allocation of space, complete the structure of Shen prestige processor to BIOS access path.Bios code is got the correct position of main memory by Shen prestige processor, then performs bios code.
Under deep sleep, PCIe uplink port quits work, and for the interruptable controller of interruption by being with guest performer's oral instructions to be delivered to Shen prestige processor waken up, makes processor release deep sleep.
Be with outer Serial Port Information to transmit, Physical layer based on common clock, man-to-man duplex transmission mode, data transmit-receive speed is up to 25Mbps, the data transmit-receive of system end can be selected at the rising edge of clock or negative edge, thus the phase relation of adjustment clock and data, reduce the engine request of plate level; Link layer, with the transmission of the form of bag, does not have strict timing requirements between request and response.The transmission of bag is continuous, can not suspend, the beginning of wrapping with special command code and answer code mark and length.Wake-up interrupts uses a special command code and packet format, passes to processor in the mode of wrapping.
By adopting above-mentioned configuration, the invention solves the I/O scaling problem based on the system of Shen prestige processor and processor electrifying startup problem.
To specific embodiments of the invention be described below, can specific implementation of the present invention be known to make those skilled in the art.
Fig. 2 is a kind of embodiment schematic diagram that I/O of the present invention expands framework method.
With reference to shown in Fig. 2, expand framework according to the IO based on Standard PC Ie uplink port of one embodiment of the present invention and comprise: Shen prestige processor 101, main memory 102, PCIe switch 103, PCIe bridge 104, PCI bridge 105, maintenance module 106 and BIOS chip 107.
Wherein, Shen prestige processor 101 directly mounting main memory 102 deposits control with integrated, and is connected with integration standard PCIe interface with PCIe switch 103; In addition, Shen prestige processor 101 also can possess low speed serial ports (band is outer), to be connected with maintenance module 106;
The uplink port of PCIe switch 103 is connected with the PCIe interface of Shen prestige processor, and PCIe switch 103 easily extensible goes out multiple PCIe port, and for connecting PCIe expansion slot or PCIe equipment, each equipment need take a PCIe port;
The uplink port of PCIe bridge 104 is connected with PCIe switch 103, and easily extensible goes out standard PCI bus, a pci bus mounts multiple load such as pci expansion slot, PCI equipment;
The uplink port of PCI bridge 105 is connected with PCIe bridge, easily extensible goes out multiple conventional bus (such as LPC(Low Pin Count) bus, XBus(eXtended Bus) bus), for mounting legacy equipment, legacy equipment has relatively little address space, and the base address range of choice in these spaces is very little.
One end of maintenance module 106 is connected with the serial ports (being with outer) of Shen prestige processor, and the other end, as legacy equipment, hangs in conventional bus, can carry out in-band communications with Shen prestige processor.The plug-in FlashROM chip of maintenance module.
FlashROM chip 107, for depositing initial configuration and the initial boot code of Shen prestige processor, can also be deposited the information such as UEFI BIOS, realize the non-volatile memory of these information.
Fig. 3 is the schematic diagram that I/O of the present invention expands a kind of embodiment of framework method.
With reference to shown in Fig. 3, expand in an embodiment of framework method at I/O of the present invention, I/O expands framework and comprises: second generation Shen prestige processor (Shen Wei-2 processor) 201, DDR3 main memory 202,8PortPCIe switch 203, PCIe-to-PCI bridge 204, PCI-to-LPC bridge 205, maintenance module 206, FlashROM chip 207.
Wherein, the integrated DDR3 of Shen Wei-2 processor 201 deposits control, directly mounts DDR3 main memory 202; Integration standard PCIe Gen2X8 interface, is connected with 8-Port PCIe Gen2 switch 203; And Shen Wei-2 processor 201 possesses low speed serial ports (band is outer), is connected with maintenance module;
The uplink port of 8-Port PCIe Gen2 switch 203 is connected with the PCIe Gen2X8 interface of Shen prestige processor, PCIe switch easily extensible goes out 7 PCIe ports, for connecting PCIe expansion slot or PCIe equipment, each equipment need take a PCIe port (comprising PCIe-to-PCI bridge 204);
The uplink port of PCIe-to-PCI bridge 204 is connected with 8-Port PCIe Gen2 switch 203, expand standard 32-bit pci bus, article one, pci bus more than 4 loads be can mount at most, pci expansion slot or PCI equipment (comprising PCI-to-LPC bridge 205) connected;
The uplink port of PCI-to-LPC bridge 205 is connected with pci bus, expands lpc bus, for mounting SIO(Super I/O), EC(Embedded Controller) etc. legacy equipment.
The BMC of lightweight and maintenance module two legacy equipments integrate by Mini-BMC+ maintenance module 206, are connected on the one hand with the serial ports (being with outer) of Shen Wei-2 processor; On the other hand as legacy equipment, hang on lpc bus, in-band communications can be carried out with Shen prestige processor.The plug-in FlashROM chip 207 of maintenance module.
FlashROM chip 207, is connected with Mini-BMC+ maintenance module 206 by SPI interface, for depositing the firmware of mini-BMC, depositing initial configuration and the information such as initial boot code, BIOS of Shen prestige processor, realizing the non-volatile memory of these information.
Fig. 4 is the another kind of embodiment schematic diagram that I/O of the present invention expands framework method.
With reference to shown in Fig. 4, I/O of the present invention expands in another embodiment of framework method, and I/O expands framework and comprises second generation Shen prestige processor (Shen Wei-2 processor) 301, DDR3 main memories 302,6PortPCIe switch 303, PCIe-to-PCI bridge 304, PCIe equipment complex 305, PCI-to-LPC bridge 306, mini-BMC+ maintenance module 307, FlashROM chip 308, wherein
Shen Wei-2 processor 301, integrated DDR3 deposits control, directly mounts DDR3 main memory 302; Integration standard PCIe Gen2X8 interface, is connected with 6-Port PCIe Gen2 switch 303; Possess low speed serial ports (band is outer), be connected with mini-BMC+ maintenance module;
6-Port PCIe Gen2 switch 303, uplink port is connected with the PCIe Gen2X8 interface of Shen prestige processor, and PCIe switch easily extensible goes out 5 PCIe ports, and for connecting PCIe expansion slot or PCIe equipment, each equipment need take a PCIe port;
PCIe-to-PCI bridge 304, uplink port is connected with 6-Port PCIe Gen2 switch 303, expands standard 32-bit pci bus, and a pci bus can mount at most more than 4 loads, connects pci expansion slot or PCI equipment;
PCIe meets equipment 305, inner integrated multiple PCIe equipment, and uplink port is connected with 6-Port PCIeGen2 switch 303, expands 32-bit local bus, mounting mini-BMC+ maintenance module 307;
PCI-to-LPC bridge 306, uplink port is connected with pci bus, expands lpc bus, for mounting SIO(Super I/O), EC(Embedded Controller), the legacy equipment such as TPM.
Mini-BMC and maintenance module two legacy equipments integrate by Mini-BMC+ maintenance module 307, are connected on the one hand with the serial ports (being with outer) of Shen Wei-2 processor; Hang on local bus on the other hand, in-band communications can be carried out with Shen prestige processor.The plug-in FlashROM chip of Mini-BMC+ maintenance module 308, two legacy equipments share FlashROM chip 308.
FlashROM chip 308 is connected with Mini-BMC+ maintenance module 307 by SPI interface, for depositing the firmware of mini-BMC, depositing initial configuration and the information such as initial boot code, BIOS of Shen prestige processor, realizing the non-volatile memory of these information.
Fig. 5 is a kind of embodiment schematic diagram of present system starting method.
With reference to shown in Fig. 5, a kind of embodiment of present system starting method comprises: mini-BMC self-inspection 401, and system configuration preserves 402, initial configuration Shen prestige processor 403, and prestige processor initialization 404, BIOS path in Shen builds 405, gets BIOS and performs 406.
Each step will be specifically described below.
Mini-BMC self-inspection 401: (comprise standby power) after powering on and perform at first, comprises the self-inspection of mini-BMC its operating conditions, and the detection of system configuration, and when system possesses requirements for starting construction, perform next step, system configuration preserves 402;
System configuration preserve 402:mini-BMC system is gone into operation need some information, be kept in Flash ROM, relief maintenance module according to these information and executing, next does not walk, initial configuration Shen prestige processor 403;
Initial configuration Shen prestige processor 403: under Shen prestige processor is in reset mode, configure the parameter of all kinds of clock generator (as PLL), the mode of operation of processor, even comprise the Instruction Cache of processor inside, some configurations, control register, relief Shen prestige processor perform next step, Shen prestige processor initialization 404;
Shen prestige processor initialization 404: after Shen prestige processor exits reset mode, start the code performed in Instruction Cache; Initialize internal register and data Cache; Train depositing control, to determine to deposit the final configuration parameter of control; Initialize main, initialization PCIe interface; Perform BIOS path afterwards and build 405;
BIOS path builds 405: according to depth-priority-searching method, carry out enumerating of PCIe/PCI equipment, and give first next stage bus by conventional I/O allocation of space, legacy equipment is the first end-equipment in the tree-shaped institutional framework of pci bus that this algorithm finds; Perform afterwards and get BIOS and perform 406;
Get BIOS and perform 406: Shen prestige processor obtains BIOS in FlashROM and some configuration informations by the register in operation two conventional I/O space, BIOS is put into specific main storage region, and builds some forms required for BIOS operation with configuration information; Perform BIOS afterwards, the startup of completion system.
With reference to shown in Fig. 6, a kind of embodiment of present system awakening method comprises: deep sleep 501, wake events 502, maintenance breaks 503, releases sleep 504, resumes operation on-the-spot 505, normal operating condition 506.
Each step will be specifically described below.
Deep sleep 501: in this case, Shen prestige processor core (Core) is in reset mode, and its PCIe interface also quits work, and link disconnects, and only has the band external tapping of low speed still in work;
Wake events 502: under deep sleep, the PME(platform management event of generation) etc. interruption, first pass to maintenance module, maintenance module is according to configuration (wake-up interrupts mask off code), and determining which interrupts can wake up process device;
Maintenance breaks 503: after maintenance module determines to want wake up process device, the request sending out special to processor by serial ports---maintenance breaks request;
Release sleep 504: after Shen prestige processor receives maintenance breaks request, PLL starts to promote core work frequency, core releases reset mode afterwards, starts to perform instruction;
Restoring scene 505: first Shen prestige processor judges that whether the object of maintenance breaks is in order to wake up, then the operation of a series of restoring scene is performed, recover the execution environment of process before sleep, process causes the interrupt event waken up, preprocessor enter normal operating condition 506.
In addition, it should be noted that, unless otherwise indicated, otherwise the term " first " in instructions, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in instructions, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (7)
1. the IO based on Standard PC Ie uplink port for Shen prestige processor expands a framework method, it is characterized in that comprising:
Carry out layered multi-stage bus extension, wherein the root of multi-level bus is the standard PCIe interface of Shen prestige processor, and processor provides the serial ports outside band, determines the distance of bus from processor according to the height of bus bandwidth, BIOS chip is hung over place farthest;
Perform the initial configuration of Shen prestige processor hardware and original execution code, by with outer serial ports by the initial configuration needed for the prestige processor of Shen and original execution code injection to the internal register and instruction cache of Shen prestige processor, complete the startup configuration of processor, make processor perform start-up code;
Completed by the original execution code of Shen prestige processor and deposit the training of control and the initialization of main memory, and pass through the enumeration operation of PCI equipment depth-first, complete the structure of Shen prestige processor to BIOS access path.
2. the IO based on Standard PC Ie uplink port according to claim 1 expands framework method, characterized by further comprising: be articulated in by legacy equipment from processor bus farthest, arbitrated by the configuration of bus at different levels to priority.
3. the IO based on Standard PC Ie uplink port according to claim 1 and 2 expands framework method, and it is characterized in that, original execution code includes PCI device enumeration function, for giving first next stage bus by conventional I/O allocation of space.
4. the IO based on Standard PC Ie uplink port according to claim 1 and 2 expands framework method, it is characterized in that, outer serial ports is with to adopt synchronous Physical layer, and the phase relation of clock and data can be joined at system end, link layer, with the transmission of the form of bag, does not have strict timing requirements between request and response.
5. the IO based on Standard PC Ie uplink port according to claim 4 expands framework method, and it is characterized in that, the transmission of the bag of link layer is continuous, can not suspend, the beginning of wrapping with command code and answer code mark and length.
6. the IO based on Standard PC Ie uplink port according to claim 1 and 2 expands framework method, characterized by further comprising: make interruption use a command code and packet format, pass to processor in the mode of wrapping.
7. the IO based on Standard PC Ie uplink port according to claim 1 and 2 expands framework method, characterized by further comprising: the ability strengthening or weaken certain grade of bus locking equipment wherein.
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| CN107957885B (en) * | 2017-12-01 | 2021-02-26 | 麒麟软件有限公司 | PCIE link equipment standby and recovery method based on Feiteng platform |
| CN108536643A (en) * | 2018-03-30 | 2018-09-14 | 西安微电子技术研究所 | A kind of high-performance calculation platform |
| CN111966624B (en) * | 2020-07-16 | 2022-02-15 | 芯发威达电子(上海)有限公司 | PCIe expansion method, system and storage medium thereof |
| CN114003170B (en) * | 2021-09-17 | 2024-03-19 | 方一信息科技（上海）有限公司 | FPGA-based Raid card driving method |
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