CN103166730A - Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 - Google Patents
Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 Download PDFInfo
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Abstract
The invention discloses a method for synchronizing time in a wireless ad hoc network based on a protocol of an institute of electrical and electronic engineers (IEEE) 1588 and aims to solve the technical problem that the time synchronization accuracy is low by the conventional time synchronization method. According to the technical scheme, the method comprises the following steps of: initializing the whole network to determine a master time node and a slave time node; performing delay measurement on time synchronization communication between the master time node and the slave time node to obtain master-slave communication delay, slave-master communication delay and unidirectional delay between the master time node and the slave time node; performing amplitude limiting filtering on the unidirectional delay in a state of a minimum withdrawn window, and performing filtering estimation on the unidirectional delay subjected to amplitude limiting through a first-order infinite impulse response filter; and calculating time deviation between the master node and the slave, and performing optimal estimation on the time deviation according to a discrete linear Kalman filtering algorithm. By the method, the time deviation stability of the time in the wireless ad hoc network is guaranteed, and the time synchronization accuracy is relatively high.
Description
Technical field
The present invention relates to a kind of wireless self-organization network clock synchronizing method, particularly relate to a kind of wireless self-organization network clock synchronizing method based on the IEEE1588 agreement.
Background technology
Clock synchronous is one of core technology of distributed system, and the performance of distributed network TT﹠C system depends on the clock synchronization accuracy that network can provide to a great extent.Extensive use along with the distributed network TT﹠C system, in order to satisfy the network TT﹠C system to the demand of high-precise synchronization clock, IEEE(Institute of Electrical and Electronics Engineers, IEEE-USA) issue IEEE1588 accurate clock synchronization protocol standard (Precision Time Protocol) in 2002, be called for short PTP.Formulated again the IEEE1588 agreement of redaction in 2008, i.e. IEEE1588v2.
Wireless Ad Hoc networking (being Ad Hoc network) is a kind of special mobile radio networks.It has and does not rely on any network infrastructure, has the characteristics such as very strong self-organization, robustness and survivability, military, speedily carry out rescue work, the disaster relief and emergency communication field have a wide range of applications.The wireless Ad Hoc networking is as a kind of novel distributed network TT﹠C system, and its application is more and more extensive.Clock synchronous is an important support technology of wireless sensor network, and the cooperation perception between network node, data fusion, location technology, energy management all need the support of clock synchronous, could normally carry out.
In wireless self-organization network, how to realize that clock synchronous is a difficult problem.Aging due to the hardware clock of intra-node, clock all has certain error, but all nodes are in distributed state, do not have fixing infrastructure or Centroid to carry out effective clock synchronous to all nodes, therefore internodal local zone time has deviation, cause wireless self-organization network can not well support real time business, make the application of wireless self-organization network be subject to certain restriction and restriction.
The IEEE1588 protocol application in wireless self-organization network, for the equipment in wireless self-organization network provides high precision clock information, is coordinated the action between each equipment, will play good impetus for applying of wireless self-organization network.
Document 1 " publication number is the Chinese invention patent of CN102664696A " discloses a kind of IEEE1588 protocol optimization system and method thereof towards the wireless transmission environment, by the hardware of master-salve clock node module, Channel Modulation demodulation module, transmitting antenna module, reception antenna module, power regulation module, synchronous processing module and signal processing module, realized being applied to the IEEE1588 clock synchronization protocol in wireless environment.
Document 2 " publication number is the Chinese invention patent of CN102104475A " discloses a kind of synchro system based on IEEE1588 and synchronous method thereof, the method is by setting up master-salve clock module, CPU management control module, build an adjustable clock counter of frequency and realize frequency compensation, realized a synchro system towards wireless communication technology field.
But it is all to rely on hardware mode to realize that document discloses high-precision Clock Synchronization Technology, use the hardware and the cost expense that realize larger in wireless self-organization network, and because there is asymmetric link in wireless network, obviously disagree with the supposition that IEEE1588 agreement forward and reverse link postpone to equate, and above-mentioned these patented inventions do not solve this contradiction targetedly.
Summary of the invention
In order to overcome the existing poor deficiency of Clock Synchronization Technology clock synchronization accuracy, the invention provides a kind of wireless self-organization network clock synchronizing method based on the IEEE1588 agreement.The method has been carried out corresponding improvement for the characteristics of asymmetric link in wireless network to IEEE1588 clock synchronous principle.At first carry out the whole network initialization, determine the master clock node and from clock node; Carry out the internodal clock synchronous communication delay of master-salve clock and measure, obtain out the master-slave communication time delay, from the One Way Delay between main communication delay and main and subordinate node; One Way Delay is carried out the limit filtration that minimum keeps out of the way under window process, the One Way Delay after amplitude limiting processing is carried out filtering by the single order infinite impulse response filter estimate to process; Calculate the clock jitter between main and subordinate node, and according to the Discrete Linear Kalman filtering algorithm, clock jitter is carried out optimum estimation; Structure is realized from clock high precision tracking master clock based on the clock servo system of PI controller.Can guarantee under wireless self-organization network the stability of clock jitter between clock, reach higher clock synchronization accuracy.
The technical solution adopted for the present invention to solve the technical problems is: a kind of wireless self-organization network clock synchronizing method based on the IEEE1588 agreement is characterized in comprising the following steps:
Step 1, the whole network initialization is determined the master clock node and from clock node;
Step 2 is carried out the internodal clock synchronous communication delay of master-salve clock and is measured, and obtains out the master-slave communication time delay, from the One Way Delay between main communication delay and main and subordinate node;
Step 3, the One Way Delay that obtains in step 2 is carried out the limit filtration that minimum keeps out of the way under window to be processed, namely only allow to belong to minimum and keep out of the way One Way Delay amplitude limit under window and filter and pass through, keep out of the way window and place an order to time delay for not belonging to minimum, adopt low-pass filtering to process.The foundation of judgement is whether One Way Delay keeps out of the way One Way Delay amplitude limit value under window less than or equal to minimum;
Described minimum is kept out of the way the One Way Delay amplitude limit value under window, produces data to the time that forms MAC layer package, when minimum is kept out of the way window, the MAC layer waits for that time used, the Frame of time, the sending node physical layer transmission Frame of channel idle transmit the time delay that produces, time that recipient's physical layer spends for the reception of completing Frame, recipient with the package decapsulation of MAC layer and extract data and give time delay six parts of respective application layer process and form in wireless channel by application layer.
Step 4 is carried out filtering with the One Way Delay after amplitude limiting processing by the single order infinite impulse response filter and is estimated to process; The formula of the single order infinite impulse response filter of taking is as follows:
s*y(k)-(s-1)*y(k-1)=[delay(k)+delay(k-1)]/2 (1)
In formula, delay (k) is the k One Way Delay through obtaining after step 4 constantly for the k One Way Delay of the moment after the amplitude limiting processing that step 3 obtains, y (k), and s is filter rigidity, round numbers.Adjust the cut-off frequency of filter by adjusting s.When system had just begun, s=1 along with the time increases, increased s gradually until maximum.
Step 5 is calculated the clock jitter between main and subordinate node, and according to the optimum estimation of Discrete Linear Kalman filtering algorithm realization to clock jitter.Wherein, implement the Discrete Linear needed state equation of Kalman Filter Estimation algorithm and observational equation, as shown in the formula:
In formula, the current system state is k, and offset (k) is the clock jitter state value of master-salve clock node current state, and offset (k-1) is the clock jitter state value of master-salve clock node laststate, offset (k)
SurveyBe the clock jitter measured value of master-salve clock node current state, Δ ε (k) is that master-salve clock node current state is poor with respect to the clock source crystal oscillator shake of laststate, and δ d (k) is that current state principal and subordinate time delay is with respect to the difference of One Way Delay.
Discrete Linear Kalman filtering algorithm equation group used is as follows:
Wherein, offset (k|k-1) is the result of laststate prediction, offset (k-1|k-1) is the result of laststate optimum, offset (k|k) is the optimization estimated value of current state, P (k|k-1) is covariance corresponding to offset (k|k-1), P (k|k) is covariance corresponding to offset (k|k), K
gBe kalman gain, Q and R are respectively process noise and measure the variance of noise.
Step 6, the clock servo system that builds based on the PI controller realizes from the clock tracing master clock.
The closed-loop control system that described PI controller is made of ratio P and two links of integration I, wherein proportional P is used for eliminating error originated from input, be the time migration between master-salve clock, integration item I is used for the steady-state error of elimination system, namely reduces the speed difference of master-salve clock.PI controller equation formula is
In formula, offset (k) is the present clock deviation, A
pBe proportional P parameter, A
IBe integration item I parameter, the clock ticktack frequency of y (k) for adjusting.
The invention has the beneficial effects as follows: for asymmetric link in wireless network, IEEE1588 clock synchronous principle has been carried out corresponding improvement due to the method.At first carry out the whole network initialization, determine the master clock node and from clock node; Carry out the internodal clock synchronous communication delay of master-salve clock and measure, obtain out the master-slave communication time delay, from the One Way Delay between main communication delay and main and subordinate node; One Way Delay is carried out the limit filtration that minimum keeps out of the way under window process, the One Way Delay after amplitude limiting processing is carried out filtering by the single order infinite impulse response filter estimate to process; Calculate the clock jitter between main and subordinate node, and according to the Discrete Linear Kalman filtering algorithm, clock jitter is carried out optimum estimation; Structure is realized from clock high precision tracking master clock based on the clock servo system of PI controller.Guarantee under the wireless self-organization network stability of clock jitter between clock, reached higher clock synchronization accuracy.
Description of drawings
Fig. 1 is clock synchronous servo system structure figure in the inventive method.
Fig. 2 minimumly in the inventive method keeps out of the way window and places an order to the composition diagram of time delay amplitude limit value.
Embodiment
Below in conjunction with Fig. 1, Fig. 2, the technique effect of design of the present invention, concrete structure and generation is described further, with abundant understanding purpose of the present invention, feature and effect.
At first the master-salve clock node communicates to measure and obtains principal and subordinate's time delay t
msWith from main time delay t
sm, obtain One Way Delay between master-salve clock through computing.Secondly One Way Delay is carried out minimum and keep out of the way amplitude limit filtration treatment under window, ensure that the IEEE1588 agreement is applicable to wireless self-organization network.Then in the processing to clock jitter, carry out the clock jitter stabilization processes based on the Discrete Linear Kalman Filter Estimation, in the removal wireless self-organization network, the unstable clock jitter that records that causes of time delay is shaken larger impact, ensures the degree of precision of the present invention on synchronization accuracy and offset error.Adjusted at last the frequency of local clock by the output of PI controller, to realize the clock synchronous of master-salve clock.
Wireless self-organization network clock synchronizing method concrete steps based on the IEEE1588 agreement of the present invention are as follows:
Step 1, best master clock is chosen in the whole network initialization, determines the master clock node and from clock node.Wherein, only have a master clock node and several in the wireless self-organization network of setting up from clock node;
Step 2 is carried out the internodal clock synchronous communication delay of master-salve clock and is measured, and obtains out the master-slave communication time delay, from the One Way Delay between main communication delay and main and subordinate node.The communication delay measurement comprises offset measurement stage and delay measurements stage;
Step 3, the One Way Delay that obtains in step 2 is carried out the limit filtration that minimum keeps out of the way under window to be processed, namely only allow to belong to minimum and keep out of the way One Way Delay amplitude limit under window and filter and pass through, keep out of the way window and place an order to time delay for not belonging to minimum, adopt low-pass filtering to process.The foundation of judgement used is whether One Way Delay keeps out of the way One Way Delay amplitude limit value under window less than or equal to minimum;
Described minimum keep out of the way under window the One Way Delay amplitude limit value as shown in Figure 2, formed by transmission processing time delay, access time delay, propagation delay time, propagation delay, receive time delay and reception ﹠ disposal time delay.Wherein, the transmission processing time delay represents the transmission delay of packet from application layer to the MAC layer, and namely application layer produces data to the time that forms MAC layer package; When access time delay represents that minimum is kept out of the way window, the MAC layer is waited for the time of channel idle, and namely keeping out of the way window is CW
minThe time time of wait channel idle; Propagation delay time represents that the sending node physical layer sends the time used of Frame; Propagation delay represents that Frame transmits the time delay that produces in wireless channel; Receive time delay represents the time that recipient's physical layer spends for the reception of completing Frame; The reception ﹠ disposal time delay represents the time of node processing Frame needs, is about to the decapsulation of MAC layer package, extracts the time delay that data are given the respective application layer process.
Step 4 is carried out filtering with the One Way Delay after amplitude limiting processing by the single order infinite impulse response filter and is estimated to process.The formula of the single order infinite impulse response filter of taking is as follows:
s*y(k)-(s-1)*y(k-1)=[delay(k)+delay(k-1)]/2 (1)
Wherein delay (k) is the k One Way Delay of the moment after the amplitude limiting processing that step 3 obtains, and y (k) is the k One Way Delay through obtaining after step 4 constantly, and s is filter rigidity, round numbers.By adjusting s, can adjust the cut-off frequency of filter.When system had just begun, s=1 along with the time increases, increased s gradually until maximum.
Step 5 is calculated the clock jitter between main and subordinate node, and according to the Discrete Linear Kalman filtering algorithm, clock jitter is carried out optimum estimation.Wherein, implement the Discrete Linear needed state equation of Kalman Filter Estimation algorithm and observational equation, as shown in the formula:
Wherein the current system state is k, and offset (k) is the clock jitter state value of master-salve clock node current state, and offset (k-1) is the clock jitter state value of master-salve clock node laststate, offset (k)
SurveyBe the clock jitter measured value of master-salve clock node current state, Δ ε (k) is that master-salve clock node current state is poor with respect to the clock source crystal oscillator shake of laststate, and δ d (k) is that current state principal and subordinate time delay is with respect to the difference of One Way Delay.
Discrete Linear Kalman filtering algorithm equation group used is as follows:
Wherein, offset (k|k-1) is the result of laststate prediction, offset (k-1|k-1) is the result of laststate optimum, offset (k|k) is the optimization estimated value of current state, P (k|k-1) is covariance corresponding to offset (k|k-1), P (k|k) is covariance corresponding to offset (k|k), K
gBe kalman gain, Q and R are respectively process noise and measure the variance of noise.
Step 6, the clock servo system that builds based on the PI controller realizes from clock high precision tracking master clock.
The closed-loop control system that described PI controller is made of ratio P and two links of integration I, wherein proportional P is used for eliminating error originated from input, be the time migration between master-salve clock, integration item I is used for the steady-state error of elimination system, namely reduces the speed difference of master-salve clock.PI controller equation formula is
Wherein offset (k) is the present clock deviation, A
pBe proportional P parameter, A
IBe integration item I parameter, the clock ticktack frequency of y (k) for adjusting.
a kind of wireless self-organization network clock synchronizing method based on the IEEE1588 agreement described in the invention, characteristics for asymmetric link in wireless network, IEEE1588 clock synchronous principle has been carried out corresponding improvement, simultaneously in order to keep the stability of clock jitter between clock, adopt the Discrete Linear Kalman filtering algorithm to carry out optimum estimation to clock jitter, do not rely on hardware, form with pure software has realized the effective application of IEEE1588 agreement in wireless self-organization network, and can be at synchronization accuracy, reach higher index on lock in time and offset error, simultaneously also make the clock synchronous hardware spending of wireless self-organization network and cost expense greatly save.
Claims (1)
1. wireless self-organization network clock synchronizing method based on the IEEE1588 agreement is characterized in that comprising the following steps:
Step 1, the whole network initialization is determined the master clock node and from clock node;
Step 2 is carried out the internodal clock synchronous communication delay of master-salve clock and is measured, and obtains out the master-slave communication time delay, from the One Way Delay between main communication delay and main and subordinate node;
Step 3, the One Way Delay that obtains in step 2 is carried out the limit filtration that minimum keeps out of the way under window to be processed, namely only allow to belong to minimum and keep out of the way One Way Delay amplitude limit under window and filter and pass through, keep out of the way window and place an order to time delay for not belonging to minimum, adopt low-pass filtering to process; The foundation of judgement is whether One Way Delay keeps out of the way One Way Delay amplitude limit value under window less than or equal to minimum;
Described minimum is kept out of the way the One Way Delay amplitude limit value under window, produces data to the time that forms MAC layer package, when minimum is kept out of the way window, the MAC layer waits for that time used, the Frame of time, the sending node physical layer transmission Frame of channel idle transmit the time delay that produces, time that recipient's physical layer spends for the reception of completing Frame, recipient with the package decapsulation of MAC layer and extract data and give time delay six parts of respective application layer process and form in wireless channel by application layer;
Step 4 is carried out filtering with the One Way Delay after amplitude limiting processing by the single order infinite impulse response filter and is estimated to process; The formula of the single order infinite impulse response filter of taking is as follows:
s*y(k)-(s-1)*y(k-1)=[delay(k)+delay(k-1)]/2 (1)
In formula, delay (k) is the k One Way Delay through obtaining after step 4 constantly for the k One Way Delay of the moment after the amplitude limiting processing that step 3 obtains, y (k), and s is filter rigidity, round numbers; Adjust the cut-off frequency of filter by adjusting s; When system had just begun, s=1 along with the time increases, increased s gradually until maximum;
Step 5 is calculated the clock jitter between main and subordinate node, and according to the optimum estimation of Discrete Linear Kalman filtering algorithm realization to clock jitter; Wherein, implement the Discrete Linear needed state equation of Kalman Filter Estimation algorithm and observational equation, as shown in the formula:
In formula, the current system state is k, and offset (k) is the clock jitter state value of master-salve clock node current state, and offset (k-1) is the clock jitter state value of master-salve clock node laststate, offset (k)
SurveyBe the clock jitter measured value of master-salve clock node current state, Δ ε (k) is that master-salve clock node current state is poor with respect to the clock source crystal oscillator shake of laststate, and δ d (k) is that current state principal and subordinate time delay is with respect to the difference of One Way Delay;
Discrete Linear Kalman filtering algorithm equation group used is as follows:
In formula, offset (k|k-1) is the result of laststate prediction, offset (k-1|k-1) is the result of laststate optimum, offset (k|k) is the optimization estimated value of current state, P (k|k-1) is covariance corresponding to offset (k|k-1), P (k|k) is covariance corresponding to offset (k|k), K
gBe kalman gain, Q and R are respectively process noise and measure the variance of noise;
Step 6, the clock servo system that builds based on the PI controller realizes from the clock tracing master clock;
The closed-loop control system that described PI controller is made of ratio P and two links of integration I, wherein proportional P is used for eliminating error originated from input, be the time migration between master-salve clock, integration item I is used for the steady-state error of elimination system, namely reduces the speed difference of master-salve clock; PI controller equation formula is
In formula, offset (k) is the present clock deviation, A
pBe proportional P parameter, A
IBe integration item I parameter, the clock ticktack frequency of y (k) for adjusting.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102104475A (en) * | 2011-01-31 | 2011-06-22 | 上海交通大学 | IEEE 1588-based synchronization system and synchronization method thereof |
CN102664696A (en) * | 2012-03-29 | 2012-09-12 | 上海交通大学 | Wireless transmission environment-oriented IEEE1588 protocol optimization system and IEEE1588 protocol optimization method thereof |
-
2013
- 2013-03-13 CN CN2013100805218A patent/CN103166730A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102104475A (en) * | 2011-01-31 | 2011-06-22 | 上海交通大学 | IEEE 1588-based synchronization system and synchronization method thereof |
CN102664696A (en) * | 2012-03-29 | 2012-09-12 | 上海交通大学 | Wireless transmission environment-oriented IEEE1588 protocol optimization system and IEEE1588 protocol optimization method thereof |
Non-Patent Citations (2)
Title |
---|
KENDALL CORRELL: "Design Considerations for Software Only Implementations", 《PROC. OF IEEE1588 STANDARD FOR A PRECISION CLOCK SYNCHRONIZATION PROTOCOL FOR NETWORKED MEASUREMENT AND CONTROL SYSTEMS》 * |
庄晓燕: "基于卡尔曼滤波器的IEEE 1588时钟同步算法", 《电子测量与仪器学报》 * |
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CN109005584A (en) * | 2017-06-06 | 2018-12-14 | 郑州联睿电子科技有限公司 | The Wireless clock synchronization scheme of positioning system based on TDOA technology |
CN109005584B (en) * | 2017-06-06 | 2021-04-20 | 郑州联睿电子科技有限公司 | Wireless clock synchronization scheme of positioning system based on TDOA technology |
CN107548147B (en) * | 2017-08-11 | 2021-01-15 | 南京微平衡信息科技有限公司 | Wireless self-organizing network external clock-free network synchronization algorithm |
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CN110034839A (en) * | 2019-04-22 | 2019-07-19 | 北京邮电大学 | A kind of telecommunication network time service method |
CN110300450A (en) * | 2019-05-22 | 2019-10-01 | 南京大学 | A kind of clock servo method using sef-adapting filter correction 1588 agreement of IEEE |
CN112311452B (en) * | 2019-07-29 | 2022-04-01 | 中国移动通信集团浙江有限公司 | Clock deviation calculation method and device and calculation equipment |
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CN111106893A (en) * | 2019-12-11 | 2020-05-05 | 江苏方天电力技术有限公司 | Self-calibration clock synchronization method for ad hoc network, master node, slave node and system |
CN112636860A (en) * | 2020-12-23 | 2021-04-09 | 西安云维智联科技有限公司 | IEEE1588 protocol time calibration method based on proportional-integral algorithm |
CN112867132A (en) * | 2020-12-27 | 2021-05-28 | 卡斯柯信号有限公司 | Multi-link time delay jitter optimization method and device based on PTP |
CN112867132B (en) * | 2020-12-27 | 2022-07-15 | 卡斯柯信号有限公司 | Multi-link time delay jitter optimization method and device based on PTP |
CN112953671A (en) * | 2021-03-29 | 2021-06-11 | 广东电网有限责任公司电力调度控制中心 | Method and device for timing accurate clock synchronization protocol |
CN115347965A (en) * | 2021-05-13 | 2022-11-15 | 中国科学院沈阳自动化研究所 | Time synchronization optimization method with cache mechanism based on improved moving average filtering |
CN115347965B (en) * | 2021-05-13 | 2024-05-17 | 中国科学院沈阳自动化研究所 | Time synchronization optimization method with buffer mechanism based on improved moving average filtering |
CN114301561A (en) * | 2021-11-30 | 2022-04-08 | 国网辽宁省电力有限公司葫芦岛供电公司 | Clock synchronization device and method and clock servo system and method for improving IEEE1588 protocol |
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CN114337980A (en) * | 2021-12-23 | 2022-04-12 | 中国电建集团河南省电力勘测设计院有限公司 | High-precision clock synchronization method for 5G smart power grid |
CN114337980B (en) * | 2021-12-23 | 2024-04-16 | 中国电建集团河南省电力勘测设计院有限公司 | High-precision clock synchronization method for 5G smart grid |
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