CN106685564A - Phase difference measuring method and device for master clock node and calibration method and device - Google Patents
Phase difference measuring method and device for master clock node and calibration method and device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
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- H04J3/06—Synchronising arrangements
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Abstract
The invention discloses a phase difference measuring method and device for a master clock node and a calibration method and device. The phase difference measuring method and device for the master clock node and the calibration method and device comprise that according to a precise clock synchronization protocol, at least one master node and at least one slave node are established in each master clock node; the master clock node comprises a first master clock node and at least one second master clock node; a first phase difference between a first master node of the first mast clock node and a first slave node of the first master clock node is obtained; a mapping relationship between the first slave node and a second master node of the second master clock node is established to obtain a second phase difference between the first slave node and the second master node; according to the first phase difference and the second phase difference, and a third phase difference between the first master clock node and the second master clock node is obtained by calculation. A PTP protocol is used to indirectly measure the phase difference between each master clock node, and therefore a reference is provided for synchronization between the main clock nodes and the time between master clock nodes is synchronized.
Description
Technical field
The present invention relates to network communication technology field, more particularly to difference measuring method and device and the school of master clock node
Quasi- method and device.
Background technology
During existing network networking, the master clock of each network is the synchronous clock reference source of other all devices in net, main
Synchronization accuracy between clock node also determine the performance of whole network.Synchronous employing mostly between master clock node at present
The mode of global positioning system (Global Positioning System, abbreviation GPS), when gps signal is good, when each main
Clock node can be synchronous well；But lose or during poor signal in GPS, master clock node will enter hold mode or
Standby clock can be selected as master clock, so as to cause the synchronization accuracy between master clock node to reduce.GPS loses or believes
When number bad, the synchronization accuracy between master clock node is reduced, no good net synchronization capability.
Existing many node synchronized algorithms can be used to calibrate node synchronization, and these algorithms are also applied for master clock node
On, for synchronous master clock nodal clock.But, the premise of these algorithm work is required for accurately obtaining each master clock node
Between phase contrast.The method for also clearly not proposing at present to differ between measurement master clock node in industry.
The content of the invention
It is an object of the present invention to：Propose measuring method and the device differed between a kind of master clock node, based on when
Calibration between clock node simultaneously provides reference.
Further object is that：The calibration steps and device of a kind of master clock node are proposed, master clock section is made
Time synchronized between point.
It is that, up to this purpose, the present invention is employed the following technical solutions：
On the one hand, there is provided the measuring method differed between a kind of master clock node, including：
S10：According to accurate clock synchronization protocol, at least one host node and at least one are set up in each master clock node
It is individual from node；
The master clock node includes the first master clock node and at least one second master clock nodes；
S20：Obtain the first master clock node the first host node and the first master clock node first between node
First difference；
S30：Mapping relations are set up from the second host node of node and the second master clock node by first, first is obtained from section
The second difference between point and the second host node；
S40：According to the described first difference and the described second difference, the first master clock node and the second master clock are calculated
Third phase between node is poor.
Specifically, contact because directly cannot set up between the first master clock node and the second master clock node, this
The main thought of method first looks for directly setting up with the first master clock node and the second master clock node in contacting
The area of a room, by asking for differing for the first master clock node and intermediate quantity and differing for intermediate quantity and the second master clock node, so that it may
To obtain differing between the first master clock node and the second master clock node.
Based on above thinking, first according to by accurate clock synchronization protocol (Precision Time
Synchronization Protocol, abbreviation PTP), the first host node and first is set up in the first master clock node from section
Point, also sets up the second host node and second from node in the second master clock node.
As the first host node and first is located in same clock node equipment, so the first host node and first from node
Can directly obtain from the first difference of node.
And first can set up mapping relations with the second host node from node, and then first is tried to achieve from node and the second main section
The second difference between point.
Thus, so that it may to calculate the first master clock node and the second master clock section by the first difference and the second difference
Third phase between point is poor.
As one kind preferred embodiment, in the S10：First from the second of node and the second master clock node from
Quantity sum of the quantity sum of node no less than the second master clock node.
Specifically, when there is multiple second master clock nodes, each second host node should with one first from section
Point sets up mapping relations, and then ensures to obtain multiple second differences simultaneously, and then accelerates the arithmetic speed of third phase difference.
Further, first the quantity sum of the second master clock node is equal to from the quantity of node.
As one kind preferred embodiment, the S20 is specially：By the internal control of the first master clock node device
Device obtains first and differs.
Specifically, because the host node in same master clock node and being all located in same equipment from node, can give
Host node in same equipment and identical reference clock is provided from node, and then same master clock is obtained by internal controller
Host node in node and differ from first between node.
As one kind preferred embodiment, the S40 is specially：
Third phase is poor=and the first difference+the second differs.
Specifically, phase place of the phase place-the first of first the=the first host node of difference from node；Second difference=the first is from section
The phase place of the second host node of phase place-the set up mapping relations of point.
On the other hand, there is provided the measurement apparatus differed between a kind of master clock node, including：
First master clock node device, for setting up the first host node and first from section according to accurate clock synchronization protocol
Point, and calculate the first host node and differ from first between node with first；
At least one second master clock node devices, for setting up the second host node and according to accurate clock synchronization protocol
Two from node, and makes first to set up mapping relations from node and the second host node, obtain first from node and the second host node it
Between second difference.
Computing module, for according to first difference and second difference, be calculated the first master clock node and second it is main when
Third phase between clock node is poor.
On the other hand, there is provided the survey differed between the calibration steps between a kind of master clock node, including above-mentioned master clock node
Amount method, also includes：
S50：According to calibration algorithm, each master clock node is calibrated, make to be mutually synchronized between master clock.
It is specifically, poor according to the third phase between the first master clock node and at least one second master clock nodes, so that it may
To calibrate to multiple master clock nodes according to existing calibration algorithm, the time synchronized of multiple master clock nodes is made.
As one kind preferred embodiment, the S50 includes：
S501：Calculate the arithmetic mean of instantaneous value of third phase difference；
S502：Using the phase place of the first host node and the arithmetic mean of instantaneous value and as calibration phase place；
S503：The phase place of each master clock node is adjusted according to calibration phase place.
Specifically, multiple master clock nodes are calibrated by arithmetic mean method, simple science, convenience of calculation.
On the other hand, there is provided differ between the calibrating installation differed between a kind of master clock node, including above-mentioned master clock node
Measurement apparatus；
Also include calibration module, for according to calibration algorithm, calibrating each master clock node, make mutually identical between master clock
Step.
As it is a kind of preferred embodiment, it is characterised in that the calibration module specifically for；
Calculate the arithmetic mean of instantaneous value of third phase difference；
Using the phase place of the first host node with calculate gained it is arithmetic mean of instantaneous value and as calibrate phase place；
The phase place of each master clock node is adjusted according to calibration phase place.
Beneficial effects of the present invention are：There is provided a kind of master clock node difference measuring method and device and calibration steps and
Device, measures indirectly the difference between each master clock node by using PTP protocol, and then：
1) calibration based between clock node simultaneously provides reference；
2) make the time synchronized between master clock node；
3) measurement and calibration steps differed between a kind of master clock node, and the measurement essence of the method not only can be provided
Degree can reach nanosecond rank.
Description of the drawings
The present invention is described in further detail below according to drawings and Examples.
The structural representation of measurement apparatus of the Fig. 1 to differ between the master clock node described in embodiment one；
Fig. 2 is the schematic diagram of the master clock node calibrating installation described in embodiment two；
The structural representation of measurement apparatus of the Fig. 3 to differ between the master clock node described in embodiment five；
The structural representation of measurement apparatus of the Fig. 4 to differ between the master clock node described in embodiment six；
The structural representation of measurement apparatus of the Fig. 5 to differ between the master clock node described in embodiment seven；
The structural representation of measurement apparatus of the Fig. 6 to differ between the master clock node described in embodiment eight.
In figure：
1st, the first master clock node；101st, the first host node；102nd, first from node；2nd, the second host node；3rd, second from
Node.
Specific embodiment
Technical scheme is further illustrated below in conjunction with the accompanying drawings and by specific embodiment.
Embodiment one
As shown in figure 1, the present embodiment includes a kind of device of the measuring method differed between use master clock node, its measurement
Method includes：
S10：According to accurate clock synchronization protocol, m1, k (k >=2, k ∈ N) the individual master of m2, m3 ... mk are followed successively by numbering
A host node and at least one is set up in clock node equipment from node；Wherein, k master clock node device includes one
One master clock node, 1 equipment m1 and (k-1) individual second master clock node device m2~m (k-1)；First master clock node 1 includes
First host node 101 and first is from node 102；Second master clock node includes the second host node 2 and second from node 3.First
Being followed successively by n1, n2, n3 ... n (k-1) (k >=2, k ∈ N), first and be equal to from the quantity of node 102 from the numbering of node 102 needs
With the quantity sum of first the second master clock node that mapping relations are set up from node 102, i.e. (k-1) (k >=2, k ∈ N)；
S20：By first host node of internal controller of 1 equipment of the first master clock node 101 and first from node 102 it
Between first difference PM1, n (k-1)；Wherein, the first difference PM1, n (k-1)The phase place-the first of the=the first host node 101 is from node 102
Phase place；
S30：Mapping relations are set up from node 102 and the second host node 2 by first, first is obtained from node 102 and second
The second difference P between host node 2N (k-1), mk；Wherein, the second difference PN (k-1), mk=the first from the phase place of node 102-set up
The phase place of the second host node 2 of mapping relations；PN (k-1), mkIn n (k-1) and mk between, need satisfaction to be mapped to same PTP
Slave paths：For example, numbering is the first of n1 to set up mapping relations with the second host node 2 that numbering is m2 from node 102, is compiled
Numbering of number setting up mapping relations with the second host node 2 that numbering is m3 from node 102 for the first of n2 ... is the of n (k-1)
One sets up mapping relations with the second host node 2 that numbering is mk from node 102.
S40：According to the first difference PM1, n (k-1)With the second difference PN (k-1), mk, it is calculated the first master clock node 1 and
Third phase difference P between two master clock nodesM1, mk；Wherein, third phase difference PM1, mk=the first difference PM1, n (k-1)- the second difference
PN (k-1), mk, i.e.,：
PM1, mk=PM1, n (k-1)+PN (k-1), mk
N (k-1) in formula needs satisfaction to be mapped to same PTP Slave paths and mk between.
Specifically, contact because directly cannot set up between the first master clock node 1 and the second master clock node, this
The main thought of method first looks for directly setting up with the first master clock node 1 and the second master clock node in contacting
The area of a room, by asking for differing for the first master clock node 1 and intermediate quantity and differing for intermediate quantity and the second master clock node, so that it may
To obtain differing between the first master clock node 1 and the second master clock node.
Based on above thinking, first according to by accurate clock synchronization protocol (Precision Time
Synchronization Protocol, abbreviation PTP protocol), 101 He of the first host node is set up in the first master clock node 1
First from node 102, and the second host node 2 and second is also set up in the second master clock node from node 3.In PTP protocol,
PTP Master modules are referred to as host node, and PTP Slave modules are referred to as from node.
As the first host node 101 and first is located in same clock node equipment, so the first host node from node 102
101 and first can directly obtain from the first difference of node 102.
And first can set up mapping relations with the second host node 2 from node 102, so try to achieve first from node 102 with
The second difference between second host node 2.
Thus, so that it may to calculate the first master clock node 1 and the second master clock by the first difference and the second difference
Third phase between node is poor.
In the present embodiment, when there is multiple second master clock nodes, each second host node 2 should be with one
One sets up mapping relations from node 102, and then ensures to obtain multiple second differences simultaneously, and then accelerates the fortune of third phase difference
Calculate speed.
It is at present many in industry mutually to recover with the difference of counting method to calculate differing between master clock node using lock：Lead to first
Over recovery equipment recovers the clock signal of each master clock node, and then using counter measures, each master clock node recovers
Difference between the clock signal for going out, so as to obtain the difference between master clock node；Restoration errors can be introduced during this
And measurement error, reduce the certainty of measurement of the difference between master clock node.And the master clock node adopted in the present embodiment it
Between difference measuring method, provide the form of High Precision Time Stamps avoiding these errors by using PTP protocol.
Embodiment two
In the present embodiment, by taking 5 master clock nodes as an example, using DPSync series PTP chip ACS9521, one
ACS9521 chips include a PTP Master and two PTP Slave modules, and the internal structure of single master clock node is such as
Under：
As shown in Fig. 23 ACS9521 used in the present embodiment, PTP Master modules have used a piece of, constitute 1
Individual first host node 101；PTP Slave modules have used 2, constitute 4 first from node 102.
After host node locking reference clock (Refrence clock, abbreviation Rf) of m1, there is provided 1pps gives PTP Slave moulds
In clock phase-locked loop (Clock phase locked loop, abbreviation Clock PLL) the Clock PLL1 of block；Rf is directly by this
Signal is supplied to another clock phase-locked loop Clock PLL2 of PTP Slave modules, then using this signal as in m1 from section
The local locked clock of point n1 and n2, first host node 101 of such m1 and numbering is n1 first from the of node 102, m1
One host node 101 and numbering be n2 first between node 102 first difference just may be considered Clock PLL1 and
M1 from difference P between nodeClock PLL1, n (k-1), i.e. PM1, n (k-1)=PClock PLL1, n (k-1)(2≤k≤3, k ∈ N).
After the host node locking reference clock of m1, there is provided clock phase-locked loop (Clocks of the 1pps to PTP Slave modules
Phase locked loop, abbreviation Clock PLL) in Clock PLL3；Rf directly provides such signal to PTP Slave moulds
Another clock phase-locked loop Clock PLL4 of block, then using this signal as in m1 when the local locking of node n3 and n4
Clock, it the first of n3 is n4 from first host node 101 and numbering of node 102, m1 that first host node 101 and numbering of such m1 are
First between node 102 first difference just may be considered Clock PLL3 and m1 from the difference between node
PClock PLL3, n (k-1), i.e. PM1, n (k-1)=PClock PLL3, n (k-1)(4≤k≤5, k ∈ N).
And in a piece of ACS9521, can be with the difference between direct access Clock PLL1 and PTP Slave
PClock PLL1, n (k-1)(2≤k≤3, k ∈ N) and difference P between Clock PLL3 and PTP SlaveClock PLL1, n (k-1)(4≤k
≤ 5, k ∈ N).
The PTP Slave1 of m1 are set up logic with the host node of m2 to be connected, the second difference P between them is asked forN1, m2；
The PTP Slave2 of m1 are set up logic with the host node of m3 to be connected, the second difference P between them is asked forN2, m3；By the PTP of m1
Slave3 sets up logic with the host node of m4 and is connected, and asks for the second difference P between themN3, m4；By the PTP Slave4 of m1 with
The host node of m5 sets up logic connection, asks for the second difference P between themN4, m5。
Calculate the third phase difference P between m1 and m2m1,m2=PClock PLL1, n1+PN1, m2；
Calculate the third phase difference P between m1 and m3m1,m3=PClock PLL1, n2+PN2, m3；
Calculate the third phase difference P between m1 and m2m1,m4=PClock PLL3, n3+PN3, m4；
Calculate the third phase difference P between m1 and m2m1,m5=PClock PLL3, n4+PN4, m5。
The synchronous calibration between node is done using common arithmetical method in the present embodiment, third phase difference P is calculatedm1,m2、
Pm1,m3、Pm1,m4、Pm1,m5Arithmetic mean of instantaneous valueWith unalterable rules by arithmetic mean of instantaneous valueCompensate each self-corresponding master clock
Node, finally gives the phase error between each master clock node after calibration.In other embodiments, it would however also be possible to employ other
Calibration algorithm is calibrated, for example, determine median or weighted mean etc..
In the present embodiment, final result of calculation be the output master clock 1pps between five nodes difference 15ns with
It is interior, it is believed that to be mutually synchronized.And the GPS Synchronos methods adopted in prior art, within its error is 100ns.So, adopt
With the calibrating installation described in the present embodiment, the synchronization accuracy between master clock node device is significantly improved.
The present invention by introducing PTP protocol to master clock node, and then measures indirectly the difference of each master clock node, not only
The measurement and calibration steps differed between a kind of master clock node can be provided, and the certainty of measurement of the method can reach nanosecond
Not, based on accurate phase difference data in real time, the synchronous correction of clock node provides favourable sample, is to solve master clock node
Between stationary problem new mode is provided.
Embodiment three
A kind of measurement apparatus differed between master clock node, including：
First master clock node, 1 equipment, for according to accurate clock synchronization protocol set up the first host node 101 and first from
Node 102, and calculate the first host node 101 and differ from first between node 102 with first；
(k-1) (k >=2, k ∈ N) individual second master clock node device, for setting up second according to accurate clock synchronization protocol
Host node 2 and second is from node 3, and makes first to set up mapping relations from node 102 and the second host node 2, obtains first from section
Point 102 is differed with second between the second host node 2.
Computing module, for according to the first difference and the second difference, be calculated the first master clock node 1 and second it is main when
Third phase between clock node is poor.
Example IV
The calibrating installation differed between a kind of master clock node, including the measurement dress differed between the master clock node of embodiment three
Put；
Also include calibration module, for according to calibration algorithm, calibrating each master clock node, make mutually identical between master clock
Step.Further, calibration module specifically for；
Calculate the arithmetic mean of instantaneous value of third phase difference；
Using the phase place of the first host node 101 with calculate gained it is arithmetic mean of instantaneous value and as calibrate phase place；
The phase place of each master clock node is adjusted according to calibration phase place.
Embodiment five
In the present embodiment, first in the first master clock node 1 is less than the second master clock node from the quantity of node 102
Quantity.As shown in figure 3,1 equipment m1 of the first master clock node is provided with first host node 101 and two first from node
102, second clock node device m2, m3, m4 are equipped with second host node 2 and two second from node 3.
The PTP Master of the PTP Slave1 and m2 of m1 set up mapping relations, the PTP of the PTP Slave2 and m3 of m1
Master sets up mapping relations；And then the third phase difference P between m1 and m2 can be obtainedM1, m2, the third phase and m1 and m3 between
Difference PM1, m3。
The PTP Master of the PTP Slave1 and m3 of m2 set up mapping relations, the PTP of the PTP Slave2 and m4 of m2
Master sets up mapping relations；And then the third phase difference P between m2 and m3 can be obtainedM2, m3, the third phase and m2 and m4 between
Difference PM2, m4。
The PTP Master of the PTP Slave1 and m1 of m3 set up mapping relations, the PTP of the PTP Slave2 and m4 of m3
Master sets up mapping relations；And then the third phase difference P between m3 and m1 can be obtainedM3, m1, the third phase and m3 and m4 between
Difference PM3, m4。
The PTP Master of the PTP Slave1 and m2 of m4 set up mapping relations, the PTP of the PTP Slave2 and m1 of m4
Master sets up mapping relations；And then the third phase difference P between m4 and m2 can be obtainedM4, m2, the third phase and m4 and m1 between
Difference PM4, m1。
By calculating, for example：
PM1, m4=PM1, m3+PM3, m4
Can be obtained by m1~m4 master clocks node difference each other.
Embodiment six
In the present embodiment, first is equal to second master clock from the quantity sum of node 3 from the quantity and second of node 102
The quantity of node.As shown in figure 4,1 equipment m1 of the first master clock node is provided with first host node 101 and one first from section
Point 102, second clock node device m2, m3, m4 are equipped with second host node 2 and one second from node 3.In other realities
Apply in example, first from the quantity of node 102 and second from the quantity sum of node 3 more than the second master clock node quantity.
The PTP Master of the PTP Slave1 and m2 of m1 set up mapping relations, so can obtain between m1 and m2
Three difference PM1, m2。
The PTP Master of the PTP Slave1 and m3 of m2 set up mapping relations, so can obtain between m2 and m3
Three difference PM2, m3。
The PTP Master of the PTP Slave1 and m1 of m3 set up mapping relations, so can obtain between m3 and m1
Three difference PM3, m1。
By calculating, for example：
PM1, m3=PM1, m2+PM2, m3
Can be obtained by node third phase each other during m1~m4 master clocks poor.
Embodiment seven
The present embodiment with the difference of embodiment one is：
As shown in figure 5,1 equipment m1 of the first master clock node is provided with two host nodes；Second clock node device m2~m
(k-1) in, what is had is provided with a host node, and what is had is provided with two, three even more host nodes.
A host node is selected from two host nodes of m1 as the first host node 101, time of m1 equipment is with first
The time of host node 101 is defined；A host node is selected from m (k-1) (k >=2, k ∈ N) equipment as the of m (k-1) equipment
Two host nodes 2, the time of m (k-1) equipment were defined by the time of the second host node 2.
Then according to the difference measuring method in embodiment one carries out the measurement of the third phase difference between m1 and m (k-1).
Embodiment eight
The present embodiment with the difference of embodiment one is：
As shown in fig. 6, the quantity of the second master clock node is that (k-1) is individual, and from section in 1 equipment m1 of the first master clock node
The quantity of point is more than (k-1), and the selection from node from m1 is individual from node with the quantity identical (k-1) of the second master clock node
As first from node 102, then according to the method in embodiment one is set up first with the second host node 2 from node 102 reflecting
Relation is penetrated, the third phase tried to achieve between each master clock node device is poor.
Herein " first ", " second " just for the sake of being distinguish between in description, not special implication.
It is to be understood that, above-mentioned specific embodiment is only that presently preferred embodiments of the present invention and institute's application technology are former
Reason, in technical scope disclosed in this invention, change that any those familiar with the art is readily apparent that or
Replace, should all cover within the scope of the present invention.
Claims (10)
1. the measuring method for differing between a kind of master clock node, it is characterised in that include：
S10：According to accurate clock synchronization protocol, set up in each master clock node at least one host node and at least one from
Node；
The master clock node includes the first master clock node and at least one second master clock nodes；
S20：Obtain the first master clock node the first host node and the first master clock node first from first between node
Difference；
S30：Mapping relations are set up from the second host node of node and the second master clock node by first, obtain first from node and
The second difference between second host node；
S40：According to the described first difference and the described second difference, the first master clock node and the second master clock node are calculated
Between third phase it is poor.
2. the measuring method for differing between a kind of master clock node according to claim 1, it is characterised in that
In the S10：First from the second of node and the second master clock node leads from the quantity sum of node no less than second
The quantity sum of clock node.
3. the measuring method for differing between a kind of master clock node according to claim 2, it is characterised in that first from node
Quantity be equal to the second master clock node quantity sum.
4. the measuring method for differing between a kind of master clock node according to claim 1, it is characterised in that
The S20 is specially：First is obtained by the internal controller of the first master clock node device to differ.
5. the measuring method for differing between a kind of master clock node according to claim 1, it is characterised in that
The S40 is specially：
Third phase is poor=and the first difference+the second differs.
6. the measurement apparatus for differing between a kind of master clock node, it is characterised in that include：
First master clock node device, for setting up the first host node and first from node according to accurate clock synchronization protocol, and
Calculate the first host node to differ from first between node with first；
At least one second master clock node devices, for according to accurate clock synchronization protocol set up the second host node and second from
Node, and make first to set up mapping relations from node and the second host node, acquisition first is between node and the second host node
Second difference.
Computing module, for according to the first difference and the second difference, being calculated the first master clock node and the second master clock section
Third phase between point is poor.
7. the calibration steps between a kind of master clock node, it is characterised in that including any one of Claims 1 to 5 claim institute
The measuring method differed between the master clock node stated, also includes：
S50：According to calibration algorithm, each master clock node is calibrated, make to be mutually synchronized between master clock.
8. the calibration steps between a kind of master clock node according to claim 7, it is characterised in that the S50 includes：
S501：Calculate the arithmetic mean of instantaneous value of third phase difference；
S502：Using the phase place of the first host node and the arithmetic mean of instantaneous value and as calibration phase place；
S503：The phase place of each master clock node is adjusted according to calibration phase place.
9. the calibrating installation for differing between a kind of master clock node, it is characterised in that including the master clock node described in claim 6
Between the measurement apparatus that differ；
Also include calibration module, for according to calibration algorithm, calibrating each master clock node, make to be mutually synchronized between master clock.
10. the calibrating installation for differing between a kind of master clock node according to claim 9, it is characterised in that the calibration
Module specifically for；
Calculate the arithmetic mean of instantaneous value of third phase difference；
Using the phase place of the first host node with calculate gained it is arithmetic mean of instantaneous value and as calibrate phase place；
The phase place of each master clock node is adjusted according to calibration phase place.
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