CN106685564B - The difference measuring method and device and calibration method and device of master clock node - Google Patents
The difference measuring method and device and calibration method and device of master clock node Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/06—Synchronising arrangements
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Abstract
The present invention discloses the difference measuring method and device and calibration method and device of master clock node, including：According to accurate clock synchronization protocol, at least one host node and at least one from node is established in each master clock node；The master clock node includes the first master clock node and at least one second master clock node；The first host node of the first master clock node is obtained to differ from first between node with the first of the first master clock node；Mapping relations are established from the second host node of node and the second master clock node by first, obtain first the second difference between node and the second host node；It is differed according to first difference and described second, the third being calculated between the first master clock node and the second master clock node differs.The present invention measures the difference between each master clock node by using PTP protocol indirectly, and then the calibration between main clock node simultaneously provides the time synchronization for referring to and making between master clock node.
Description
Technical field
The present invention relates to the difference measuring method and device of network communication technology field more particularly to master clock node and schools
Quasi- method and device.
Background technology
During existing net networking, the master clock of each network is the clock reference source that other all devices synchronize in net, main
Synchronization accuracy between clock node also determines the performance of whole network.Synchronizing between master clock node mostly uses greatly at present
The mode of global positioning system (Global Positioning System, abbreviation GPS), when GPS signal is good, when each main
Clock node can synchronize well；But when GPS loses either poor signal master clock node will enter hold mode or
Spare clock can be selected as master clock, to cause the synchronization accuracy between master clock node to reduce.GPS loses or letter
When number bad, the synchronization accuracy between master clock node reduces, without good net synchronization capability.
Existing many node synchronized algorithms can be used for calibrating node synchronization, these algorithms are also applied for master clock node
On, it is used for synchronous master clock nodal clock.But the premise of these algorithms work is required for accurately obtaining each master clock node
Between phase difference.It clearly proposes to measure the method differed between master clock node not yet in industry at present.
Invention content
It is an object of the present invention to：The measurement method differed between a kind of master clock node and device are proposed, when being main
Calibration between clock node simultaneously provides reference.
It is another object of the present invention to：It proposes a kind of calibration method and device of master clock node, makes master clock section
Time synchronization between point.
For this purpose, the present invention uses following technical scheme：
On the one hand, the measurement method differed between a kind of master clock node is provided, including：
S10：According to accurate clock synchronization protocol, at least one host node and at least one are established in each master clock node
It is a from node；
The master clock node includes the first master clock node and at least one second master clock node；
S20：Obtain the first master clock node the first host node and the first master clock node first between node
First difference；
S30：Mapping relations are established from the second host node of node and the second master clock node by first, obtain first from section
The second difference between point and the second host node；
S40：It is differed according to first difference and described second, the first master clock node and the second master clock is calculated
Third difference between node.
Specifically, it is contacted because can not directly be established between the first master clock node and the second master clock node, this
The main thought of method is in first looking for contact with the first master clock node and the direct foundation of the second master clock node
The area of a room, by seeking differing for the first master clock node and intermediate quantity and differing for intermediate quantity and the second master clock node, so that it may
To obtain differing between the first master clock node and the second master clock node.
Based on the above thinking, first according to by accurate clock synchronization protocol (Precision Time
Synchronization Protocol, abbreviation PTP), the first host node and first is established in the first master clock node from section
Point also establishes the second host node and second from node in the second master clock node.
Since the first host node and first are located at from node in same clock node equipment, so the first host node and first
It can be directly obtained from the first difference of node.
And first can establish mapping relations from node with the second host node, and then first is acquired from node and the second main section
The second difference between point.
Thus, the first master clock node and the second master clock section can be calculated by the first difference and the second difference
Third difference between point.
As a preferred embodiment, in the S10：First from the second of node and the second master clock node from
The sum of quantity of node is no less than the sum of the quantity of the second master clock node.
Specifically, when there is multiple second master clock nodes, each second host node should be with one first from section
Point establishes mapping relations, and then ensures that multiple second differences can be obtained simultaneously, and then accelerates the arithmetic speed of third difference.
Further, the first the sum of quantity from the quantity of node equal to the second master clock node.
As a preferred embodiment, the S20 is specially：Pass through the internal control of the first master clock node device
Device obtains the first difference.
Specifically, it because host node in same master clock node and being all located in same equipment from node, can give
Host node in same equipment and identical reference clock is provided from node, and then same master clock is obtained by internal controller
Host node in node and from the first difference between node.
As a preferred embodiment, the S40 is specially：
Third difference the+the second difference of the=the first difference.
Specifically, phase of the phase-the first of first the=the first host node of difference from node；Second differs=the first from section
The phase of the second host node of mapping relations has been established in the phase-of point.
On the other hand, the measuring device differed between a kind of master clock node is provided, including：
First master clock node device, for establishing the first host node and first from section according to accurate clock synchronization protocol
Point, and calculate the first host node and differed from first between node with first；
At least one second master clock node device, for establishing the second host node and according to accurate clock synchronization protocol
Two from node, and makes first to establish mapping relations from node and the second host node, obtain first from node and the second host node it
Between second difference；
Computing module, for according to first difference and second difference, be calculated the first master clock node and second it is main when
Third difference between clock node.
On the other hand, the calibration method between a kind of master clock node is provided, including the survey differed between above-mentioned master clock node
Amount method further includes：
S50：According to calibration algorithm, each master clock node is calibrated, makes to be mutually synchronized between master clock.
Specifically, it is differed according to the third between the first master clock node and at least one second master clock node, so that it may
To be calibrated to multiple master clock nodes according to existing calibration algorithm, make the time synchronization of multiple master clock nodes.
As a preferred embodiment, the S50 includes：
S501：Calculate the arithmetic mean of instantaneous value of third difference；
S502：Using the phase of the first host node and the arithmetic mean of instantaneous value and as calibration phase；
S503：The phase of each master clock node is adjusted according to calibration phase.
Specifically, multiple master clock nodes are calibrated by arithmetic mean method, simple science, convenience of calculation.
On the other hand, the calibrating installation differed between a kind of master clock node is provided, including is differed between above-mentioned master clock node
Measuring device；
Further include calibration module, for according to calibration algorithm, calibrate each master clock node, makes mutually identical between master clock
Step.
As a preferred embodiment, it is characterized in that, the calibration module is specifically used for；
Calculate the arithmetic mean of instantaneous value of third difference；
Using the phase of the first host node with calculate gained arithmetic mean of instantaneous value and as calibration phase；
The phase of each master clock node is adjusted according to calibration phase.
Beneficial effects of the present invention are：There is provided a kind of master clock node difference measuring method and device and calibration method and
Device measures the difference between each master clock node by using PTP protocol, in turn indirectly：
1) calibration between main clock node simultaneously provides reference；
2) make the time synchronization between master clock node；
3) measurement differed between a kind of master clock node and calibration method, but also the measurement essence of this method can be not only provided
Degree can reach nanosecond rank.
Description of the drawings
Below according to drawings and examples, invention is further described in detail.
The structural schematic diagram for the measuring device that Fig. 1 is differed between the master clock node described in embodiment one；
Fig. 2 is the schematic diagram of the master clock node calibrating installation described in embodiment two；
The structural schematic diagram for the measuring device that Fig. 3 is differed between the master clock node described in embodiment five；
The structural schematic diagram for the measuring device that Fig. 4 is differed between the master clock node described in embodiment six；
The structural schematic diagram for the measuring device that Fig. 5 is differed between the master clock node described in embodiment seven；
The structural schematic diagram for the measuring device that Fig. 6 is differed between the master clock node described in embodiment eight.
In figure：
1, the first master clock node；101, the first host node；102, first from node；2, the second host node；3, second from
Node.
Specific implementation mode
Technical solution to further illustrate the present invention below with reference to the accompanying drawings and specific embodiments.
Embodiment one
As shown in Figure 1, the present embodiment includes a kind of device of the measurement method differed between the node using master clock, measure
Method includes：
S10：According to accurate clock synchronization protocol, m1, k (k >=2, k ∈ N) a master of m2, m3 ... mk are followed successively by number
A host node and at least one from node is established in clock node equipment；Wherein, k master clock node device includes one the
One master clock node, 1 equipment m1 and (k-1) a second master clock node device m2~m (k-1)；First master clock node 1 includes
First host node 101 and first is from node 102；Second master clock node includes the second host node 2 and second from node 3.First
It is followed successively by n1, n2, n3 ... n (k-1) (k >=2, k ∈ N), first from the number of node 102 and is equal to needs from the quantity of node 102
The sum of the quantity for the second master clock node for establishing from node 102 mapping relations with first, i.e., (k-1) (k >=2, k ∈ N)；
S20：By the first host node of internal controller 101 and first of 1 equipment of the first master clock node from node 102 it
Between first difference PM1, n (k-1)；Wherein, the first difference PM1, n (k-1)The phase-the first of=the first host node 101 is from node 102
Phase；
S30：Mapping relations are established from node 102 and the second host node 2 by first, obtain first from node 102 and second
The second difference P between host node 2N (k-1), mk；Wherein, the second difference PN (k-1), mk=the first has been established from the phase-of node 102
The phase of second host node 2 of mapping relations；PN (k-1), mkIn n (k-1) needed between mk meet be mapped to same PTP
The paths Slave：For example, number be n1 first from node 102 with number be m2 the second host node 2 establish mapping relations, compile
Number be the first of n2 be m3 with number from node 102 the second host node 2 establish mapping relations ... number is the of n (k-1)
One establishes mapping relations from node 102 with the second host node 2 for being mk is numbered.
S40：According to the first difference PM1, n (k-1)With the second difference PN (k-1), mk, the first master clock node 1 and is calculated
Third between two master clock nodes differs PM1, mk；Wherein, third differs PM1, mk=the first difference PM1, n (k-1)- the second difference
PN (k-1), mk, i.e.,：
PM1, mk=PM1, n (k-1)+PN (k-1), mk
N (k-1) in formula, which needs to meet between mk, is mapped to the paths same PTP Slave.
Specifically, it is contacted because can not directly be established between the first master clock node 1 and the second master clock node, this
The main thought of method is in first looking for contact with the first master clock node 1 and the direct foundation of the second master clock node
The area of a room, by seeking differing for the first master clock node 1 and intermediate quantity and differing for intermediate quantity and the second master clock node, so that it may
To obtain differing between the first master clock node 1 and the second master clock node.
Based on the above thinking, first according to by accurate clock synchronization protocol (Precision Time
Synchronization Protocol, abbreviation PTP protocol), 101 He of the first host node is established in the first master clock node 1
First from node 102, and the second host node 2 and second is also established in the second master clock node from node 3.In PTP protocol,
PTP Master modules are known as host node, and PTP Slave modules are known as from node.
Since the first host node 101 and first is located at from node 102 in same clock node equipment, so the first host node
101 and first can directly obtain from the first difference of node 102.
And first can establish mapping relations from node 102 with the second host node 2, and then acquire first from node 102 with
The second difference between second host node 2.
Thus, the first master clock node 1 and the second master clock can be calculated by the first difference and the second difference
Third difference between node.
In this present embodiment, when there is multiple second master clock nodes, each second host node 2 should be with one
One establishes mapping relations from node 102, and then ensures that multiple second differences can be obtained simultaneously, and then accelerates the fortune of third difference
Calculate speed.
Locking phase is mostly used in industry at present to restore to calculate differing between master clock node with the difference of counting method：It is logical first
Over recovery equipment recovers the clock signal of each master clock node, and each master clock node of counter measures is then utilized to restore
Difference between the clock signal gone out, to obtain the difference between master clock node；Restoration errors can be introduced during this
And measurement error, reduce the measurement accuracy of the difference between master clock node.And the master clock node used in the present embodiment it
Between difference measuring method, the form that High Precision Time Stamps are provided by using PTP protocol avoids these errors.
Embodiment two
In this present embodiment, by taking 5 master clock nodes as an example, using the PTP chips ACS9521 of DPSync series, one
ACS9521 chips include a PTP Master and two PTP Slave modules, and the internal structure of single master clock node is such as
Under：
As shown in Fig. 2, used 3 ACS9521 in the present embodiment, PTP Master modules have used a piece of, constitute 1
A first host node 101；PTP Slave modules have used 2, constitute 4 first from node 102.
After the host node locking reference clock (Refrence clock, abbreviation Rf) of m1,1pps is provided and gives PTP Slave moulds
In clock phase-locked loop (Clock phase locked loop, abbreviation Clock PLL) Clock PLL1 of block；Rf is directly by this
Signal is supplied to another clock phase-locked loop Clock PLL2 of PTP Slave modules, then using this signal as the slave section in m1
The local locked clock of point n1 and n2, the first host node 101 of such m1 and number is n1 first from node 102, m1 the
One host node 101 and number be n2 first between node 102 first difference just may be considered Clock PLL1 and
Difference P between the slave node of m1Clock PLL1, n (k-1), i.e. PM1, n (k-1)=PClock PLL1, n (k-1)(2≤k≤3, k ∈ N).
After the host node locking reference clock of m1, clock phase-locked loop (Clocks of the 1pps to PTP Slave modules is provided
Phase locked loop, abbreviation Clock PLL) in Clock PLL3；Rf directly provides such signal to PTP Slave moulds
Another clock phase-locked loop Clock PLL4 of block, then using this signal as when the local locking of the slave node n3 and n4 in m1
Clock, the first host node 101 of such m1 and number is n3 first from node 102, the first host node 101 of m1 and number be n4
First just may be considered the difference between the slave node of Clock PLL3 and m1 from the first difference between node 102
PClock PLL3, n (k-1), i.e. PM1, n (k-1)=PClock PLL3, n (k-1)(4≤k≤5, k ∈ N).
And in a piece of ACS9521, the difference P between Clock PLL1 and PTP Slave can be directly acquiredClock PLL1, n (k-1)The difference P of (2≤k≤3, k ∈ N) between Clock PLL3 and PTP SlaveClockPLL1, n (k-1)(4≤k≤5, k
∈N)。
The host node of the PTP Slave1 and m2 of m1 are established into logical connection, seek the second difference P between themN1, m2；
The host node of the PTP Slave2 and m3 of m1 are established into logical connection, seek the second difference P between themN2, m3；By the PTP of m1
The host node of Slave3 and m4 establishes logical connection, seeks the second difference P between themN3, m4；By the PTP Slave4 of m1 with
The host node of m5 establishes logical connection, seeks the second difference P between themN4, m5。
The third calculated between m1 and m2 differs Pm1,m2=PClock PLL1, n1+PN1, m2；
The third calculated between m1 and m3 differs Pm1,m3=PClock PLL1, n2+PN2, m3；
The third calculated between m1 and m2 differs Pm1,m4=PClock PLL3, n3+PN3, m4；
The third calculated between m1 and m2 differs Pm1,m5=PClock PLL3, n4+PN4, m5。
The synchronous calibration between node is done using common arithmetic mean method in the present embodiment, third is calculated and differs Pm1,m2、
Pm1,m3、Pm1,m4、Pm1,m5Arithmetic mean of instantaneous valueWith unalterable rules by arithmetic mean of instantaneous valueCompensate corresponding master clock
Node finally obtains the phase error between each master clock node after calibration.In other embodiments, it can also use other
Calibration algorithm is calibrated, such as determines median or weighted average etc..
In this present embodiment, final result of calculation be the output master clock 1pps between five nodes difference 15ns with
It is interior, it is believed that be mutually synchronized.And the GPS Synchronos methods used in the prior art, error are within 100ns.So adopting
With the calibrating installation described in the present embodiment, the synchronization accuracy between master clock node device is significantly improved.
The present invention measures the difference of each master clock node indirectly by introducing PTP protocol to master clock node, not only
The measurement differed between a kind of master clock node and calibration method can be provided, and the measurement accuracy of this method can reach nanosecond
Not, accurate phase difference data in real time provides advantageous sample for the synchronous correction of main clock node, to solve master clock node
Between stationary problem new mode is provided.
Embodiment three
A kind of measuring device differed between master clock node, including：
First master clock node, 1 equipment, for according to accurate clock synchronization protocol establish the first host node 101 and first from
Node 102, and calculate the first host node 101 and differed from first between node 102 with first；
(k-1) (k >=2, k ∈ N) a second master clock node device, for establishing second according to accurate clock synchronization protocol
Host node 2 and second makes first to establish mapping relations from node 102 and the second host node 2 from node 3, obtains first from section
Point 102 is differed with second between the second host node 2.
Computing module, for according to the first difference and the second difference, be calculated the first master clock node 1 and second it is main when
Third difference between clock node.
Example IV
The calibrating installation differed between a kind of master clock node, including the measurement dress that is differed between the master clock node of embodiment three
It sets；
Further include calibration module, for according to calibration algorithm, calibrate each master clock node, makes mutually identical between master clock
Step.Further, calibration module is specifically used for；
Calculate the arithmetic mean of instantaneous value of third difference；
Using the phase of the first host node 101 with calculate gained arithmetic mean of instantaneous value and as calibration phase；
The phase of each master clock node is adjusted according to calibration phase.
Embodiment five
In this present embodiment, first in the first master clock node 1 is less than the second master clock node from the quantity of node 102
Quantity.As shown in figure 3,1 equipment m1 of the first master clock node is set, there are one the first host node 101 and two first from node
102, second clock node device m2, m3, m4 are all provided with that there are one the second host node 2 and two second from node 3.
The PTP Master of the PTP Slave1 and m2 of m1 establish mapping relations, the PTP of the PTP Slave2 and m3 of m1
Master establishes mapping relations；And then the third that can be obtained between m1 and m2 differs PM1, m2Third phase between m1 and m3
Poor PM1, m3。
The PTP Master of the PTP Slave1 and m3 of m2 establish mapping relations, the PTP of the PTP Slave2 and m4 of m2
Master establishes mapping relations；And then the third that can be obtained between m2 and m3 differs PM2, m3Third phase between m2 and m4
Poor PM2, m4。
The PTP Master of the PTP Slave1 and m1 of m3 establish mapping relations, the PTP of the PTP Slave2 and m4 of m3
Master establishes mapping relations；And then the third that can be obtained between m3 and m1 differs PM3, m1Third phase between m3 and m4
Poor PM3, m4。
The PTP Master of the PTP Slave1 and m2 of m4 establish mapping relations, the PTP of the PTP Slave2 and m1 of m4
Master establishes mapping relations；And then the third that can be obtained between m4 and m2 differs PM4, m2Third phase between m4 and m1
Poor PM4, m1。
By calculating, such as：
PM1, m4=PM1, m3+PM3, m4
It can be obtained by the mutual difference of m1~m4 master clock nodes.
Embodiment six
In this present embodiment, first is equal to the second master clock from the quantity of node 102 and second from the sum of quantity of node 3
The quantity of node.As shown in figure 4,1 equipment m1 of the first master clock node is set, there are one the first host node 101 and one first from section
Point 102, second clock node device m2, m3, m4 are all provided with that there are one the second host node 2 and one second from node 3.In other realities
It applies in example, first is more than the quantity of the second master clock node from the quantity of node 102 and second from the sum of quantity of node 3.
The PTP Master of the PTP Slave1 and m2 of m1 establish mapping relations, so can obtain between m1 and m2
Three difference PM1, m2。
The PTP Master of the PTP Slave1 and m3 of m2 establish mapping relations, so can obtain between m2 and m3
Three difference PM2, m3。
The PTP Master of the PTP Slave1 and m1 of m3 establish mapping relations, so can obtain between m3 and m1
Three difference PM3, m1。
By calculating, such as：
PM1, m3=PM1, m2+PM2, m3
The third difference that node is mutual when can be obtained by m1~m4 master clocks.
Embodiment seven
The difference between this embodiment and the first embodiment lies in：
As shown in figure 5,1 equipment m1 of the first master clock node is set, there are two host nodes；Second clock node device m2~m
(k-1) in, some is set there are one host node, some set there are two, three even more host nodes.
Select a host node as the first host node 101 from two host nodes of m1, the time of m1 equipment is with first
Subject to the time of host node 101；Selected from m (k-1) (k >=2, k ∈ N) equipment a host node as m (k-1) equipment
Two host nodes 2, time of m (k-1) equipment are subject to time of the second host node 2.
Then the measurement that the third between m1 and m (k-1) differs is carried out according to the difference measuring method in embodiment one.
Embodiment eight
The difference between this embodiment and the first embodiment lies in：
As shown in fig. 6, the quantity of the second master clock node is that (k-1) is a, and from section in 1 equipment m1 of the first master clock node
The quantity of point is more than (k-1), and it is a from node that (k-1) identical with the quantity of the second master clock node is chosen from the slave node of m1
As first from node 102, then first is reflected from node 102 and the foundation of the second host node 2 according to the method in embodiment one
Relationship is penetrated, the third difference between each master clock node device is acquired.
" first " herein, " second " have no special meaning just for the sake of being distinguish in description.
It is to be understood that above-mentioned specific implementation mode is only that presently preferred embodiments of the present invention and institute's application technology are former
Reason, in technical scope disclosed in this invention, variation that any one skilled in the art is readily apparent that or
It replaces, should all cover within the scope of the present invention.
Claims (10)
1. the measurement method differed between a kind of master clock node, which is characterized in that including：
S10：According to accurate clock synchronization protocol, established in each master clock node at least one host node and it is at least one from
Node；
The master clock node includes the first master clock node and at least one second master clock node；
S20：Obtain the first master clock node the first host node and the first master clock node first from first between node
Difference；
S30：Establish mapping relations from the second host node of node and the second master clock node by first, obtain first from node and
The second difference between second host node；
S40：It is differed according to first difference and described second, the first master clock node and the second master clock node is calculated
Between third difference.
2. the measurement method differed between a kind of master clock node according to claim 1, which is characterized in that
In the S10：First from the second of node and the second master clock node is no less than the second master from the sum of quantity of node
The sum of quantity of clock node.
3. the measurement method differed between a kind of master clock node according to claim 2, which is characterized in that first from node
Quantity be equal to the second master clock node the sum of quantity.
4. the measurement method differed between a kind of master clock node according to claim 1, which is characterized in that
The S20 is specially：The first difference is obtained by the internal controller of the first master clock node device.
5. the measurement method differed between a kind of master clock node according to claim 1, which is characterized in that
The S40 is specially：
Third difference the+the second difference of the=the first difference.
6. the measuring device differed between a kind of master clock node, which is characterized in that including：
First master clock node device, for establishing the first host node and first from node according to accurate clock synchronization protocol, and
The first host node is calculated to differ from first between node with first；
At least one second master clock node device, for according to accurate clock synchronization protocol establish the second host node and second from
Node, and make first to establish mapping relations from node and the second host node, first is obtained between node and the second host node
Second difference；
Computing module, for according to the first difference and the second difference, the first master clock node and the second master clock section to be calculated
Third difference between point.
7. the calibration method between a kind of master clock node, which is characterized in that including any one of Claims 1 to 5 claim institute
The measurement method differed between the master clock node stated further includes：
S50：According to calibration algorithm, each master clock node is calibrated, makes to be mutually synchronized between master clock.
8. the calibration method between a kind of master clock node according to claim 7, which is characterized in that the S50 includes：
S501：Calculate the arithmetic mean of instantaneous value of third difference；
S502：Using the phase of the first host node and the arithmetic mean of instantaneous value and as calibration phase；
S503：The phase of each master clock node is adjusted according to calibration phase.
9. the calibrating installation differed between a kind of master clock node, which is characterized in that including the master clock node described in claim 6
Between the measuring device that differs；
Further include calibration module, for according to calibration algorithm, calibrating each master clock node, making to be mutually synchronized between master clock.
10. the calibrating installation differed between a kind of master clock node according to claim 9, which is characterized in that the calibration
Module is specifically used for；
Calculate the arithmetic mean of instantaneous value of third difference；
Using the phase of the first host node with calculate gained arithmetic mean of instantaneous value and as calibration phase；
The phase of each master clock node is adjusted according to calibration phase.
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| CN103166730A (en) * | 2013-03-13 | 2013-06-19 | 西北工业大学 | Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 |
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| CN102457346A (en) * | 2010-10-29 | 2012-05-16 | 中兴通讯股份有限公司 | Time synchronization realizing method and clock node |
| CN102148652A (en) * | 2011-02-17 | 2011-08-10 | 上海奇微通讯技术有限公司 | System and method for measuring network clock synchronization |
| CN103166730A (en) * | 2013-03-13 | 2013-06-19 | 西北工业大学 | Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 |
| CN103248471A (en) * | 2013-05-22 | 2013-08-14 | 哈尔滨工业大学 | Clock synchronization method based on PTP (Precision Time Protocol) and reflective memory network |
| CN105553598A (en) * | 2016-01-10 | 2016-05-04 | 北京航空航天大学 | Time-triggered Ethernet (TTE) clock compensation method based on M estimation robust regression |
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