CN115347965A - Time synchronization optimization method with cache mechanism based on improved moving average filtering - Google Patents
Time synchronization optimization method with cache mechanism based on improved moving average filtering Download PDFInfo
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Abstract
The invention relates to a time synchronization optimization method based on improved moving average filtering with a cache mechanism. Determining the equipment state of each controller by using a clock state decision algorithm, respectively sending and receiving a clock synchronization message with a hardware timestamp by using controllers serving as a master clock node and a slave clock node according to an IEEE1588 clock synchronization principle, establishing a cache table in the controllers, and maintaining and managing the serial number and the timestamp of the clock synchronization message; and the slave clock node calculates a clock deviation value according to an IEEE1588 clock synchronization principle, performs filtering processing on the clock deviation value by utilizing an improved moving average filtering algorithm, and finally corrects the local clock of the slave node controller by using a filtering result. The method solves the problem that the stability and the precision of the clock synchronization process are influenced due to congestion in the network and obvious delay generated by clock synchronization message transmission, improves the time synchronization precision among all controllers in the whole control system, and has wide application prospect.
Description
Technical Field
The invention belongs to the field of network communication, and particularly relates to a time synchronization optimization method based on improved moving average filtering with a cache mechanism.
Background
In industrial production, with the enlargement of industrial production scale and the improvement of complexity, the control requirements of practical application on an industrial control system are higher and higher, and an industrial ethernet distributed control system based on the switched ethernet technology is widely applied in the field of industrial control systems due to the advantages of high integration, high efficiency and contribution to remote centralized control.
In an industrial Ethernet distributed control system, each controller operates in a distributed network environment respectively, and the operation of the whole control system needs a uniform and accurate time standard, so that the controllers are coordinated to perform multi-task control. The IEEE1588 high-precision time synchronization standard defines a time synchronization protocol in an industrial control system, other clocks in a network can be synchronized to the most accurate clock by adopting an open-source IEEE1588 protocol to realize codes, and the accurate synchronization among all controllers in a distributed system is ensured.
However, with the increasing complexity of the industrial production technology, the parameters to be monitored and controlled in the industrial production process are continuously increased, the parameter data amount is increased by geometric multiples, and the mixed flow transmission of the monitoring parameter data and the control parameter data cooperated by the multiple controllers is gradually changed into a normal state. In the existing products and technologies, no matter the acquisition position of the timestamp of the IEEE1588 high-precision time synchronization method is improved, or various types of filtering processing are performed on the IEEE1588 high-precision time synchronization result, the method is established on the basis that the whole time synchronization process is stable and reliable, and the existing method is ineffective for the condition that the synchronization message is frequently delayed or even lost in the clock synchronization process.
Disclosure of Invention
Aiming at the defects in the prior art, the technical problem to be solved by the invention is to provide a time synchronization optimization method with a cache mechanism based on improved moving average filtering, which is mainly used for the precise synchronization among controllers in a distributed system under the condition that the synchronous messages are frequently delayed or even lost in the clock synchronization process when the network environment is very complex.
The invention adopts the technical scheme for realizing the purpose that: the time synchronization optimization method with the buffer mechanism based on the improved moving average filtering comprises the following steps:
the controller determines whether the current controller is a slave clock node or not according to a clock state decision algorithm;
when the controller is a slave clock node, internally caching and managing a serial number and a timestamp of a clock synchronization message; and obtaining a clock deviation value according to the serial number and the timestamp, filtering the clock deviation value by using a moving average filtering algorithm, and finally correcting the local clock of the current controller by using a filtering result.
The controller determines whether the current controller is a slave clock node according to a clock state decision algorithm, and the method comprises the following steps:
the controller with the minimum time sum is selected as a master clock node and other controllers are selected as slave clock nodes by calculating the transmission time sum of the current controller and other controllers in the network.
The controller establishes a plurality of buffer tables which are respectively used for maintaining and managing the serial number and the timestamp information of the received and sent clock synchronization messages and the corresponding relation among the clock synchronization messages.
The time when the clock synchronization message leaves and enters the MAC layer of the controller network interface card is adopted and recorded in the clock synchronization message in the form of hardware timestamp.
The moving average filtering algorithm comprises the following steps:
by applying the calculated clock Offset value Offset new And stored average value of historical clock deviation values
And standard deviation delta offset Comparing, checking whether the clock deviation value is in
Within the range;
if yes, executing the next step; otherwise, discarding the clock deviation adjustment value of this time, and exiting the clock adjustment of this time.
The moving average filtering algorithm further comprises:
selecting a set window size M, and calculating the Offset value of the current clock new Average value of continuous M historical clock deviation values inside
For using average values
The local clock of the slave node controller is modified.
A time synchronization optimization method with a buffer mechanism based on improved moving average filtering is used for synchronization among controllers in a distributed system.
The time synchronization optimization terminal with the buffer mechanism based on the improved moving average filtering comprises:
the master-slave clock node judgment module is used for determining whether the current controller is a slave clock node according to a clock state decision algorithm;
the synchronous optimization module is used for internally caching and managing the serial number and the timestamp of the clock synchronous message when the controller is a slave clock node; and obtaining a clock deviation value according to the serial number and the timestamp, filtering the clock deviation value by using a moving average filtering algorithm, and finally correcting the local clock of the current controller by using a filtering result.
A time synchronization optimization device comprises a memory and a processor; the memory for storing a computer program; the processor is configured to implement the time synchronization optimization method based on the improved moving average filtering with the cache mechanism when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method for time synchronization optimization with a caching mechanism based on improved moving average filtering.
The invention is used for realizing a time synchronization optimization method with a cache mechanism based on improved moving average filtering. It has the following advantages:
1. the stability is high. The method solves the problem that the clock synchronization can not be finished according to the IEEE1588 clock synchronization principle because the transmission of the clock synchronization message generates obvious delay due to congestion in a network by caching the serial number and the timestamp information of the clock synchronization message in the clock synchronization management process. The stability of time synchronization among all controllers in the whole control system is improved.
2. The clock synchronization precision is high. The method of the invention removes error interference caused by network delay jitter and other reasons by using an improved moving average filtering algorithm for the calculated clock deviation value, so that the clock deviation value after filtering can reflect the clock deviation between the master clock node controller and the slave clock node controller, thereby improving the time synchronization precision between all controllers in the whole control system.
3. The universality is strong. The method is based on mature high-precision clock synchronization technology and data processing technology, the technical difficulty for realizing the method is small, the technical development is mature, the complexity for realizing the system is low, only the control software in the controller needs to be improved, a hardware system platform does not need to be changed, the universality is high, and the method is easy to realize.
Drawings
FIG. 1 is an overall flow diagram of the method of the present invention;
FIG. 2 is a block diagram of a control network system constructed according to an exemplary embodiment of the method of the present invention;
FIG. 3 is a schematic diagram of the time synchronization message timestamp generation location of the method of the present invention;
FIG. 4 is a schematic diagram of the IEEE1588 clock synchronization principle;
FIG. 5 is a master clock node controller cache table of the method of the present invention;
FIG. 6 is a slave clock node controller cache table of the present invention method.
FIG. 7 is a detailed flow chart of an improved moving average filtering algorithm in the method of the present invention
Detailed Description
The invention is described in further detail below with reference to the drawings and the examples.
A time synchronization optimization method with a cache mechanism based on improved moving average filtering is used for precise synchronization among controllers in a distributed system and comprises the following steps:
each controller determines the equipment state according to a clock state decision algorithm, the controllers serving as the master clock node and the slave clock node respectively send and receive clock synchronization messages with hardware timestamps according to the IEEE1588 clock synchronization principle, and cache and manage the sequence numbers and the timestamps of the clock synchronization messages; and then the slave clock node calculates a clock deviation value according to an IEEE1588 clock synchronization principle, the clock deviation value is filtered by using an improved moving average filtering algorithm, and finally the local clock of the slave node controller is corrected by using a filtering result.
All controllers in the network determine the equipment state according to a clock state decision algorithm, and the specific process is as follows: the controller A in the network broadcasts a request message to other controllers, the other controllers immediately reply after receiving the request message broadcast by the controller A, the controller A respectively records the time interval from the beginning of broadcasting the request message to the time when the other controllers reply the message, and accumulates and calculates all the time sum; then other controllers in the network carry out the processes one by one, the time sum calculated by each controller in the network is compared, the controller with the minimum time sum is selected as a master clock node, and other controllers are used as slave clock nodes.
And the master clock node transmits a clock message according to an IEEE1588 clock synchronization principle, and records the time when the clock synchronization message leaves the MAC layer of the network interface card of the controller in the clock synchronization message in a hardware timestamp mode. And the slave clock node receives the clock synchronization message according to the IEEE1588 clock synchronization principle and records and stores the time when the MAC layer of the network interface card of the controller receives the clock synchronization message.
The controller is internally provided with a plurality of cache tables which are respectively used for storing and managing the serial numbers and the timestamp information of the received and sent clock synchronization messages and the corresponding relation among the clock synchronization messages.
And the slave clock node controller calculates a clock deviation value with the master clock according to an IEEE1588 clock synchronization principle, then performs filtering processing on the clock deviation value by utilizing an improved moving average filtering algorithm, and corrects the local clock of the slave node controller by using a filtering result. The specific process of improving the moving average filtering algorithm mainly comprises the following two steps:
the first step is as follows: calculating an average of historical clock bias values stored from clock nodes
Sum standard deviation delta offset Calculating the clock Offset value Offset of the time obtained from the node new And historical clock deviation value average
Comparing, if the current clock deviation value Offset new In that
Within range, then store the new clock Offset value Offset new Discarding the oldest clock deviation value in the stored historical clock deviation value record; otherwise, discarding the clock deviation value Offset calculated this time new The process of improving the moving average filter algorithm is ended, and this clock skew adjustment is abandoned.
The second step is that: selecting a proper window size M according to the actual network jitter condition, and calculating the clock Offset value Offset including the current time new Average value of continuous M historical clock deviation values
And using the mean value
The local clock of the slave node controller is modified.
Fig. 1 is an overall flowchart of the method of the present invention, in which a clock state decision algorithm is first used to determine the states of each controller device, controllers serving as master and slave clock nodes respectively send and receive clock synchronization messages with hardware timestamps according to the IEEE1588 clock synchronization principle, and buffer and manage the sequence numbers and timestamps of the clock synchronization messages; and then, the slave clock node calculates a clock deviation value according to an IEEE1588 clock synchronization principle, performs filtering processing on the clock deviation value by utilizing an improved moving average filtering algorithm, and finally corrects the local clock of the slave node controller by using a filtering result.
The method of the invention uses the improved sliding average filtering algorithm to buffer and manage the serial number and the timestamp information of the clock synchronization message and the calculated clock deviation value in the clock synchronization process, solves the problem that the clock synchronization message transmission generates obvious delay due to congestion in the network, thereby influencing the stability and the precision of the clock synchronization process, improves the time synchronization precision among all controllers in the whole control system, and then specifically introduces the implementation process of all steps of the method by combining with the implementation example shown in fig. 2.
The method comprises the steps of firstly determining the equipment state according to a clock state decision algorithm, namely sequentially and respectively calculating the time sum of data transmission from each controller to other controllers in a control system network, selecting the controller with the minimum time sum as a master clock node, and using the other controllers as slave clock nodes. The time for each controller to propagate data to the other controllers in FIG. 2 is shown in the following table:
TABLE 1
The total time of the controllers 1-5 transmitting data to other controllers in the table is 41ms,34ms,39ms and 39ms. The controller 3 has the least total time for transmitting data to the rest controllers, so that the controller is used as a master clock node in the control system network, and the rest controllers are used as slave clock nodes.
In the conventional IEEE1588 open source implementation protocol, the application layer t is shown in figure 3 A The acquired software timestamp is used as timestamp information in the time synchronization message, but the timestamp acquired at the position is easily influenced by the delay and jitter of a protocol stack, so the time synchronization precision is relatively low; and some improved IEEE1588 open source implementation protocols move down the time stamp acquisition position to the network layer t N Although the influence of protocol stack delay and jitter on the timestamp accuracy can be effectively reduced, the influence of network transmission delay and jitter still exists; at the interface t of MAC layer and physical layer M The obtained time stamp can truly reflect the time information of the time synchronization message, the precision of the time stamp is highest, but the time stamp needs to be supported by the aid of controller hardware, and along with the continuous development of the digitization technology, most of controllers on the market support the related functions of IEEE1588 hardware time stamps, so that the master node and the slave node in the method are selected at the interface t between the MAC layer and the physical layer M And recording and storing the acquired hardware timestamp into the time synchronization message as the time information of the time synchronization message entering and leaving the controller.
According to the schematic diagram of the IEEE1588 clock synchronization principle shown in fig. 4, 4 pieces of time information, which are respectively the time t when the Sync message leaves the master clock node, need to be acquired in a complete time synchronization process 1 And the time t of receiving the clock synchronization Sync message from the clock node 2 The time t when the master clock node receives a Req request message sent by the slave clock and then replies to a Resp message of the slave clock node 3 And time t when Resp message is received from clock node 4 In the traditional application process, the monitoring and control data volume in the control system network is relatively small, the clock synchronization message transmission between the master clock node and the slave clock node is stable, the transmission delay is relatively small, and t 1 、t 2 、t 3 、t 4 The four moments are accurately and stably acquired, and the clockThe synchronization accuracy is also relatively high. However, with the increasing complexity of the industrial production process, the amount of monitoring control data increases rapidly, and the time synchronization process is easily interfered by the monitoring control data to cause delay and jitter of clock synchronization message transmission, so that the Resp message received from the clock node is not the message of the current synchronization process but the Resp message of the synchronization process of the next or even longer time later, thereby seriously affecting the clock synchronization precision. Therefore, the method of the invention stores and manages the serial numbers and the timestamp information of the received and sent clock synchronization messages by establishing a plurality of cache tables in the controller, thereby ensuring t used for calculating the clock deviation value 1 、t 2 、t 3 、t 4 The clock synchronization process is stable at the same time in the clock synchronization process, and the clock synchronization precision between the controllers is improved.
The cache table managed and maintained by the master clock node controller is shown in FIG. 5, t 1 The time cache table mainly manages and maintains the sequence number of the Sync message transmitted by the master clock node and the time information of the Sync message leaving the master clock node, t 3 The time buffer table mainly manages and maintains the serial number of the Resp message transmitted by the master clock node, the time information of the Resp message leaving the master clock node and the target node information. The cache table managed and maintained by the slave clock node controller is shown in FIG. 6, t 2 The time cache table mainly manages and maintains the serial number of the Sync message received from the clock node and the time information of the Sync message reaching the slave clock node, t 4 The time buffer table mainly manages and maintains the serial number of Resp message received from the clock node and the time information of Resp message arriving at the slave clock node, and according to the IEEE1588 clock synchronization principle, t is in the same clock synchronization process 1 And t 2 The time is the time when the same Sync message leaves the master clock node and arrives at the slave clock node, so the corresponding serial numbers are completely the same, namely the serial numbers of the Sync message, and the same t 3 And t 4 The sequence number corresponding to the moment is also completely the same as the sequence number of the Resp message, but is t 1 And t 2 The serial numbers of the Sync messages corresponding to the moments are different, so that the slave clock node needs to additionally maintain and manage one piece of slave clock nodeAnd the buffer table corresponds the sequence number of the Resp message and the sequence number of the Sync message in the same clock synchronization process.
Calculating the clock Offset value Offset of the slave clock node and the master clock node according to the IEEE1588 clock synchronization principle new Then, the clock offset value is filtered by using an improved moving average filtering algorithm, a specific flow of the improved moving average filtering algorithm is shown in fig. 7, which will be described in detail with reference to an implementation example, and the improved moving average filtering algorithm is mainly divided into the following two steps:
the first step is as follows: firstly according to the formula
Calculating an average of historical clock bias values stored from nodes
Offset i Representing the stored ith historical clock bias value, wherein an appropriate parameter N value is selected according to the size of the internal storage space of the controller and the processing capacity, in this example N =10; then according to the formula
δ offset > 0 calculating the standard deviation delta of the stored historical clock deviation record value offset Then, the clock Offset value Offset calculated in the clock synchronization process is detected new Whether or not to be at
Within the range, if the current clock deviation value Offset new In that
Within range, then store the new clock Offset value Offset new Discarding the oldest clock deviation value in the stored historical clock deviation value record, and preparing for the next step; otherwise, the clock Offset value Offset calculated this time is discarded new Ending the process of improving the moving average filter algorithm and discarding the clock biasAnd (4) adjusting the difference.
The second step is that: according to the formula
The calculation comprises the clock deviation value Offset of the time new Average value of continuous M historical clock deviation values
The size M of the sliding average window can be selected to be a proper window size M according to the actual network jitter condition, and M =5 is selected in the example; final using the mean value
The local clock of the slave node controller is modified.
Claims (10)
1. The time synchronization optimization method based on the improved moving average filtering with the buffer mechanism is characterized by comprising the following steps of:
the controller determines whether the current controller is a slave clock node or not according to a clock state decision algorithm;
when the controller is a slave clock node, internally caching and managing a serial number and a timestamp of a clock synchronization message; and obtaining a clock deviation value according to the serial number and the timestamp, filtering the clock deviation value by using a moving average filtering algorithm, and finally correcting the local clock of the current controller by using a filtering result.
2. The method for optimizing time synchronization based on improved moving average filtering with a cache mechanism according to claim 1, wherein the controller determines whether the current controller is a slave clock node according to a clock state decision algorithm, comprising the following steps:
the controller with the minimum time sum is selected as a master clock node and other controllers are selected as slave clock nodes by calculating the transmission time sum of the current controller and other controllers in the network.
3. The method according to claim 1, wherein a plurality of buffer tables are established inside the controller for maintaining and managing sequence numbers and timestamp information of received and transmitted clock synchronization packets, and corresponding relationships between clock synchronization packets.
4. The time synchronization optimization method based on the improved moving average filtering with the buffering mechanism according to claim 1 or 3, characterized in that the time when the clock synchronization message leaves and enters the MAC layer of the controller network interface card is recorded in the clock synchronization message in the form of hardware timestamp.
5. The method for optimizing time synchronization based on improved moving average filtering with buffer mechanism according to claim 1, wherein the moving average filtering algorithm comprises the following steps:
by applying the calculated clock Offset value Offset new And average value of stored historical clock deviation values
Sum standard deviation delta offset Comparing, checking whether the clock deviation value is in
Within the range;
if yes, executing the next step; otherwise, discarding the clock deviation adjustment value of this time, and exiting the clock adjustment of this time.
6. The method for optimizing time synchronization based on improved moving average filtering with buffer mechanism according to claim 5, wherein the moving average filtering algorithm further comprises:
selecting a set window size M, and calculating a clock deviation value Offset including the time new Average value of continuous M historical clock deviation values
For using average values
The local clock of the slave node controller is modified.
7. The method for optimizing time synchronization based on improved moving average filtering with buffer mechanism according to claim 1, wherein: for synchronization between controllers in a distributed system.
8. The time synchronization optimization terminal based on the improved moving average filtering with the buffer mechanism is characterized by comprising the following components:
the master-slave clock node judgment module is used for determining whether the current controller is a slave clock node according to a clock state decision algorithm;
the synchronous optimization module is used for internally caching and managing the serial number and the timestamp of the clock synchronous message when the controller is a slave clock node; and obtaining a clock deviation value according to the serial number and the timestamp, filtering the clock deviation value by using a moving average filtering algorithm, and finally correcting the local clock of the current controller by using a filtering result.
9. A time synchronization optimization apparatus, comprising a memory and a processor; the memory for storing a computer program; the processor, configured to, when executing the computer program, implement the method for time synchronization optimization based on improved moving average filtering with a caching mechanism according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when being executed by a processor, carries out a method for improved moving average filtering based time synchronization optimization with a caching mechanism according to any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116700094A (en) * | 2023-06-21 | 2023-09-05 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100218019A1 (en) * | 2007-10-09 | 2010-08-26 | St-Ericsson Sa | Non-recursive adaptive filter for predicting the mean processing performance of a complex system's processing core |
| CN102122995A (en) * | 2010-12-20 | 2011-07-13 | 北京航空航天大学 | Wireless distributed automatic test system (WDATS) |
| CN103166730A (en) * | 2013-03-13 | 2013-06-19 | 西北工业大学 | Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 |
| US20160119070A1 (en) * | 2013-05-20 | 2016-04-28 | Zte Corporation | Time Correction Method and Apparatus for Slave Clock Device |
| CN108460731A (en) * | 2017-03-16 | 2018-08-28 | 中国人民解放军海军航空工程学院青岛校区 | A method of it eliminating scenery picture in networking flight simulation and shakes |
| CN112350794A (en) * | 2019-08-09 | 2021-02-09 | 诺基亚通信公司 | End-to-end transparent clock and method for forwarding PTP (precision time protocol) message |
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100218019A1 (en) * | 2007-10-09 | 2010-08-26 | St-Ericsson Sa | Non-recursive adaptive filter for predicting the mean processing performance of a complex system's processing core |
| CN102122995A (en) * | 2010-12-20 | 2011-07-13 | 北京航空航天大学 | Wireless distributed automatic test system (WDATS) |
| CN103166730A (en) * | 2013-03-13 | 2013-06-19 | 西北工业大学 | Method for synchronizing time in wireless ad hoc network based on protocol of institute of electrical and electronic engineers (IEEE) 1588 |
| US20160119070A1 (en) * | 2013-05-20 | 2016-04-28 | Zte Corporation | Time Correction Method and Apparatus for Slave Clock Device |
| CN108460731A (en) * | 2017-03-16 | 2018-08-28 | 中国人民解放军海军航空工程学院青岛校区 | A method of it eliminating scenery picture in networking flight simulation and shakes |
| CN112350794A (en) * | 2019-08-09 | 2021-02-09 | 诺基亚通信公司 | End-to-end transparent clock and method for forwarding PTP (precision time protocol) message |
Non-Patent Citations (1)
| Title |
|---|
| 刘明哲等: ""基于IEEE1588的时钟同步算法软件实现"", 《仪器仪表学报》, 30 December 2006 (2006-12-30) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116700094A (en) * | 2023-06-21 | 2023-09-05 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
| CN116700094B (en) * | 2023-06-21 | 2024-03-01 | 哈尔滨博尼智能技术有限公司 | Data driving control system |
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