CN103138768A - Apparatus and method for encoding and decoding channel in a communication system using low-density parity-check codes - Google Patents

Abstract

An apparatus and method for generating a parity-check matrix of a Low-Density Parity-Check (LDPC) code are provided. Parameters for designing the LDPC code are determined, and a first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix, and a third parity-check matrix is created by rearranging the second parity-check matrix.

Description

The equipment of the channel in the Code And Decode communication system and method

The application be that February 18, application number in 2009 are 200980105340.8 the applying date, denomination of invention divides an application for the application for a patent for invention of " being used for equipment and the method for channel that Code And Decode uses the communication system of low-density checksum check code ".

Technical field

Relate generally to of the present invention uses the communication system of low-density checksum inspection (LDPC) code, more specifically, relates to channel encoding/decoding device and method for generation of the LDPC code of specific type.

Background technology

In wireless communication system, due to multiple noise, fade-out and intersymbol interference (ISI) in channel, link performance significantly reduces.Therefore, in order to realize the high-speed digital communication system of demanding data throughout and reliability, for example next generation mobile communication, digital broadcasting and mobile Internet, need a kind of technology be used to overcoming noise, decline and ISI of exploitation.Recently, to relating to the use of error correcting code in improving communication reliability by the information that the efficient recovery distortion is arranged, conduct in-depth research.

At first the LDPC code is proposed in nineteen sixties by Gallager, and because it can not be by the realization of the complexity that technology solved in past, the LDPC code is not fully utilized always.Yet the Turbo code by Berrou, Glavieux and Thitimajshima found in 1993 shows the performance near the Shannon channel limit.Like this, to repeat decoding with based on the chnnel coding of figure and the performance of Turbo code and the analysis of characteristic are studied.Due to this research, the LDPC code was restudied in later stage nineteen nineties, if proof is by using based on scheming the repeat decoding of (sum-product) algorithm on (special circumstances of factor graph) and long-pending corresponding to the Tanner of LDPC code, the LDPC code is decoded, and the LDPC code has the performance near the Shannon channel limit.

The LDPC code represents with the diagrammatic representation technology usually, based on the method for graph theory, algebraical sum probability theory, can analyze a lot of characteristics.Usually, the graph model of channel code is useful to the explanation of code.By the information on the bit of coding being mapped to the summit (vertex) in figure and passing through the limit (edge) of the relationship map between bit to figure, might consider following communication network: the summit exchanges predetermined message by the limit in this communication network.This makes the decoding algorithm that might derive nature.The decoding algorithm of for example, deriving from the grid (trellis) that is used as a kind of figure can comprise known Viterbi algorithm and Bahl, Cocke, Jelinek and Raviv(BCJR) algorithm.

The LDPC code is normally defined the parity check matrix, can utilize bipartite graph (bipartite graph) expression, and this bipartite graph refers to Tanner figure.In consisting of the bipartite graph summit of figure, figure is divided into two different types, and the LDPC code is represented by the bipartite graph that the summit forms, some bipartite graph called after variable nodes, other bipartite graph called after inspection node.Variable node is mapped to the bit of coding one to one.

With reference to figure 1 and Fig. 2, explanation is used for the graphical representation method of LDPC code.

Fig. 1 illustrates the parity check matrix H of the LDPC code that is comprised of 4 row 8 row ₁Example.With reference to figure 1, because the number that is listed as is that 8, LDPC code produces 8 long code words (codeword), row are mapped to the bit of 8 codings.

Fig. 2 is the H of explanation corresponding to Fig. 1 ₁The figure of Tanner figure.

With reference to figure 2, the Tanner figure of LDPC code is by 8 variable node x ₁(202), x ₂(204), x ₃(206), x ₄(208), x ₅(210), x ₆(212), x ₇(214) and x ₈(216) and 4 check that node 218,220,222 and 224 forms.The parity check matrix H of LDPC code ₁I row and the capable variable node x that is mapped to respectively of j _iWith j inspection node.In addition, value 1, that is, nonzero value is positioned at the parity check matrix H of LDPC code ₁I row and the capable cross one another point of j on, point out the variable node x on Tanner figure as shown in Figure 2 _iAnd there is the limit between j inspection node.

In the Tanner of LDPC code figure, variable node and inspection degree of node are defined as and are connected to each number on the limit of node separately, and degree equals the number corresponding to the input of the non-zero in the column or row of node related in the parity check matrix of LDPC code.For example, in Fig. 2, variable node x ₁(202), x ₂(204), x ₃(206), x ₄(208), x ₅(210), x ₆(212), x ₇(214) and x ₈(216) degree is respectively 4,3,3,3,2,2,2 and 2, checks that node 218,220,222 and 224 degree are respectively 6,5,5 and 5.In addition, the parity check matrix H of Fig. 1 ₁Row (it is corresponding to the variable node of Fig. 2) in the number of non-zero input, equal its degree 4,3,3,3,2,2,2 and 2.The parity check matrix H of Fig. 1 ₁Row (it is corresponding to the inspection node of Fig. 2) in the number of non-zero input, equal its degree 6,5,5 and 5.

For the degree of node of expressing the LDPC code distributes, the ratio of the number of the variable node of degree-i(degree-i) and the total number of variable node is defined as f _i, degree-j(degree-j) check the number of node and check that the ratio of the total number of node is defined as g _jFor example, for the LDPC code corresponding to Fig. 1 and Fig. 2, f ₂=4/8, f ₃=3/8, f ₄=1/8, when i ≠ 2,3,4 o'clock f _i=0; g ₅=3/4, g ₆=1/4, as j ≠ 5,6 o'clock g _j=0.When the length of LDPC code, that is, the number of row is defined as N, and the number of row is defined as N/2, and density such as formula (1) with the non-zero input in the whole parity check matrix that above-mentioned degree distributes calculate.

$\frac{2f_{2}N+3f_{3}N+4f_{4}N}{N\·N/2}=\frac{5.25}{N}...\left(1\right)$

In formula (1), when the N increase, in the parity check matrix, ' 1 ' density reduces.Normally, for the LDPC code, because the density of code length N and non-zero input is inversely proportional to, the LDPC code with large N has the density of low-down non-zero input.Word in the title of LDPC code ' low-density ' originates from above-mentioned relation.

Next, with reference to figure 3, will the characteristic of the parity check matrix of the structurized LDPC code of using in the present invention be described.Fig. 3 has schematically illustrated the LDPC code that adopts as standard technique in second generation digital video broadcast satellite transmission (DVB-S2), DVB-S2 is one of European standards for digital broadcasting.

In Fig. 3, N ₁Represent the length of LDPC code word, K ₁The length of information word (information word) is provided, and (N ₁-K ₁) odd-even check length is provided.In addition, integer M ₁Be determined to satisfy q=(N with q ₁-K ₁)/M ₁Preferably, K ₁/ M ₁It is also preferably integer.

With reference to figure 3, the parity check part in the parity check matrix, that is, and K ₁Row to the (N ₁-l) row, structure have the double diagonal line shape.Therefore, distribute as the degree that lists corresponding to the parity check part, all row degree of having ' 2 ' are except last row degree of having ' 1 '.

In the parity check matrix, message part, namely, the 0th row are to (K ₁-1) structure of row utilizes following rule to draw.

Rule 1: by will be corresponding to the K of the information word in the parity check matrix ₁Individual row form each by M ₁Be listed as a plurality of groups that form, produce K altogether ₁/ M ₁Individual row group (column group).Formation belongs to the method for the row of each row group and follows following regular 2.

Rule 2: at first determine i row group each the 0th position of ' 1 ' that is listed as (i=1 wherein ..., K ₁/ M ₁).When i row group each the 0th row degree by D _iDuring expression, if be that the hypothesis on location of 1 row is

It is the position of 1 row (K=1,2 ..., D _i) the j of i row group row (j=1 wherein, 2 ..., M ₁-1), define as formula (2).

$R_{i,j}^{\left(k\right)}=R_{i,(j-1)}^{\left(k\right)}+q\mathrm{mod}(N_1-k_1)$

K=1,2,...,D _i,i=1,...,K ₁/M ₁,j=1,...,M ₁-1.......(2)

According to above-mentioned rule, it should be understood that belong to i row group (i=1 wherein ..., K ₁/ M ₁) the degree of row all equal D _iFor the better structure of the DVB-S2LDPC code of storage information on the parity check matrix of understanding according to above-mentioned rule, will the following concrete example of explanation.

As concrete example, for N ₁=30, K ₁=15, M ₁=5 and q=3, the 0th three sequences classifying the locational information of 1 row as can be expressed as follows in 3 row groups.Herein, this sequence is called " weight-1 position sequence " for convenience

$R_{\mathrm{1,0}}^{\left(1\right)}=0,$ $R_{\mathrm{1,0}}^{\left(2\right)}=1,$ $R_{\mathrm{1,0}}^{\left(3\right)}=2$

$R_{\mathrm{2,0}}^{\left(1\right)}=0,$ $R_{\mathrm{2,0}}^{\left(2\right)}=11,$ $R_{\mathrm{2,0}}^{\left(3\right)}=13$

$R_{\mathrm{3,0}}^{\left(1\right)}=0,$ $R_{\mathrm{3,0}}^{\left(2\right)}=10,$ $R_{3,0}^{\left(3\right)}=14$

About weight-1 position sequence of the 0th row in each row group, for each row group only corresponding position sequence can be expressed as follows.For example:

0?1?2

0?11?13

0?10?14

In other words, i weight-1 position sequence that i is capable sequentially represents in i row group the information of the position that is 1 row.

Utilization is corresponding to the information of concrete example and rule 1 and rule 2, by forming the parity check matrix, can produce the LDPC code that has with the DVB-S2LDPC code same concept of Fig. 4.

Known DVB-S2LDPC code according to rule 1 and rule 2 designs can utilize structurized shape effectively to be encoded.Each step in utilizing the method for carrying out the LDPC coding based on the parity check matrix of DVB-S2 will be described as follows by the mode of example.

In following, as concrete example, to N ₁=16200, K ₁=10800, M ₁=360 and the processing of encoding of the DVB-S2LDPC code of q=15.For convenience, has K ₁The information bit of length is expressed as

Has (N ₁-K ₁) Parity Check Bits of length is expressed as

The following initialization Parity Check Bits of step 1:LDPC encoder:

${\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">p</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">p</figure-callout>}}_1=...=p_{N_1-K_1-1}=0$

Step 2:LDPC encoder reads information on row from the 0th weight-1 position sequence outside the sequence of the storage of expression parity check matrix, and in this row, 1 is arranged in the row group.

0?2084?1613?1548?1286?1460?3196?4297?2481?3369?3451?4620?2622

${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(1\right)}=0,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(2\right)}=2048,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(3\right)}=1613,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(4\right)}=1548,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(5\right)}=1286,$

${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(6\right)}=1460,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(7\right)}=3196,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(8\right)}=4297,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(9\right)}=2481,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(10\right)}=3369,$

${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(11\right)}=3451,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(12\right)}=4620,$ ${\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{1,0}}^{\left(13\right)}=2622.$

The information that the utilization of LDPC encoder is read and first information bit i ₀, upgrade concrete Parity Check Bits p according to formula (3) _xHerein, x represents

Value, k=1 wherein, 2 ... 13.

${\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">p</figure-callout>}}_0={\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">p</figure-callout>}}_0\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{2084}=p_{2064}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{1613}=p_{1613}\&CirclePlus;i_0$

$p_{1548}=p_{1548}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{1286}=p_{1286}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{1460}=p_{1460}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0$

$p_{3196}=p_{3196}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{4297}=p_{4297}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{2481}=p_{2481}\&CirclePlus;i_0---\left(3\right)$

$p_{3369}=p_{3369}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{3451}=p_{3451}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0,$ $p_{4620}=p_{4620}\&CirclePlus;i_0,$

$p_{2622}=p_{2622}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_0$

In formula (3),

Also can be expressed as

The expression binary addition.

Step 3:LDPC encoder is at first for i ₀After 359 information bit i _m(m=1 wherein, 2 ... 359) find out the value of formula (4).

{x+(mmodM ₁)×q}mod(N ₁-K ₁)，M ₁=360，m=1,2,...,359……（4）

In formula (4), x represents

Value, k=1 wherein, 2 ..., 13.Should be noted that formula (4) has the concept identical with formula (2).

Next, the LDPC encoder utilizes the value find in formula (4) to carry out the computing that is similar to formula (3).That is, the LDPC encoder is i _mUpgrade

For example, work as m=1, that is, be i ₁, the LDPC encoder upgrades Parity Check Bits

Such as in formula (5) definition.

$p_{15}=p_{15}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{2099}=p_{2099}\&CirclePlus;i_1,$ $p_{1628}=p_{1628}\&CirclePlus;i_1$

$p_{1563}=p_{1563}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ ${\mathrm{<figure-callout\; id="1301"\; label="p"\; filenames="HDA00002773947700111.png"\; state="\{\{state\}\}">p</figure-callout>}}_{1301}={\mathrm{<figure-callout\; id="1301"\; label="p"\; filenames="HDA00002773947700111.png"\; state="\{\{state\}\}">p</figure-callout>}}_{1301}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{1475}=p_{1475}\&CirclePlus;i_1$

$p_{3211}=p_{3211}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{4312}=p_{4312}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{2496}=p_{2496}\&CirclePlus;i_1---\left(5\right)$

$p_{3384}=p_{3384}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{3466}=p_{3466}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$ $p_{4635}=p_{4635}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1,$

$p_{2637}=p_{2637}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="HDA00002773947700021.png,HDA00002773947700031.png"\; state="\{\{state\}\}">i</figure-callout>}}_1$

Should be noted that in formula (5) q=15.The LDPC encoder with identical method as implied above for m=1,2 ..., 359 carry out above-mentioned processing.

Step 4: in step 2, the LDPC encoder is the 361st information bit i ₃₆₀Read the 1st weight-1 position sequence (k=1,2 ..., 13) information, and upgrade concrete p _x, wherein x represents

The LDPC encoder by application of formula (4) similarly to i ₃₆₀Rear ensuing 359 information bits upgrade $P_{\{x+\left({m\mathrm{mod}M}_1\right)\&times;q\}\mathrm{mod}(N_1-K_1)},$ m=361,362,...，719。

Step 5:LDPC encoder is to all groups (each has 360 information bits) repeating step 2,3 and 4.

Step 6:LDPC encoder utilizes formula (6) finally to determine Parity Check Bits.

$p_i=p_i\&CirclePlus;p_{i-1},i=\mathrm{1,2},...,N_1-K_1-1---\left(6\right)$

The Parity Check Bits of formula (6) is the Parity Check Bits through the LDPC coding.

As mentioned above, in DVB-S2, the LDPC encoder is carried out the LDPC coding by step 1 to the method for step 6.

The ring property of the performance of known LDPC code and Tanner figure (cycle characteristics) is closely related.Particularly, when known number when short (short-length) ring of length is very large in Tanner figure by experiment, can degenerate by generation performance.Like this, to have high performance LDPC code in order designing, should to consider the ring property of Tanner figure.

Yet, do not propose to be used for the method that design has the DVB-S2LDPC code of good ring property at present.For the DVB-S2LDPC code, when the optimization of the ring property of not considering Tanner figure, observe error floor phenomenon (error floor phenomenon) when high s/n ratio (SNR).For those reasons, need a kind of method can effectively improve ring property when design has the LDPC code of DVB-S2 structure.

Summary of the invention

Made the present invention solving the problems referred to above and/or shortcoming at least, and following at least beneficial effect is provided.Therefore, an aspect of of the present present invention provides channel encoding/decoding device and method, be used in the communication system of utilizing the LDPC code, design is based on the parity check matrix of standard circulation (quasi-cyclic) LDPC code of cycle arrangement (circulant permutation) matrix design, thus design DVB-S2LDPC code.

Another aspect of the present invention provides channel encoding/decoding device and method, is used in the communication system of utilizing the LDPC code, designs the parity check matrix of the LDPC code identical with the DVB-S2LDPC code with good Tanner figure characteristic.

According to an aspect of the present invention, provide the generation low-density checksum to check the method for the parity check matrix of (LDPC) code.Determined the parameter of design LDPC code.According to determined parameter, form the first parity check matrix of quasi-cyclic LDPC code.By removing the predetermined portions of the parity check part in the first parity check matrix, produce the second parity check matrix.Produce the 3rd parity check matrix by rearranging the second parity check matrix.

The method of the channel that is used for being coded in the communication system of using low-density checksum inspection (LDPC) code is provided according to a further aspect in the invention.Read the parity check matrix of storage.Utilize the parity check matrix of storage to carry out the LDPC coding to the signal that receives.The parity check matrix is divided into information word and parity check.When code check is 3/5, code word size is 16200, as following table institute formation parity check matrix with defining;

The method of the channel of decoding in the communication system of using low-density checksum inspection (LDPC) code is provided according to another embodiment of the invention.Extract the parity check matrix of LDPC code.Utilize the parity check matrix that extracts to carry out the LDPC decoding.The parity check matrix that extracts is divided into the parity check sum information word.When code check is 3/5, and code word size is 16200 o'clock, formation parity check matrix as defined in following table;

According to another aspect of the present invention, provide the equipment that is coded in the channel in the communication system of using low-density checksum inspection (LDPC) code.LDPC code parity check matrix extractor reads the parity check matrix of storage.The parity check matrix of LDPC encoder utilization storage carries out the LDPC-coding to the signal that receives.The parity check matrix is divided into the parity check sum information word.When code check is 3/5, and code word size is 16200 o'clock, formation parity check matrix as defined in following table;

The equipment of the channel of decoding in the communication system of utilizing low-density checksum inspection (LDPC) code is provided according to another aspect of the present invention.LDPC code parity check matrix extractor reads the parity check matrix of storage.The parity check matrix that the utilization of LDPC decoder is read is carried out the LDPC decoding.The parity check matrix that reads is divided into the parity check sum information word.When code check is 3/5, and code word size is 16200 o'clock, the parity check matrix that formation as defined in following table is read;

Description of drawings

By the reference accompanying drawing, above-mentioned feature and beneficial effect with other of the present invention become more obvious by following detailed description, wherein:

Fig. 1 is the parity check graph of matrix of 8 long LDPC codes of explanation.

Fig. 2 is the figure of the Tanner figure of the parity check matrix of 8 long LDPC codes of explanation.

Fig. 3 is the figure of the schematic structure of explanation DVB-S2LDPC code.

Fig. 4 is the parity check graph of matrix of explanation DVB-S2LDPC code.

Fig. 5 is for illustrating parity check graph of matrix according to an embodiment of the invention, and this parity check matrix is according to predetermined rule, and the columns and rows in the parity check matrix of the DVB-S2LDPC code by rearranging Fig. 4 generate.

Fig. 6 is used for the parity check graph of matrix of the required quasi-cyclic LDPC code of design DVB-S2LDPC code according to an embodiment of the invention for explanation.

Fig. 7 is used for designing the figure of the result that the parity check matrix of the required quasi-cyclic LDPC code of DVB-S2LDPC code obtains according to an embodiment of the invention for explanation by distortion.

Fig. 8 designs the flow chart of the process of DVB-S2LDPC code according to an embodiment of the invention for explanation.

Fig. 9 for explanation according to an embodiment of the invention to the figure of the Computer simulation results of DVB-S2LDPC code.

Figure 10 is for illustrating the block diagram of the structure of the transceiver in the communication system of the DVB-S2LDPC code that uses redesign according to an embodiment of the invention.

Figure 11 is the block diagram that the structure of the transmitter that utilizes according to an embodiment of the invention the LDPC code is described.

Figure 12 is the block diagram that the structure of the receiving equipment that utilizes according to an embodiment of the invention the LDPC code is described.

Figure 13 is for illustrating the flow chart of the reception work in the receiving equipment that utilizes the LDPC code according to an embodiment of the invention.

Embodiment

By the reference accompanying drawing, will describe the preferred embodiment of the present invention in detail.Although illustrate in different accompanying drawings, identical or similar element represents with identical or similar Reference numeral.Can omit the specific description of structure as known in the art and method to avoid making main body of the present invention not obvious.

The invention provides the method that has the DVB-S2LDPC code of good Tanner figure characteristic for design.In addition, the invention provides method and the equipment thereof of the parity check matrix generation LDPC code word of the LDPC code that utilizes above-mentioned design.

The parity check matrix description of the characteristic utilization of the structure of DVB-S2LDPC code DVB-S2LDPC code as shown in Figure 4 is as follows.For parity check matrix as shown in Figure 4, N ₁=30, K ₁=15, M ₁=5 and q3, and weight-1 position sequence of the row of the 0th row in three row groups is as follows:

0?1?2

0?11?13

0?10?14

At this, i weight-1 position sequence that i is capable sequentially represents in i row group the information of the position that is 1 row.

Re-construct the parity check matrix of Fig. 4 according to following rule.Fig. 4 is the parity check graph of matrix of explanation DVB-S2LDPC code.

Rule 3: rearrange the 0th row to the (N ₁-K ₁-1) OK, make (qi+j) line position in (M ₁J+i) in the row, 0≤i≤M wherein ₁And 0≤j≤q.

Rule 4: keep the 0th row to (K ₁-1) row are constant, rearrange K ₁Row to the (N ₁-1) row make (K ₁+ qi+j) row are positioned at (K ₁+ M ₁J+i) row.

According to rule 3 and rule 4, by re-constructing the parity check matrix of Fig. 4, obtain the parity check matrix with shape as shown in Figure 5.Fig. 5 is for illustrating parity check graph of matrix according to an embodiment of the invention, and this parity check matrix is according to predetermined rule, and the columns and rows in the parity check matrix of the DVB-S2LDPC code by rearranging Fig. 4 generate.

If ' the 1 ' (N that is present in the 0th row in supposition Fig. 5 ₁-1) row it should be understood that parity check matrix in Fig. 5 corresponding to a kind of quasi-cyclic LDPC code, and it is by M ₁* M ₁, that is, the cycle arrangement matrix of 5 * 5 sizes forms.' cycle arrangement matrix ' is defined as by a kind of permutation matrix of producing of cyclic shift row one by one to the right in unit matrix.In addition, ' quasi-cyclic LDPC code ' is defined as by the parity check matrix is divided into and severally has the piece (block) of formed objects and by cycle arrangement matrix or null matrix are mapped to a kind of LDPC code that piece produces.

In a word, it should be understood that and to obtain the parity check matrix of similar quasi-cyclic LDPC code by rule 3 and the rule 4 parity check matrixes that re-construct the DVB-S2LDPC code.Similarly, can be expected that, the inverse process by rule 3 and rule 4 can produce the DVB-S2LDPC code from quasi-cyclic LDPC code.

Although there is no known result of study to the DVB-S2LDPC code, a lot of known methods for designing for quasi-cyclic LDPC code arranged.The method for designing that is used for quasi-cyclic LDPC code comprises the known method for the ring property of optimizing Tanner figure.

Embodiments of the invention have proposed to utilize the method for known method design DVB-S2LDPC code of the ring property of the Tanner figure that improves quasi-cyclic LDPC code.Yet, because the method for the ring property that improves quasi-cyclic LDPC code only relates to the present invention indirectly, omit its detailed description for simplification.

Utilize the explanation of the method for quasi-cyclic LDPC code design DVB-S2LDPC code to provide as follows.The DVB-S2LDPC code has code word size N ₁, message length K ₁, and parity check length (N ₁-K ₁), and q=(N ₁-K ₁)/M ₁

The parity check matrix of quasi-cyclic LDPC code as shown in Figure 6.Fig. 6 is used for the parity check graph of matrix of the required quasi-cyclic LDPC code of design DVB-S2LDPC code according to an embodiment of the invention for explanation.Parity check matrix as shown in Figure 6 has (N ₁-K ₁) row and N ₁Row, and be divided into M ₁* M ₁Localized mass.For convenience, if t=K ₁/ M ₁, the message part of the parity check matrix of Fig. 6 and parity check part comprise respectively t row piece (column block) and q row piece, have the capable piece of q (row block) altogether.At this, N ₁/ M ₁=t+q.

The piece of the part separately of the parity check matrix of composition diagram 6 is corresponding to cycle arrangement matrix or null matrix.At this, the cycle arrangement matrix has M ₁* M ₁Size, and produce based on cycle arrangement matrix P, it is defined as follows:

In Fig. 6, a _ij Be 0 to M ₁-1 integer or the value of ∞, P ⁰Be defined as unit matrix I, P ^∞Expression M ₁* M ₁Null matrix.In addition, ' 0 ' the expression M of the numeral in the parity check part ₁* M ₁Null matrix.

The parity check matrix of Fig. 6 is characterised in that, has unit matrix I and cycle arrangement matrix corresponding to the row piece of parity check

As shown in the figure.In other words, the row piece corresponding to parity check is fixed as structure shown in Figure 6.The cycle arrangement matrix

Be defined as follows:

Quasi-cyclic LDPC code as shown in Figure 6 is the part that remains unchanged in the method for the ring of optimizing quasi-cyclic LDPC code, because fix corresponding to the structure of its parity check row piece partly.In other words, because the row piece corresponding to the parity check part is fixed in the parity check matrix of Fig. 6, be determined corresponding to being connected on Tanner figure between the variable node of parity check, in order to optimize the ring of Tanner figure, therefore only need to optimize the connection corresponding between the variable node of message part.

As mentioned above, there have been many known methods of the ring property of the Tanner figure that optimizes quasi-cyclic LDPC code.Because the method for designing of the quasi-cyclic LDPC code of the Tanner figure of the ring property that is used for having optimization only relates to the present invention indirectly, omit its detailed description at this.

Suppose that degree of certainty distributes to show outstanding performance at following state: the structure of parity check part by being used for the method for designing of quasi-cyclic LDPC code, is fixed in the standard circulation parity check matrix of Fig. 6 in this state.The position of cycle arrangement matrix and null matrix is distributed in row piece corresponding to message part according to degree and is determined.The ring property of Tanner figure is optimised thus.

For example form shown in Figure 7 is passed through at the cycle arrangement matrix

Last row of the first row in eliminate ' 1 ' and draw this cycle arrangement matrix

Last (N corresponding to the first row piece of the parity check matrix of Fig. 6 ₁/ M ₁) or (t+q) row piece.Fig. 7 is used for designing the figure of the result that the parity check matrix of the required quasi-cyclic LDPC code of DVB-S2LDPC code obtains according to an embodiment of the invention for explanation by distortion.

It should be noted that the cycle arrangement matrix Be changed to following matrix Q in Fig. 7.

Following regular 5 and regular 6 are defined as the processes that adopt rule 3 opposite with rule 4.

Rule 5: keep the 0th row to (K ₁-1) row are constant, rearrange K ₁To (N ₁-1) row, make (K ₁+ M ₁J+i) row are positioned at (K ₁+ qi+j) row, 0≤i≤M wherein ₁And 0≤j≤q.

Rule 6: rearrange the 0th row to the (N ₁-K ₁-1) OK, make (M ₁J+i) line position in (qi+j) OK.

The parity check matrix of the LDPC code that for example, produces from the quasi-cyclic LDPC code of Fig. 6 becomes the parity check matrix of the form with DVB-S2LDPC code shown in Figure 3 by the said process that adopts rule 5 and rule 6.Above-mentioned method for design DVB-S2 parity check matrix can be summarized as following step, and wherein, the code word of this DVB-S2 parity check matrix, information and parity check length are respectively N ₁, K ₁, and (N ₁-K ₁), and q=(N ₁-K ₁)/M ₁

DVB-S2LDPC code design process

Fig. 8 designs the flow chart of the process of DVB-S2LDPC code according to an embodiment of the invention for explanation.

With reference to figure 8, be identified for the required parameter of DVB-S2LDPC code of expected design in step 801.Be assumed to be design DVB-S2LDPC code herein and determined in advance the parameter that distributes such as code word size and message length and good degree.

Next, in step 803, according to determined parameter in step 801 form as shown in Figure 6 by M ₁* M ₁The parity check matrix of the quasi-cyclic LDPC code that cycle arrangement matrix and null matrix form.In Fig. 6, always be fixed into special form corresponding to parity check row piece partly.

In step 805, the algorithm of ring property that is used for improving the Tanner figure of quasi-cyclic LDPC code by employing is determined the cycle arrangement matrix corresponding to the row piece of Fig. 6 message part.Can use any known algorithm for improving ring property at this.

In step 807, for example obtain parity check matrix shown in Figure 7 by remove ' 1 ' in last row of the first row of that obtained in step 805, parity check matrix in Fig. 6.

In step 809, by the parity check matrix application rule 5 and regular 6 of Fig. 7 being rearranged parity check matrix column and the row of Fig. 7.The parity check matrix that obtains at last can be DVB-S2LDPC code as shown in Figure 3.

By through above-mentioned steps, the LDPC code being used above-mentioned DVB-S2LDPC cataloged procedure and generated codeword.

In order to analyze the performance of DVB-S2LDPC code, designed the DVB-S2LDPC code with following parameter.For example:

N ₁=648000，K ₁=38880，M ₁=360，q=72

The DVB-S2LDPC code that has the code check-3/5 of above-mentioned parameter for design is by using DVB-S2LDPC code design process, from having N altogether ₁/ M ₁=180 row piece and q=(N ₁-K ₁)/M ₁The quasi-cyclic LDPC code of=72 row pieces can obtain for example parity check matrix shown in table 1 and table 2.I weight-1 position sequence of i row sequentially represents in i row group the information of the position that is 1 row.

Table 1

Table 2

In addition, designed the DVB-S2LDPC code with following parameter.For example,

N ₁=16200，K ₁=9720，M ₁=360，q=18

The DVB-S2LDPC code that has the code check-3/5 of above-mentioned parameter for design is by using DVB-S2LDPC code design process, from having N altogether ₁/ M ₁=45 row piece and q=(N ₁-K ₁)/M ₁The quasi-cyclic LDPC code of=18 row pieces for example can obtain table 3 to the parity check matrix shown in table 6.I weight-1 position sequence that it should be noted that i row sequentially represents in i row group the information of the position that is 1 row.

Table 3

Table 4

Table 5

Table 6

Recently the design the DVB-S2LDPC code and existing DVB-S2LDPC code between performance more as shown in Figure 9.Fig. 9 for explanation according to an embodiment of the invention to the figure of the Computer simulation results of DVB-S2LDPC code.

It should be understood that when Additive White Gaussian Noise (AWGN) channel adopts binary phase shift keying (BPSK) modulation principle, at BER=10 ^-4The time, realize the improvement in performance of about 0.15dB.Can realize the improvement in performance of the DVB-S2LDPC code of code check-3/5 about table 1 to the information of the parity check matrix shown in table 6 by simple change.

Not only can be used for 3/5 code check and can be used in other code checks with reference to the described DVB-S2LDPC code of figure 8 design process.Example as being used for designing the DVB-S2LDPC code with other code checks has designed the DVB-S2LDPC code with following parameter.

N ₁=64800，K ₁=43200，M ₁=360，q=60

The DVB-S2LDPC code that has the code check-2/3 of above-mentioned parameter for design can be by the DVB-S2LDPC code design process of application drawing 8, from having N altogether ₁/ M ₁The quasi-cyclic LDPC code of=180 row pieces and the capable piece of q=60 for example obtains table 7 to the parity check matrix shown in table 10.

Table 7

Table 8

Table 9

Table 10

Figure 10 is the block diagram of the structure of the transceiver in the communication system that the DVB-S2LDPC code that uses according to an embodiment of the invention redesign is described.

With reference to Figure 10, message u is imported into the LDPC encoder 1011 in transmitter 1010 before being sent to receiver 1030.Then, the message u of LDPC encoder 1011 coding inputs, and also the signal c that coding is provided is to modulator 1013.The signal of modulator 1013 modulating-codings and send the signal s of modulation to receiver 1030 by wireless channel 1020.Then the signal r that sent by reflector 1010 of demodulator 1031 demodulation in receiver 1030, and the signal x of output demodulation is to LDPC decoder 1033.Then, LDPC decoder 1033 calculates the estimated value of message from the data that receive by wireless channel u

The detailed construction of the transmission equipment in the communication system of the DVB-S2LDPC code of utilization redesign as shown in figure 11.Figure 11 is for illustrating the block diagram of the structure of the transmitter of the LDPC code of utilization redesign according to an embodiment of the invention.

Transmitter comprises controller 1130, LDPC code parity check matrix extractor 1110 and LDPC encoder 1150.

LDPC code parity check matrix extractor 1110 extracts LDPC code parity check matrix according to the requirement of system.LDPC code parity check matrix can be extracted to the sequence information shown in table 10 from table 1, can be extracted by utilizing the memory stored therein the parity check matrix, and is can be in transmitter given or be produced in transmitter.

Controller 1130 is adapted according to code check, code word size or message length determines that required parity check matrix is to satisfy the requirement of system.

LDPC encoder 1150 is carried out coding based on the LDPC code parity check matrix information that is read by controller 1130 and LDPC code parity check matrix extractor 1110.

Figure 12 illustrates the block diagram of the structure of receiving equipment according to an embodiment of the invention.

Figure 12 has illustrated and has been used for receiving from the signal of the communication system transmitting of the DVB-S2LDPC code that utilizes redesign and recovers the receiving equipment of the data of user's expection from the signal that receives.

Receiving equipment comprises controller 1250, parity check matrix decision device (decider) 1230, LDPC code parity check matrix extractor 1270, demodulator 1210 and LDPC decoder 1290.

The LDPC code that demodulator 1210 demodulation receive provides the signal of demodulation to parity check matrix decision device 1230 and LDPC decoder 1290.

Parity check matrix decision device 1230, under the control of controller 1250, the parity check matrix of the LDPC code that uses in the signal deciding system based on demodulation.

Controller 1250 provides determination result to LDPC code parity check matrix extractor 1270 and LDPC decoder 1290 from parity check matrix decision device 1230.

LDPC code parity check matrix extractor 1270, under the control of controller 1250, the parity check matrix of the LDPC code that extraction system is required provides the parity check matrix that extracts to LDPC decoder 1290.As mentioned above, the parity check matrix of LDPC code can be from being extracted as table 1 to sequence information as shown in table 10, can be extracted by utilizing the memory of having stored therein the parity check matrix, can be given in transmitter, or can be produced in transmitter.

LDPC decoder 1290 under the control of controller 1250, based on the signal of the reception that provides from demodulator 1210 with from the information about the parity check matrix of LDPC code that LDPC code parity check matrix extractor 1270 provides, is carried out decoding.

In Figure 12, the workflow diagram of receiving equipment as shown in figure 13.

In step 1301, decoder 1210 receives from the signal of the communication system transmitting of the DVB-S2LDPC code that utilizes redesign, and the signal that receives of demodulation.After this, in step 1303, parity check matrix decision device 1230 is made decision to the parity check matrix of the LDPC code that uses in system based on the signal of demodulation.

In step 1305, be provided to LDPC code parity check matrix extractor 1270 from the determination result of parity check matrix decision device 1230.In step 1307, the LDPC code parity check matrix that LDPC code parity check matrix extractor 1270 extraction systems are required, and provide this matrix to LDPC decoder 1290.

As mentioned above, the parity check matrix of LDPC code can be from being extracted as table 1 to sequence information as shown in table 10, can be extracted by utilizing the memory of having stored therein the parity check matrix, can be given in transmitter, or can be produced in transmitter.

After this, in step 1309, LDPC decoder 1290 is carried out decoding based on the information of the parity check matrix of the relevant LDPC code that provides from LDPC code parity check matrix extractor 1270.

Obviously find out from above-mentioned, the present invention has optimized the characteristic of Tanner figure in design DVB-S2LDPC code, has optimized thus the performance of the communication system of utilizing the LDPC code.

Although illustrate and illustrated the present invention with reference to some preferred embodiment of the present invention, will be understood by those skilled in the art that, under the prerequisite that does not break away from the spirit and scope of the present invention that claims limit, can carry out in form and details different variations.

Claims (8)

1. the method for the channel of the communication system of decoding use low-density checksum inspection LDPC code, comprise the steps:

Extract the parity check matrix of LDPC code; With

Utilize the parity check matrix of described extraction, carry out the LDPC decoding;

Wherein code check be 3/5 and also code word size be 16200, as following table institute parity check matrix as described in formation with defining:

2. the method for claim 1, wherein said parity check matrix has a plurality of row groups that have in groups by dividing corresponding to the row of information word, and each row group has the row of predetermined number; And

Every delegation in wherein said table comprises sequence information, and described sequence information points out that wherein ' 1 ' is positioned at the position of row of row group of the correspondence of described parity check matrix.

3. the method for the channel of the communication system of decoding use low-density checksum inspection LDPC code, comprise the steps:

Extract the parity check matrix of LDPC code; With

Utilize the parity check matrix that extracts, carry out the LDPC decoding;

Wherein code check be 3/5 and also code word size be 64800, as following table institute parity check matrix as described in formation with defining:

4. the method for the channel of the communication system of decoding use low-density checksum inspection LDPC code, comprise the steps:

Extract the parity check matrix of described LDPC code; With

Utilize the parity check matrix that extracts, carry out the LDPC decoding;

Wherein code check be 2/3 and also code word size be 64800, as following table institute parity check matrix as described in formation with defining:

5. one kind is used for decoding and uses low-density checksum to check the equipment of channel of the communication system of LDPC code, comprising:

Be used for reading the LDPC code parity check matrix extractor of parity check matrix; With

Be used for utilizing the described parity check matrix that reads to carry out the LDPC decoder of LDPC decoding;

Wherein code check be 3/5 and also code word size be 16200, as following table institute parity check matrix as described in formation with defining:

6. equipment as claimed in claim 5, wherein said parity check matrix has a plurality of row groups that have in groups by dividing corresponding to the row of information word, and each row group has the row of predetermined number; And

Every delegation in wherein said table comprises sequence information, and described sequence information points out that wherein ' 1 ' is positioned at the position of row of row group of the correspondence of described parity check matrix.

7. one kind is used for decoding and uses low-density checksum to check the equipment of channel of the communication system of LDPC code, comprising:

Be used for reading the LDPC code parity check matrix extractor of parity check matrix; With

Be used for utilizing the described parity check matrix that reads, carry out the LDPC decoder of LDPC decoding;

Wherein code check be 3/5 and also code word size be 64800, as following table institute parity check matrix as described in formation with defining:

8. one kind is used for decoding and uses low-density checksum to check the equipment of channel of the communication system of LDPC code, comprising:

Be used for reading the LDPC code parity check matrix extractor of parity check matrix; With

Be used for utilizing the described parity check matrix that reads, carry out the LDPC decoder of LDPC decoding;

Wherein code check be 2/3 and also code word size be 64800, as following table institute parity check matrix as described in formation with defining:

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