CN103138550A - System adopting software to achieve voltage spike inhibition - Google Patents
System adopting software to achieve voltage spike inhibition Download PDFInfo
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- CN103138550A CN103138550A CN2013100520995A CN201310052099A CN103138550A CN 103138550 A CN103138550 A CN 103138550A CN 2013100520995 A CN2013100520995 A CN 2013100520995A CN 201310052099 A CN201310052099 A CN 201310052099A CN 103138550 A CN103138550 A CN 103138550A
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Abstract
The invention discloses a system adopting software to achieve voltage spike inhibition. The system adopts a digitally controlled voltage spike inhibition circuit. The scheme is mainly that the system consists of a ninth switch tube, a sixth diode, a first capacitor responsible for energy storage and leakage inductance resonance, and auxiliary networks of a fifth diode and a second capacitor, wherein the ninth switch tube and the sixth diode are responsible for energy path changing. The software respectively controls a power tube and an active embedding tube of a phase-shifted full bridge through three efficient event managers. The system adopts the digital control scheme, eliminates auxiliary edging voltage spike, achieves flexibility and adaptability of a controller and remarkably improves the convertor efficiency.
Description
Technical field
The present invention relates to field of power conversion, be specifically related to a kind of software that adopts and realize the system that due to voltage spikes suppresses.
Background technology
In recent years, along with the development of soft switch technique, powerful DC/DC and DC/AC module more and more adopt the full-bridge soft-switching topological structure, adopt the converter of this topological form all to have switching loss low, the advantage that keeps constant frequency to control.But the converter of this topological form also has obvious deficiency, as transformer leakage inductance and rectifying tube parasitic capacitance generation resonance, the rectifying tube two ends can produce serious voltage overshoot and oscillatory occurences (due to voltage spikes), if it is bad that this due to voltage spikes suppresses, its peak value may reach the twice of secondary busbar voltage, this is fatal for the secondary rectifier diode, so must adopt certain braking measure.
Measure commonly used at present comprises: resistance-capacitance absorption in parallel loop, (1) rectifying tube two ends, and method is simple, but large at the large-power occasions resistance loss, assimilation effect is undesirable; (2) add clamping diode at transformer primary side, do like this voltage oscillation that can improve on transformer secondary rectifying tube, but oscillation-damped fully.
Adopted a kind of clamped control program of software of novelty in the present invention, the spike that can well suppress rectifying tube voltage, simultaneously owing to adopting secondary auxiliary circuit network can better reduce the loss of circuit, the efficiency of the integral transformation device guaranteed, and numerically controlled introducing has guaranteed very high flexibility and very strong robustness.
Summary of the invention
The object of the invention is to overcome the above problem that prior art exists, provide a kind of software that adopts to realize the system that due to voltage spikes suppresses, the present invention has adopted numerically controlled scheme, eliminated the secondary voltage spike, realized the flexibility of controller simultaneously, adaptability, and significantly promoted transducer effciency.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
Adopt software to realize the system that due to voltage spikes suppresses, comprise that inverter topology and control module form, described inverter topology is delivered flow module by direct current, active clamp circuit, the secondary clamp circuit is delivered the flow module composition with exchanging, described direct current delivers flow module and active clamp circuit is connected in parallel, described active clamp circuit is also delivered flow module and is connected in parallel with exchanging with the secondary clamp circuit, described control module is by clamped driving logic protection module, the control loop module, phase-shifting full-bridge drives logic protection module and three efficient task managers to be composed in series, described phase-shifting full-bridge drives logic protection module also to be connected with the second efficient task manager, the described first efficient task manager is provided with the first control end and the second control end, described the first control end is connected with the first switching tube, described the second control end is connected with the second switch pipe, the described second efficient task manager is provided with the 3rd control end and the 4th control end, described the 3rd control end is connected with the 3rd switching tube, described the 4th control end is connected with the 4th switching tube, described third high effect task manager is provided with the 5th control end, described the 5th control end is connected with the 9th switching tube.
Further, the carrier frequency of the described first efficient task manager and the second efficient task manager is 20K.
Further, the carrier frequency of described third high effect task manager is 40K.
Further, described direct current is delivered flow module by power supply, transformer, four diodes and four switching tubes connect to form, described the first switching tube and second switch pipe string connection, and in parallel with power supply, described the 3rd switching tube and the series connection of the 4th switching tube, and in parallel with power supply, described transformer is connected to form by the first inductance and the second inductance coupling high, described the first inductance is connected with second switch pipe and the 4th switching tube, described the second inductance is connected with the second diode and the 4th diode, described the first diode, the second diode, the 3rd diode and the series connection of the 4th diode.
Further, described active clamp circuit is connected to form by the 9th switching tube, the 6th diode and the first electric capacity, described the 9th switching tube and the first capacitances in series, and with the 6th diodes in parallel.
Further, described secondary clamp circuit is connected to form by the 5th diode, the second electric capacity and the first resistance, and described the second electric capacity is connected with the 5th diode, and in parallel with the first resistance.
Further, described interchange is delivered flow module and is connected to form by the second resistance and four switching tubes, described the second resistance is connected with the 6th switching tube and minion is closed the pipe string connection, described the 6th switching tube series connection, the 7th switching tube, the 5th switching tube series connection and the 8th switch pipe string connection.
The invention has the beneficial effects as follows:
The present invention is ingenious has adopted active clamped principle, the active clamped control method of a kind of software of novelty has been applied in the topological structure of phase-shifting full-bridge, and the analog control method broken traditions, adopted numerically controlled scheme, eliminated the secondary voltage spike, realized the flexibility of controller simultaneously, adaptability, and significantly promoted transducer effciency.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, below with preferred embodiment of the present invention and coordinate accompanying drawing to be described in detail as follows.The specific embodiment of the present invention is provided in detail by following examples and accompanying drawing thereof.
The accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention the present invention does not form inappropriate limitation of the present invention for explaining.In the accompanying drawings:
Fig. 1 is circuit topology figure of the present invention.
Fig. 2 be of the present invention be software control logic figure.
Fig. 3 is phase-shifting full-bridge drive waveforms figure of the present invention.
Fig. 4 is the drive waveforms figure of phase-shifting full-bridge of the present invention and the 9th switching tube.
Number in the figure explanation: 1, inverter topology, 2, control module, 3, the control loop module, 4, clamped driving logic protection module, 5, phase-shifting full-bridge drives logic protection module, 6, the first efficient task manager, 7, the second efficient task manager, 8, third high effect task manager, 9, the first control end, 10, the second control end, 11, the 3rd control end, 12, the 4th control end, 13, the 5th control end, 14, direct current is delivered flow module, and 15, active clamp circuit, 16, the secondary clamp circuit, 17, flow module is delivered in interchange, Q1, the first switching tube, Q2, the second switch pipe, Q3, the 3rd switching tube, Q4, the 4th switching tube, Q5, the 5th switching tube, Q6, the 6th switching tube, Q7, the 7th switching tube, Q8, the 8th switching tube, Qc, the first switching tube, D1, the first diode, D2, the second diode, D3, the 3rd diode, D4, the 4th diode, D5, the 5th diode, Dc, the 6th diode, DC, power supply, T1, transformer, L1, the first inductance, L2, the second inductance, R1, the first resistance, R2, the second resistance, Cs, the first electric capacity, C2, the second electric capacity.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Shown in Fig. 1 and Fig. 2, adopt software to realize the system that due to voltage spikes suppresses, comprise that inverter topology 1 and control module 2 form, described inverter topology 1 is delivered flow module 14 by direct current, active clamp circuit 15, secondary clamp circuit 16 is delivered flow module 17 compositions with exchanging, described direct current is delivered flow module 14 and is connected in parallel with active clamp circuit 15, described active clamp circuit 15 is also delivered flow module 17 and is connected in parallel with exchanging with secondary clamp circuit 16, described control module 2 is by clamped driving logic protection module 4, control loop module 3, phase-shifting full-bridge drives logic protection module 5 and three efficient task managers 6, 7, 8 are composed in series, described phase-shifting full-bridge drives logic protection module 5 also to be connected with the second efficient task manager 7, the described first efficient task manager 6 is provided with the first control end 9 and the second control end 10, described the first control end 9 is connected with the first switching tube Q1, described the second control end 10 is connected with second switch pipe Q2, the described second efficient task manager 7 is provided with the 3rd control end 11 and the 4th control 12 system ends, described the 3rd control end 11 is connected with the 3rd switching tube Q3, described the 4th control end 12 is connected with the 4th switching tube Q4, described third high effect task manager 8 is provided with the 5th control end 13, described the 5th control end 13 is connected with the 9th switching tube Qc.
Further, the carrier frequency of the described first efficient task manager 6 and the second efficient task manager 7 is 20K.
Further, the carrier frequency of described third high effect task manager 8 is 40K.
Further, described direct current is delivered flow module 14 by power supply DC, transformer T1, four diode D1, D2, D3, D4 and four switching tube Q1, Q2, Q3, Q4 connects to form, described the first switching tube Q1 and second switch pipe Q2 series connection, and DC is in parallel with power supply, described the 3rd switching tube Q3 and the 4th switching tube Q4 series connection, and DC is in parallel with power supply, described transformer T1 is of coupled connections and is formed by the first inductance L 1 and the second inductance L 2, described the first inductance L 1 is connected with second switch pipe Q2 and the 4th switching tube Q4, described the second inductance L 2 is connected with the second diode D2 and the 4th diode D4, described the first diode D1, the second diode D2, the 3rd diode D3 and the 4th diode D4 series connection.
Further, described active clamp circuit 15 is connected to form by the 9th switching tube Qc, the 6th diode Dc and the first capacitor C s, and described the 9th switching tube Qc connects with the first capacitor C s, and in parallel with the 6th diode Dc.
Further, described secondary clamp circuit 16 is connected to form by the 5th diode D5, the second capacitor C 2 and the first resistance R 1, and described the second capacitor C 2 is connected in the 5th diode D5, and in parallel with the first resistance R 1.
Further, described interchange is delivered flow module 17 and is connected to form by the second resistance R 2 and four switching tube Q5, Q6, Q7, Q8, described the second resistance R 2 is connected with the 6th switching tube Q6 and the 7th switching tube Q7 series connection, described the 6th switching tube Q6 series connection, the 7th switching tube Q7, the 5th switching tube Q5 series connection and the 8th switching tube Q8 series connection.
The operation principle of the present embodiment is as follows:
As shown in Figure 1, in figure, the first switching tube Q1 and the 4th switching tube Q4 are leading-bridge, and second switch pipe Q2 and the 3rd switching tube Q3 are lagging leg, and T1 is transformer, and the 9th switching tube Qc, the 6th diode Dc and the first capacitor C s form the secondary active clamp loop.When T1 level power output of transformer, transformer T1 leakage inductance produces resonance by the first capacitor C s of the 6th diode Dc and clamp, give the first capacitor C s charging, rectifying tube voltage is clamped at the steady-state value of the first capacitor C s voltage simultaneously, so the rectifying tube two ends no longer produce voltage overshoot and vibration.In T1 level power output of transformer, through an of short duration time delay, to the 9th switching tube Qc triggering and conducting, like this when leakage inductance and the first capacitor C s resonant charging voltage during higher than the rectifying tube output voltage, electric capacity by the 9th switching tube Qc by energy back to load.The circuit that the 5th diode D5, the first resistance R 1 and the second capacitor C 2 form plays the effect of secondary clamper, when zero crossing, the voltage at the first capacitor C s two ends can be higher to some extent, use secondary clamp circuit 16 to charge to the second capacitor C 2 by the 5th diode D5 when the first capacitor C s overtension, the second capacitor C 2 is discharged by the second resistance R 2 again, plays the effect of better inhibition due to voltage spikes.
As shown in Figure 2, in figure, the first efficient task manager 6 and the second efficient task manager 7 adopt the carrier frequency of 20K, third high effect task manager 8 adopts the carrier frequency of 40K, wherein the first efficient task manager 6 is controlled advance pipe (first control end 9 control the first switching tube Q1, the second control end 10 is controlled second switch pipe Q2), (the 3rd control end 11 is controlled the 3rd switching tube Q3 to the second efficient task manager 7 control hysteresis pipes, the 4th control end 12 is controlled the 4th switching tube Q4), the 5th control end 13 is controlled the 9th switching tube Qc, control loop module 3 is by outside inductive current iL, line voltage vGrid, the a series of parameters such as Bus voltage vBus, carry out closed-loop control, produce and control duty ratio Duty, clamped driving logic protection module 4 is by the T of duty ratio Duty and software set
oFFDand T
oNDproduce the driving T of the 9th switching tube Qc
oN, the driving signal that phase-shifting full-bridge drives logic protection module 5 to produce the first efficient task manager 6 and the second efficient task manager 7 by duty ratio Duty is realized phase-shifting full-bridge,
As shown in Figure 3, in figure, Deff is effective duty cycle.
As shown in Figure 4, be the drive waveforms of phase-shifting full-bridge and the 9th switching tube Qc.T wherein
oNDfor the time that clamped pipe time delay effective duty cycle is opened, T
oFFDbe the time that the leading effective duty cycle of the 9th switching tube Qc turn-offs, T
oNthe time of opening for clamped pipe.
Concrete step is:
(1) system initialization, configure three efficient task manager 6,7,8 modules, and the second efficient task manager 7 is synchronized with the clock of the first efficient task manager 6, and third high effect task manager 8 is synchronized with the clock of the second efficient task manager 7;
(2) signal (iL, vGrid, vBus) that control loop module 3 gathers according to outside obtains the needed duty ratio Duty of system by closed loop control algorithm;
(3) after phase-shifting full-bridge drives logic and protection module 5 to obtain duty ratio Duty, the Duty assignment is given to the register of the second efficient task manager 7, because the second efficient task manager 7 is synchronized with the clock of the first efficient task manager 6, the second efficient task manager 7 can be controlled the carrier phase of the second efficient task manager 7 according to Duty, form the controlling mechanism of phase-shifting full-bridge;
(4) after clamped driving logic and protection module 4 obtain duty ratio Duty, and T
oFFD+ T
oNDand compare, if Duty is greater than T
oFFD+ T
oNDand, enter next step.Otherwise, because the 5th control end 13 can not be exported negative duty ratio, software is closed the 5th control end 13;
(5) clamped driving logic and protection module 4 are Duty, T
oFFD, T
oNDdeliver in the lump the register of the 5th control end, obtain the driving T of the 9th switching tube Qc by the 5th control end 13
oN, DSP is at the new PWM of next renewal point output, and software rebound step (2), carry out the control of next cycle.
Due to the control mode of the phase-shifting full-bridge adopted, in control loop, to circuit topology, real effective duty cycle is the first control end and the staggered part of the second control end, the 9th switching tube Qc the opening along a period of time T of effective duty cycle that need to lag behind
oND, also want opening along a period of time T of leading effective duty cycle simultaneously
oFFD.The waveform of concrete the 9th switching tube Qc as shown in Figure 4, digital control owing to adopting, T
oNDand T
oFFall can adjust by software, minimum adjustment beat is 16.7ns, can meet the requirement of system fully.The clock frequency of this timeticks and DSP is relevant, and by adopting the DSP of higher frequency clock, timeticks can be accomplished less.Simultaneously due in the present invention, all control modules all are integrated in a DSP, timeticks can be accomplished in full accord, can't as analogue device, along with the variation of time and temperature, cause the variation of device parameters, do not have the drift of working point yet, digital control have a fabulous linearity, and the robustness of system is had to good raising.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. adopt software to realize the system that due to voltage spikes suppresses, it is characterized in that: comprise that inverter topology (1) and control module (2) form, described inverter topology (1) is delivered flow module (14) by direct current, active clamp circuit (15), secondary clamp circuit (16) is delivered flow module (17) composition with exchanging, described direct current is delivered flow module (14) and is connected in parallel with active clamp circuit (15), described active clamp circuit (15) is also delivered flow module (17) and is connected in parallel with exchanging with secondary clamp circuit (16), described control module (2) is by clamped driving logic protection module (4), control loop module (3), phase-shifting full-bridge drives logic protection module (5) and three efficient task managers (6, 7, 8) be composed in series, described phase-shifting full-bridge drives logic protection module (5) also to be connected with the second efficient task manager (7), the described first efficient task manager (6) is provided with the first control end (9) and the second control end (10), described the first control end (9) is connected with the first switching tube (Q1), described the second control end (10) is connected with second switch pipe (Q2), the described second efficient task manager (7) is provided with the 3rd control end (11) and the 4th control (12) system end, described the 3rd control end (11) is connected with the 3rd switching tube (Q3), described the 4th control end (12) is connected with the 4th switching tube (Q4), described third high effect task manager (8) is provided with the 5th control end (13), described the 5th control end (13) is connected with the 9th switching tube (Qc).
2. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, and it is characterized in that: the described first efficient task manager (6) is 20K with the carrier frequency of the second efficient task manager (7).
3. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, and it is characterized in that: the carrier frequency of described third high effect task manager (8) is 40K.
4. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, it is characterized in that: described direct current is delivered flow module (14) by power supply (DC), transformer (T1), four diode (D1, D2, D3, D4) and four switching tube (Q1, Q2, Q3, Q4) connect to form, described the first switching tube (Q1) and second switch pipe (Q2) series connection, and in parallel with power supply (DC), described the 3rd switching tube (Q3) and the series connection of the 4th switching tube (Q4), and in parallel with power supply (DC), described transformer (T1) is of coupled connections and is formed by the first inductance (L1) and the second inductance (L2), described the first inductance (L1) is connected with second switch pipe (Q2) and the 4th switching tube (Q4), described the second inductance (L2) is connected with the second diode (D2) and the 4th diode (D4), described the first diode (D1), the second diode (D2), the 3rd diode (D3) and the series connection of the 4th diode (D4).
5. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, it is characterized in that: described active clamp circuit (15) is connected to form by the 9th switching tube (Qc), the 6th diode (Dc) and the first electric capacity (Cs), described the 9th switching tube (Qc) is connected with the first electric capacity (Cs), and in parallel with the 6th diode (Dc).
6. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, it is characterized in that: described secondary clamp circuit (16) is connected to form by the 5th diode (D5), the second electric capacity (C2) and the first resistance (R1), described the second electric capacity (C2) is connected with the 5th diode (D5), and in parallel with the first resistance (R1).
7. employing software according to claim 1 is realized the system that due to voltage spikes suppresses, it is characterized in that: described interchange is delivered flow module (17) and is connected to form by the second resistance (R2) and four switching tubes (Q5, Q6, Q7, Q8), described the second resistance (R2) is connected with the 6th switching tube (Q6) and the series connection of the 7th switching tube (Q7), described the 6th switching tube (Q6) series connection, the 7th switching tube (Q7), the 5th switching tube (Q5) series connection and the series connection of the 8th switching tube (Q8).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9966864B2 (en) | 2014-12-15 | 2018-05-08 | Delta Electronics, Inc. | Electronic apparatus and control method of electronic apparatus |
| CN111786547A (en) * | 2020-07-27 | 2020-10-16 | 石家庄通合电子科技股份有限公司 | Design method and circuit for inhibiting diode rectification voltage peak |
| CN112234810A (en) * | 2020-09-04 | 2021-01-15 | 西安交通大学 | Novel SiC MOSFET oscillation suppression circuit applied to half-bridge circuit |
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| US5198969A (en) * | 1990-07-13 | 1993-03-30 | Design Automation, Inc. | Soft-switching full-bridge dc/dc converting |
| CN102570830A (en) * | 2011-12-23 | 2012-07-11 | 上海电机学院 | Modular photovoltaic power electronic converter based on coupling inductance |
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| US5198969A (en) * | 1990-07-13 | 1993-03-30 | Design Automation, Inc. | Soft-switching full-bridge dc/dc converting |
| CN102570830A (en) * | 2011-12-23 | 2012-07-11 | 上海电机学院 | Modular photovoltaic power electronic converter based on coupling inductance |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9966864B2 (en) | 2014-12-15 | 2018-05-08 | Delta Electronics, Inc. | Electronic apparatus and control method of electronic apparatus |
| CN111786547A (en) * | 2020-07-27 | 2020-10-16 | 石家庄通合电子科技股份有限公司 | Design method and circuit for inhibiting diode rectification voltage peak |
| CN112234810A (en) * | 2020-09-04 | 2021-01-15 | 西安交通大学 | Novel SiC MOSFET oscillation suppression circuit applied to half-bridge circuit |
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Application publication date: 20130605 |