CN103137605B - The test structure of monitoring source and drain polycrystalline and pipe side wall stray capacitance and manufacture method - Google Patents
The test structure of monitoring source and drain polycrystalline and pipe side wall stray capacitance and manufacture method Download PDFInfo
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- CN103137605B CN103137605B CN201110394479.8A CN201110394479A CN103137605B CN 103137605 B CN103137605 B CN 103137605B CN 201110394479 A CN201110394479 A CN 201110394479A CN 103137605 B CN103137605 B CN 103137605B
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Abstract
The invention discloses a kind of test structure monitoring source and drain polycrystalline and pipe side wall stray capacitance, comprise grid, grid curb wall and source and drain polysilicon, described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer, grid curb wall is formed at the both sides of grid, source and drain polysilicon is formed at the outside of grid curb wall, and grid, grid curb wall and source and drain polysilicon are all positioned at above silica shallow-trench isolation.The present invention also discloses the manufacture method of described test structure and a kind of test structure referring to structure more.The present invention is directed to the autoregistration CMOS tube in germanium silicon BiCMOS technique, can effective monitoring grid polycrystalline silicon by the size of the parasitic capacitance of pipe side wall and source and drain inter polysilicon; Test structure is based upon on shallow trench oxidation insulate on Si completely, the bottom of source and drain polysilicon is silica, can be ignored by the additional parasitic electric capacity produced bottom source and drain polysilicon and grid polycrystalline silicon, survey the single parasitic capacitance from source and drain polysilicon-CMOS side wall-grid polycrystalline silicon of electric capacity.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly a kind of in germanium silicon BiCMOS technique for the monitoring source and drain polycrystalline of autoregistration field effect transistor and the test structure of pipe side wall stray capacitance and manufacture method.
Background technology
Promote the prime movers that semiconductor device speed is down feature sizes, but this generally needs to use expensive equipment to realize.Other method is then reduce the various ghost effects of device by every means, and mainly dead resistance and electric capacity realize this purpose.
In the process exploitation of germanium silicon BiCMOS, because the emitter in germanium-silicon heterojunction bipolar triode technique needs to use one deck polysilicon, this layer of polysilicon can be used in CMOS technology and form self aligned field effect transistor, the area of source-drain area can be reduced by the source and drain that this one deck polysilicon connects field effect transistor, thus reduce the parasitic capacitance of source and drain and trap.
But the source and drain polysilicon of this structure exceeds monocrystalline silicon interface, active area, in it and grid polycrystalline silicon, one, interval CMOS side wall forms a new parasitic capacitance C
gDand C
gS, as shown in Figure 1, directly affect the effect that autoregistration field effect transistor parasitic capacitance reduces, although this parasitic capacitance is very little, if cannot be effectively controlled or monitor, also can the optimization of limiting device performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of test structure monitoring source and drain polycrystalline and pipe side wall stray capacitance, directly can test the parasitic capacitance of grid polycrystalline silicon by being formed between side wall and source and drain polysilicon in autoregistration CMOS tube.For this reason, the present invention also provides the manufacture method of described test structure.
For solving the problems of the technologies described above, the test structure of monitoring source and drain polycrystalline provided by the invention and pipe side wall stray capacitance, described test structure comprises grid, grid curb wall and source and drain polysilicon, described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer, grid curb wall is formed at the both sides of grid, source and drain polysilicon is formed at the outside of grid curb wall, and grid, grid curb wall and source and drain polysilicon are all positioned at above silica shallow-trench isolation.
Further, described grid curb wall is made up of nitride film medium and oxide film dielectric.
The present invention also provides a kind of manufacture method monitoring the test structure of source and drain polycrystalline and pipe side wall stray capacitance, comprises the following steps:
1st step, forms silica shallow-trench isolation on a silicon substrate;
2nd step, growth grid oxide layer, deposit one deck grid polycrystalline silicon on it, deposit one deck nitride film medium on grid polycrystalline silicon;
3rd step, chemical wet etching forms grid, and described grid has nitride film medium, grid polycrystalline silicon and grid oxide layer;
4th step, deposit layer oxide film medium, deposit one deck nitride film medium on oxide film dielectric;
5th step, anti-carves nitride film medium and oxide film dielectric forms grid curb wall;
6th step, deposit emitter-polysilicon;
7th step, anti-carve and form source and drain polysilicon, described source and drain polysilicon is positioned in silica shallow-trench isolation.
Further, in the 3rd step, nitride film medium applies photoresist, chemical wet etching forms grid.
The test structure of monitoring source and drain polycrystalline of the present invention and pipe side wall stray capacitance, described test structure is the many fingers structure be formed in silica shallow-trench isolation, this many fingers structure is alternately made up of multiple grid and multiple source and drain polysilicon, and the outermost referring to structure is the grid of redundancy structure more, the both sides of described each grid are grid curb wall, the described multiple source and drain polysilicons referred in structure draw formation source and drain exit more, and the multiple grids between source and drain polysilicon draw formation gate terminal.
Further, described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer.Describedly refer to that the grid of outermost two redundancy structures of structure is electrically connected more.
Beneficial effect of the present invention is:
1, the present invention is directed to the autoregistration CMOS tube in germanium silicon BiCMOS technique, can effective monitoring grid polycrystalline silicon by the parasitic capacitance of pipe side wall and source and drain inter polysilicon, and the size of direct measurement parasitic capacitance;
2, test structure is based upon on shallow trench oxidation insulate on Si completely, the bottom of source and drain polysilicon is silica, can be ignored by the additional parasitic electric capacity produced bottom source and drain polysilicon and grid polycrystalline silicon, survey the single parasitic capacitance from source and drain polysilicon-CMOS side wall-grid polycrystalline silicon of electric capacity;
3, test structure of the present invention can design as required and refer to structure more, increases the parasitic capacitance that grid polycrystalline silicon passes through pipe side wall and source and drain inter polysilicon, to improve measuring accuracy.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the parasitic capacitance schematic diagram formed in existing germanium silicon BiCMOS technique;
Fig. 2 to Fig. 9 is the schematic cross-section of test structure manufacturing process of the present invention;
Figure 10 is the schematic diagram referring to structure in the present invention more.
Embodiment
The test structure of monitoring source and drain polycrystalline of the present invention and pipe side wall stray capacitance, as shown in Figure 9, comprise grid, grid curb wall and source and drain polysilicon, described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer, grid curb wall is formed at the both sides of grid, source and drain polysilicon is formed at the outside of grid curb wall, and grid, grid curb wall and source and drain polysilicon are all positioned at above silica shallow-trench isolation.
Wherein, described grid curb wall is made up of nitride film medium and oxide film dielectric.
The manufacture method of the test structure of above-mentioned monitoring source and drain polycrystalline and pipe side wall stray capacitance, comprises the following steps:
1st step, forms silica shallow-trench isolation, as shown in Figure 2 on a silicon substrate;
2nd step, growth grid oxide layer, deposit one deck grid polycrystalline silicon on it, deposit one deck nitride film medium on grid polycrystalline silicon, as shown in Figure 3;
3rd step, nitride film medium applies photoresist, and chemical wet etching forms grid, and described grid has nitride film medium, grid polycrystalline silicon and grid oxide layer, as shown in Figure 4 and Figure 5;
4th step, deposit layer oxide film medium, deposit one deck nitride film medium on oxide film dielectric, as shown in Figure 6;
5th step, anti-carves nitride film medium and oxide film dielectric forms grid curb wall, as shown in Figure 7;
6th step, deposit emitter-polysilicon, as shown in Figure 8;
7th step, anti-carve and form source and drain polysilicon, described source and drain polysilicon is positioned in silica shallow-trench isolation, as shown in Figure 9.
Described test structure is the many fingers structure be formed in silica shallow-trench isolation, as shown in Figure 10, this many fingers structure is alternately made up of grid and source and drain polysilicon, and the outermost referring to structure is the grid of redundancy structure more, the both sides of described grid are grid curb wall, the described multiple source and drain polysilicons referred in structure draw formation source and drain exit more, and the multiple grids between source and drain polysilicon draw formation gate terminal.
Describedly refer to that the grid of outermost two redundancy structures of structure is electrically connected, the structure that the grid of redundancy structure is process uniformity for ensureing test structure and increases, this structure arranges around required operator guards usually, and can not be electrically connected more.
The present invention is directed to the autoregistration CMOS tube in germanium silicon BiCMOS technique, can effective monitoring grid polycrystalline silicon by the parasitic capacitance of pipe side wall and source and drain inter polysilicon, and the size of direct measurement parasitic capacitance; Test structure is based upon on shallow trench oxidation insulate on Si completely, the bottom of source and drain polysilicon is silica, can be ignored by the additional parasitic electric capacity produced bottom source and drain polysilicon and grid polycrystalline silicon, survey the single parasitic capacitance from source and drain polysilicon-CMOS side wall-grid polycrystalline silicon of electric capacity; Test structure of the present invention can design as required and refer to structure more, increases the parasitic capacitance that grid polycrystalline silicon passes through pipe side wall and source and drain inter polysilicon, to improve measuring accuracy.
Because the final thickness of source and drain polysilicon is relevant with the spacing of grid polycrystalline silicon, this spacing in test structure must be identical with the gate pitch of the CMOS tube in BiCMOS technique.This distance values can be monitored on source and drain polysilicon final thickness and then the impact on parasitic capacitance by the distance values (beelines between adjacent two grids between source and drain polysilicon) of a series of grid polycrystalline silicon.In process exploitation and optimizing process, according to the capacitance size change recorded, optimized integrated technique can be selected, improves the performance of device further.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. monitor the test structure of source and drain polycrystalline and pipe side wall stray capacitance for one kind, it is characterized in that: described test structure comprises grid, grid curb wall and source and drain polysilicon, described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer, grid curb wall is formed at the both sides of grid, source and drain polysilicon is formed at the outside of grid curb wall, and grid, grid curb wall and source and drain polysilicon are all positioned at above silica shallow-trench isolation.
2. the test structure of monitoring source and drain polycrystalline according to claim 1 and pipe side wall stray capacitance, is characterized in that: described grid curb wall is made up of nitride film medium and oxide film dielectric.
3. monitor a manufacture method for the test structure of source and drain polycrystalline and pipe side wall stray capacitance, it is characterized in that, comprise the following steps:
1st step, forms silica shallow-trench isolation in a silicon substrate;
2nd step, growth grid oxide layer, deposit one deck grid polycrystalline silicon on it, deposit one deck nitride film medium on grid polycrystalline silicon;
3rd step, chemical wet etching forms grid, and described grid has nitride film medium, grid polycrystalline silicon and grid oxide layer;
4th step, deposit layer oxide film medium, deposit one deck nitride film medium on oxide film dielectric;
5th step, anti-carves nitride film medium and oxide film dielectric forms grid curb wall;
6th step, deposit emitter-polysilicon;
7th step, anti-carve and form source and drain polysilicon, described source and drain polysilicon is positioned in silica shallow-trench isolation.
4. the manufacture method of the test structure of monitoring source and drain polycrystalline according to claim 3 and pipe side wall stray capacitance, is characterized in that, in the 3rd step, the nitride film medium of whole silicon chip applies photoresist, and chemical wet etching forms grid.
5. monitor the test structure of source and drain polycrystalline and pipe side wall stray capacitance for one kind, it is characterized in that: described test structure is the many fingers structure be formed in silica shallow-trench isolation, this many fingers structure is alternately made up of multiple grid and multiple source and drain polysilicon, and the outermost referring to structure is the grid of redundancy structure more, the both sides of described each grid are grid curb wall, the described multiple source and drain polysilicons referred in structure draw formation source and drain exit more, and the multiple grids between source and drain polysilicon draw formation gate terminal.
6. the test structure of monitoring source and drain polycrystalline according to claim 5 and pipe side wall stray capacitance, is characterized in that: described grid comprises grid oxide layer and is positioned at the grid polycrystalline silicon above grid oxide layer.
7. the test structure of monitoring source and drain polycrystalline according to claim 5 and pipe side wall stray capacitance, is characterized in that: describedly refer to that the grid of outermost two redundancy structures of structure is electrically connected more.
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| CN104465432A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Structure for monitoring stray capacitance |
| TWI571970B (en) * | 2015-10-13 | 2017-02-21 | 力晶科技股份有限公司 | Static random access memory and manufacturing method thereof |
| CN108899368B (en) * | 2018-06-29 | 2022-05-20 | 上海华虹宏力半导体制造有限公司 | Structure and process method for monitoring doping of intrinsic base region of self-aligned germanium-silicon HBT device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4043025A (en) * | 1975-05-08 | 1977-08-23 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | MOSFET structure and manufacturing method thereof |
| CN201956352U (en) * | 2010-12-27 | 2011-08-31 | 上海集成电路研发中心有限公司 | Test and calibration structure for capacitor with MOSFET (metal-oxide-semiconductor field effect transistor) grid overlapped with source and drain |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4043025A (en) * | 1975-05-08 | 1977-08-23 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
| CN102117750A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | MOSFET structure and manufacturing method thereof |
| CN201956352U (en) * | 2010-12-27 | 2011-08-31 | 上海集成电路研发中心有限公司 | Test and calibration structure for capacitor with MOSFET (metal-oxide-semiconductor field effect transistor) grid overlapped with source and drain |
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