CN103137594A - Novel semiconductor lead frame - Google Patents
Novel semiconductor lead frame Download PDFInfo
- Publication number
- CN103137594A CN103137594A CN2011103974581A CN201110397458A CN103137594A CN 103137594 A CN103137594 A CN 103137594A CN 2011103974581 A CN2011103974581 A CN 2011103974581A CN 201110397458 A CN201110397458 A CN 201110397458A CN 103137594 A CN103137594 A CN 103137594A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- semiconductor lead
- new semiconductor
- row
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a novel semiconductor lead frame. The novel semiconductor lead frame comprises a frame base plate. The novel semiconductor lead frame is characterized in that at least seven chip package units are arranged on the frame base plate. The chip package units are distributed on the frame base plate in a permutable mode, wherein the chip package units are in a multiple rows and two lines mode. The design of the position of the chips of the novel semiconductor lead frame can not only meet practical needs, but also can optimize the structure, so that the number of lead feet and leads is reduced, defects caused by the package can be reduced and product yield can be increased.
Description
Technical field
The present invention relates to a kind of Intelligent Power Module of 26 pins, relate to more specifically a kind of new semiconductor lead frame.
Background technology
About semi-conductive lead frame, all first fixed chip at present, carry out pin by lead-in wire again and be connected with pad and carry out conducting, in addition, the design of lead frame in the prior art generally has single-chip or dual chip, structure is single, the diversity of not meeting the need of market, as the demand of air-conditioning system about the temperature debugging, and the quantity of pin and lead-in wire is more, encapsulation is caused bad impact, reduced the yield of product.
Summary of the invention
The objective of the invention is to address the aforementioned drawbacks, a kind of new semiconductor lead frame is provided, fix seven chips on lead frame, can satisfy air-conditioning system about the demand of temperature debugging, and this Stability Analysis of Structures, can be good at improving quality.
Content of the present invention is: a kind of new semiconductor lead frame, comprise frame base, it is characterized in that, be provided with at least seven each and every one chip packaging units on described frame base, described chip packaging unit with many row's two row form arranged distribution on described frame base.
Described chip packaging unit comprises the Ji Dao of six of one of first row and secondary series, and is distributed in 22 lead district of seven described basic island peripheries.
Be electrically connected by lead-in wire between every adjacent described chip packaging unit, between every adjacent legs, nothing is intersected.
It is a kind of in square and rectangle that described Ji Dao is, and 22 described lead district are arranged along upside and the outside of the two described Ji Dao of row.
22 described lead district stretch out and form 22 outer pins.
The distance of every adjacent outer pin is 0.98mm～1.02mm.
Compared with prior art, the present invention has the following advantages: lead frame of the present invention has changed the general single-chip of existing semiconductor or dual chip pattern, at least seven chips have been adopted, well satisfied the demand of air-conditioning system for the temperature debugging, structurally optimized simultaneously the position of chip, reduced the quantity of pin and lead-in wire as far as possible, avoid because of encapsulation bring bad, and this Stability Analysis of Structures can be good at improving quality.
Description of drawings
Fig. 1 is structural representation of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
with reference to shown in Figure 1, comprise frame base 1, be provided with at least seven each and every one chip packaging units 2 on frame base 1, chip packaging unit 2 with many row's two row form arranged distribution on frame base 1, chip packaging unit 2 comprises the basic island 3 of six of one of first row and secondary series, with 22 lead district 4 that are distributed in seven basic island 3 peripheries, be electrically connected by lead-in wire 5 between every adjacent chip packaging unit 2, between every adjacent legs 5, nothing is intersected, base island 3 is in square or rectangle any, 22 lead district 4 are arranged along upside and the outside of two row Ji Dao, 22 lead district 4 stretch out and form 22 outer pins 6, the distance of every adjacent outer pin 6 is 0.98mm～1.02mm.
Purpose of the present invention has provided description of the preferred embodiment of the present invention; can make the present invention of those skilled in the art's comprehend; but do not limit the present invention in any way; and anyly can modify or be equal to replacement the present invention, all should be encompassed in the protection range of patent of the present invention.
Claims (6)
1. a new semiconductor lead frame, comprise frame base, it is characterized in that, is provided with at least seven each and every one chip packaging units on described frame base, described chip packaging unit with many row's two row form arranged distribution on described frame base.
2. a kind of new semiconductor lead frame as claimed in claim 1, is characterized in that, described chip packaging unit comprises the Ji Dao of six of one of first row and secondary series, and be distributed in 22 lead district of seven described basic island peripheries.
3. a kind of new semiconductor lead frame as claimed in claim 1, is characterized in that, is electrically connected by lead-in wire between every adjacent described chip packaging unit, and between every adjacent legs, nothing is intersected.
4. a kind of new semiconductor lead frame as claimed in claim 2, is characterized in that, it is a kind of in square and rectangle that described Ji Dao is, and 22 described lead district are arranged along upside and the outside of the two described Ji Dao of row.
5. a kind of new semiconductor lead frame as claimed in claim 2, is characterized in that, 22 described lead district stretch out and form 22 outer pins.
6. a kind of new semiconductor lead frame as claimed in claim 5, is characterized in that, the distance of every adjacent outer pin is 0.98mm～1.02mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103974581A CN103137594A (en) | 2011-12-05 | 2011-12-05 | Novel semiconductor lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103974581A CN103137594A (en) | 2011-12-05 | 2011-12-05 | Novel semiconductor lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103137594A true CN103137594A (en) | 2013-06-05 |
Family
ID=48497207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103974581A Pending CN103137594A (en) | 2011-12-05 | 2011-12-05 | Novel semiconductor lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103137594A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010900A (en) * | 2017-12-20 | 2018-05-08 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030141579A1 (en) * | 2002-01-28 | 2003-07-31 | Yoshinori Oda | Lead frame for resin-molded semiconductor device |
| CN201681908U (en) * | 2010-05-05 | 2010-12-22 | 江苏长电科技股份有限公司 | Insular base exposure and multi-convex-point insular base exposure type multi-circle lead foot passive device packaging structure |
| CN102034784A (en) * | 2010-11-10 | 2011-04-27 | 吴江巨丰电子有限公司 | 28K lead frame |
| CN201859875U (en) * | 2010-10-28 | 2011-06-08 | 吴江巨丰电子有限公司 | 8N lead wire framework |
| CN202394948U (en) * | 2011-12-05 | 2012-08-22 | 正文电子(苏州)有限公司 | New semiconductor lead frame |
-
2011
- 2011-12-05 CN CN2011103974581A patent/CN103137594A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030141579A1 (en) * | 2002-01-28 | 2003-07-31 | Yoshinori Oda | Lead frame for resin-molded semiconductor device |
| CN201681908U (en) * | 2010-05-05 | 2010-12-22 | 江苏长电科技股份有限公司 | Insular base exposure and multi-convex-point insular base exposure type multi-circle lead foot passive device packaging structure |
| CN201859875U (en) * | 2010-10-28 | 2011-06-08 | 吴江巨丰电子有限公司 | 8N lead wire framework |
| CN102034784A (en) * | 2010-11-10 | 2011-04-27 | 吴江巨丰电子有限公司 | 28K lead frame |
| CN202394948U (en) * | 2011-12-05 | 2012-08-22 | 正文电子(苏州)有限公司 | New semiconductor lead frame |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010900A (en) * | 2017-12-20 | 2018-05-08 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130605 |