CN103137061B - Shift register cell, gate driver circuit and display device - Google Patents
Shift register cell, gate driver circuit and display device Download PDFInfo
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- CN103137061B CN103137061B CN201310052893.XA CN201310052893A CN103137061B CN 103137061 B CN103137061 B CN 103137061B CN 201310052893 A CN201310052893 A CN 201310052893A CN 103137061 B CN103137061 B CN 103137061B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a kind of shift register cell, gate driver circuit and display device, this shift register cell has a capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end is connected with pull-up node, described shift register cell also comprises the first drop-down unit and the second drop-down unit, described first drop-down unit comprises at least two the first transistors, described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, output low level signal is to described output node at the corresponding levels in turn, when described pull-up node is in the drop-down stage, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and output low level signal is to described pull-up node in turn.
Description
Technical field
The present invention relates to shift LD technology, particularly a kind of shift register cell, gate driver circuit and display device.
Background technology
Grid impulse output register is integrated on panel by integrated gate shift register, thus saves IC, reduces cost.The implementation method of integrated gate shift register has a variety of, and can comprise different multiple transistor and electric capacity, conventional has 12T1C, the structures such as 9T1C, 13T1C.
Generally speaking, a shift register is made up of multi-stage shift register unit, and every one-level shift register cell just exports a high level signal within the extremely short time, and all can output low level signal at other times, is generally VSS signal.
At least there is the lower shortcoming of life of product in the shift register of prior art, is described as follows this.
Mention above, every one-level shift register cell just exports a high level signal within the extremely short time, and all can output low level signal at other times, in order to ensure shift register cell output low level signal, then need, to pull-up node and output node output low level signal, to be generally VSS.That is, the time to pull-up node and output node output low level signal is very long, and this time accounts for more than 99% usually.
And simultaneously, this VSS signal is all exported by pull-down transistor, and this just needs pull-down transistor to be in the state of high level conducting, to export VSS signal to pull-up node and output node.
Can find from the above description, the grid of pull-down transistor is in high level state for a long time, this will cause making pull-down transistor faster than other transistor ageings in shift register cell, shortens the serviceable life of product.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of shift register cell, gate driver circuit and display device, improves the life-span of shift register.
To achieve these goals, embodiments provide a kind of shift register cell, described shift register cell has a capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end is connected with pull-up node, described shift register cell also comprises the second drop-down unit for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and the current potential for drop-down described pull-up node, described first drop-down unit comprises at least two the first transistors, described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, output low level signal is to described output node at the corresponding levels in turn, when described pull-up node is in the drop-down stage, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and output low level signal is to described pull-up node in turn.
Above-mentioned shift register cell, wherein, also comprises:
Transistor T1, source electrode is connected with described output node at the corresponding levels with the signal output part sub-connection exporting the second control signal, drain electrode, and grid is connected with pull-up node; When output node at the corresponding levels needs to export high level signal, described second control signal is in high level;
Transistor T3, source electrode is connected with upper level output node, and drain electrode is connected with described pull-up node, and grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level;
Described at least two transistor secondses comprise described transistor T3, and the low level signal that described pull-up node receives comprises the low level signal of the described upper level output node output exported by described transistor T3.
Above-mentioned shift register cell, wherein, described at least two transistor secondses also comprise transistor T4, and source electrode is connected with next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal; The low level signal that described pull-up node receives comprises the low level signal of the described next stage output node output exported by described transistor T4.
Above-mentioned shift register cell, wherein, also comprises:
Transistor T2, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, and grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level;
Described at least two the first transistors comprise described transistor T2, and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals exported by described transistor (T2).
Above-mentioned shift register cell, wherein,
Described at least two the first transistors comprise:
Transistor T2, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the first control signal;
Transistor T6, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 3rd control signal;
Transistor T7, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal;
Described at least two transistor secondses comprise:
Transistor T3, source electrode is connected with upper level output node, and drain electrode is connected with pull-up node, grid and the signal output part sub-connection exporting the first control signal;
Transistor T4, source electrode is connected with next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal;
Transistor T5, source electrode is connected with output node at the corresponding levels with the signal output part sub-connection exporting cut-off signals, drain electrode, grid and the signal output part sub-connection exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described first control signal, the second control signal, the 3rd control signal, the 4th control signal is 1/4, and is in the time period non-overlapping copies of high level;
When upper level output node exports high level, described first control signal is in high level;
When output node at the corresponding levels needs to export high level signal, described second control signal is in high level;
When next stage output node exports high level, described 3rd control signal is in high level.
In order to better realize above-mentioned purpose, the embodiment of the present invention additionally provides a kind of gate driver circuit, comprises multistage shift register cell as claimed in claim.
In order to better realize above-mentioned purpose, the embodiment of the present invention additionally provides a kind of display device, comprises above-mentioned gate driver circuit.
The embodiment of the present invention has at least one in following beneficial effect:
In the embodiment of the present invention, multiple TFT conducting in turn (namely grid is in high level control in turn) in drop-down unit, therefore, in the drop-down stage, the grid of pull-down transistor only has part-time to be in high level state, reduce the grid dutycycle voltage of pull-down transistor, improve the life-span of pull-down transistor, thus improve the life-span of whole shift register cell.
In the embodiment of the present invention, the multiple TFT conducting output low level in turn signal in drop-down unit, to treating pull-down node, is treated pull-down node and is carried out repeatedly drop-down, decreases the burr of drop-down stage shift register cell output signal;
In the embodiment of the present invention, part in multiple TFT in drop-down unit is the existing TFT in multiplexing shift register cell, decrease number of devices, reduce cost, also make the shift register cell of the embodiment of the present invention be conducive to realizing narrower panel border.
Accompanying drawing explanation
Fig. 1 represents the structural representation of the shift register cell of the embodiment of the present invention;
Fig. 2 represents the signal timing diagram of the shift register cell shown in Fig. 1;
Fig. 3 represents the structural representation of the shift register of the embodiment of the present invention.
Embodiment
The shift register cell of the embodiment of the present invention, in gate driver circuit and display device, eachly treat that drop-down unit corresponding to pull-down node (output node at the corresponding levels and pull-up node) includes at least two TFT, make when needing to be controlled by low level signal until pull-down node, at least two TFT that drop-down unit comprises can be in conducting state in turn, output low level signal is to treating pull-down node, reduce the time that the TFT grid in drop-down unit works under high level state, slow down the aging speed of the TFT in drop-down unit, improve the serviceable life of whole shift register cell.
Before being further elaborated to the embodiment of the present invention, the conceptual illustration first related to the embodiment of the present invention is as follows.
For n-th grade of shift register cell, its course of work is as follows, and it is generally divided into following 4 stages:
Stage A, (n-1)th grade of output node n-1 exports high level, and the high level signal now utilizing upper level output node to export tentatively draws high the level of PU node;
Stage B, the PU node continuing to draw high opens a TFT, and high level signal is outputted to output node at the corresponding levels, makes the output node of n-th grade of shift register cell export high level signal;
Stage C, (n+1)th grade of output node exports high level signal, and PU node and the output node at the corresponding levels of n-th grade of shift register cell drag down by low level signal;
Stage D, until before (n-1)th grade of output node n-1 exports high level, PU node and the output node at the corresponding levels of n-th grade of shift register cell drag down by low level signal next time.
In a particular embodiment of the present invention, this drop-down stage refers to stage C and stage D, the time namely except the stage that output node at the corresponding levels and upper level output node export high level signal.
There is in the shift register cell of the embodiment of the present invention capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end is connected with pull-up node, described shift register cell also comprises the second drop-down unit for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and the current potential for drop-down described pull-up node, wherein, described first drop-down unit comprises at least two the first transistors, described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage needing to control by low level signal, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, output low level signal is to described output node at the corresponding levels in turn, when described pull-up node is in the drop-down stage needing to control by low level signal, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and output low level signal is to described pull-up node in turn.
At this, first should be noted that being in conducting state in turn in the drop-down stage comprises following various situations:
1, conducting state is in turn, and continuous distribution in time; Thisly easily to realize when being distributed in independent design drop-down unit.
2, conducting state is in turn, but discontinuously arranged in time.Thisly to there will be when being distributed in the TFT needed in multiplexing existing shift register cell, as the shift register of 7T1C that will mention later.
In the shift register cell of the embodiment of the present invention, owing to being provided with multiple TFT in each drop-down unit, these TFT conducting in turn (namely grid be in turn high level control), with output low level signal in turn to the node of correspondence.Relative to prior art need until pull-down node by low level signal control time, the grid of pull-down transistor will be in high level state always, TFT in the drop-down unit of the embodiment of the present invention only has part-time to be in high level state, reduce the grid dutycycle voltage of pull-down transistor, improve the life-span of pull-down transistor, thus improve the life-span of whole shift register cell.
Illustrate as follows with the drop-down unit that output node at the corresponding levels is corresponding.
Assuming that gate driver circuit comprises 1024 grades of shift register cells, then method conventionally, then pull-down transistor operationally in, under the time grid of more than 99.9% (1023/1024) is all in the control of high level signal.
And suppose in the method for the embodiment of the present invention, 2 TFT parallel connections, its source electrode connects VSS signal, and drain electrode is connected with output node at the corresponding levels, then when output node at the corresponding levels needs to be in low level signal control, signal then by controlling to output to the grid of 2 TFT is in high level with time interval T in turn, then can ensure that VSS signal constantly outputs to output node at the corresponding levels, simultaneously, when output node at the corresponding levels needs to be in low level signal control, under the grid of each TFT only has part-time to be in the control of high level signal, because this reducing the aging speed of transistor, thus improve the life-span of whole shift register cell.
Meanwhile, in a particular embodiment of the present invention, in the whole drop-down stage, can carry out repeatedly drop-down to PU node and output node at the corresponding levels, the burr of shift register cell output signal can be reduced.
In a particular embodiment of the present invention, the first drop-down unit and the second drop-down unit specifically can be accomplished in several ways, and are described as follows.
< mode one >
First drop-down unit and the second drop-down unit work alone separately, have separately independently control signal.
As the first drop-down unit can be identical with the TFT quantity of the second drop-down unit, also can be different.
As the first drop-down unit has 3 TFT, source electrode receives VSS signal, and drain electrode is connected with output node at the corresponding levels, and the second drop-down unit has 2 TFT, and source electrode all receives VSS signal, and drain electrode is connected with pull-up node.
A kind of reasonable mode is:
The high level signal non-overlapping copies of each self-corresponding 3 control signals of 3 TFT of the first drop-down unit, but within the whole drop-down stage of output node at the corresponding levels continuous distribution.
The high level signal non-overlapping copies of each self-corresponding 2 control signals of 2 TFT of the second drop-down unit, but within the whole drop-down stage of pull-up node continuous distribution.
And these control signals can dutycycle identical, also can dutycycle different, the high level signal non-overlapping copies of each self-corresponding 2 the control signal X1 and X2 of 2 TFT as the second drop-down unit, and within the time period that output node at the corresponding levels needs output low level signal continuous distribution, but the high level lasting time of X1 is longer than the high level lasting time of X1.
< mode two >
For mode one, each drop-down unit works alone separately, is unfavorable for the overall arrangement of control signal, also needs more control signal simultaneously, can cause complex structure.
In mode two, in drop-down unit, TFT quantity is identical, therefore the TFT in different drop-down unit can be divided into groups between two, each group TFT uses identical control signal, the high level distributed area non-overlapping copies of all these control signals, but need simultaneously by continuous distribution in the time period of low level signal control at output node at the corresponding levels and pull-up node.
Certainly, the realization of the drop-down unit in the embodiment of the present invention is not limited to above implementation, and those skilled in the art can realize above-mentioned drop-down unit according to the record of the embodiment of the present invention by alternate manner, do not describe in detail one by one at this.
In a particular embodiment of the present invention, above-mentioned shift register cell also comprises other TFT device, as being in conducting when upper level output node exports high level signal and this high level signal being outputted to PU node to carry out the TFT of precharge, and for example in pre-charging stage, a low level signal is outputted to the TFT of output node at the corresponding levels.
In a particular embodiment of the present invention, above-mentioned drop-down unit can increase new TFT to realize on the basis of above-mentioned existing element, but this will increase the quantity of TFT, increases the complexity realized.
Therefore, in a particular embodiment of the present invention, further consider that multiplexing existing TFT is used as the TFT in drop-down unit, to reduce the quantity of TFT.
In the specific embodiment of the invention, one or more in multiplexing existing TFT can reduce the quantity that shift register cell uses TFT, this just wherein several mode be described as follows.
In existing shift register cell, comprise one for the high level signal that upper level output node exports being outputted to the transistor T3 that pull-up node carries out precharge when upper level output node exports high level signal, its source electrode is connected with upper level output node, drain electrode is connected with described pull-up node, and grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level;
When considering that shift register cell at the corresponding levels is in the drop-down stage, the inevitable output low level signal of upper level shift register cell, based on above consideration, in the specific embodiment of the invention, multiplexing above-mentioned transistor T3 is as a part for the second drop-down unit, that is: described at least two transistor secondses comprise described transistor T3, and the low level signal that described pull-up node receives comprises the low level signal of the described upper level output node output exported by described transistor T3.
In existing shift register, also comprise one for when shift register at the corresponding levels is in pre-charging stage, export the transistor T4 of a low level signal (cut-off signals) to output node at the corresponding levels, its grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level; Therefore, upper level output node exports high level, and the control that transistor T4 is subject to high level signal is in conducting state, exports a cut-off signals to output node at the corresponding levels.
In the prior art, this transistor T4 only needs to work in pre-charging stage, and is in cut-off state in the drop-down stage, therefore, in the specific embodiment of the invention, and all right multiplexing above-mentioned transistor T4, as a part for the first drop-down unit, that is:
Described at least two the first transistors comprise described transistor T2, and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals exported by described transistor T2.
At the shift register cell of prior art, the high level signal that next stage output node exports uses as the reset signal of shift register cell at the corresponding levels, consider that signal that next stage output node exports drags down the stage at shift register cell at the corresponding levels, the overwhelming majority time is in low level state, therefore in a particular embodiment of the present invention, can also TFT for resetting in multiplexing prior art, but for the second drop-down unit after needing the annexation of amendment TFT, in amended TFT, the signal using next stage output node to export uses as degrade signal, under this mode, described at least two transistor secondses also comprise transistor T4, source electrode is connected with next stage output node, drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal, the low level signal that described pull-up node receives comprises the low level signal of the described next stage output node output exported by described transistor (T4).
Under above-mentioned various modes, multiplexing existing at least one transistor T2, T3 or T4, when ensureing that the TFT quantity taken turns to operate in each drop-down unit is enough, reducing the device usage quantity of whole shift register cell, reducing cost and implementation complexity.
The 7T1C shift register cell realized with 4 control signals below describes the course of work and the structure of the shift register cell of the embodiment of the present invention in detail.
As shown in Figure 1, the 7T1C shift register cell of the embodiment of the present invention comprises:
One output node OUTPUT at the corresponding levels;
One end of capacitor cell C, described capacitor cell C is connected with output node OUTPUT at the corresponding levels, and the other end is connected with pull-up node PU;
Transistor T1, source electrode is connected with described output node OUTPUT at the corresponding levels with the signal output part sub-connection exporting the second control signal C2, drain electrode, and grid is connected with pull-up node PU; When output node OUTPUT at the corresponding levels needs to export high level signal, the control of the high level signal that the grid due to transistor T1 exports by PU node, transistor T1 conducting, exports current the second control signal C2 being in high level state;
Transistor T2, source electrode receives cut-off signals VSS, and drain electrode is connected with output node OUTPUT at the corresponding levels, grid and the signal output part sub-connection exporting the first control signal C1; When upper level output node N-1OUT exports high level signal, the grid of transistor T2 controls by the signal C1 being in high level state, transistor T2 conducting, exports cut-off signals VSS to output node OUTPUT at the corresponding levels;
Transistor T3, source electrode is connected with upper level output node N-1OUT, and drain electrode is connected with pull-up node PU, grid and the signal output part sub-connection exporting the first control signal C1; When upper level output node N-1OUT exports high level signal, the grid of transistor T3 controls by the signal C1 being in high level state, transistor T3 conducting, and the high level signal exporting N-1OUT output carries out precharge to PU node.
In a particular embodiment of the present invention, the first drop-down unit for the current potential of drop-down described output node OUTPUT at the corresponding levels is multiplexing transistor T2, and use the current potential of VSS signal to output node OUTPUT at the corresponding levels to carry out drop-down, and for the multiplexing transistor T3 of the second drop-down unit of the current potential of drop-down described pull-up node PU, and use VSS signal, the low level signal that upper level output node N-1OUT exports and the current potential of low level signal to pull-up node PU that next stage output node N+1OUT exports carry out drop-down, as shown in Figure 1, at least two the first transistors that described first drop-down unit comprises are:
Transistor T2;
Transistor T6, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 3rd control signal;
Transistor T7, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal;
At least two transistor secondses that described second drop-down unit comprises comprise:
Transistor T3;
Transistor T4, source electrode is connected with next stage output node, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal;
Transistor T5, source electrode is connected with output node at the corresponding levels with the signal output part sub-connection exporting cut-off signals, drain electrode, grid and the signal output part sub-connection exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described first control signal C1, the second control signal C2, the 3rd control signal C3, the 4th control signal C4 is 1/4, and is in the time period non-overlapping copies of high level;
When upper level output node exports high level, described first control signal is in high level;
When output node at the corresponding levels needs to export high level signal, described second control signal is in high level;
When next stage output node exports high level, described 3rd control signal is in high level.
Be described in detail as follows below in conjunction with the course of work of the signal timing diagram shown in Fig. 2 to above-mentioned 7T1C shift register cell.
First, can find, the signal dutyfactor of C1, C2, C3 and C4 is 1/4, and is in the time period non-overlapping copies of high level, and when upper level output node N-1OUT exports high level, C1 is in high level, and during output node OUTPUT output high level signal at the corresponding levels, C2 is in high level, when next stage output node N+1OUT exports high level, C3 is in high level, and all the other time, C4 was in high level.
In pre-charging stage 1., C1 is high level, and C2, C3, C4 are low level, and N-1OUT is high level, and N+1OUT is low level.Now, T1, T4, T5, T6, T7 end, T2, T3 conducting.The high level signal that then N-1OUT exports outputs to PU node by T3, carries out precharge to T1 grid, and PU point voltage rises, and T2 conducting, export VSS signal to OUTPUT, keep OUTPUT to be in low level.
The pull-up stage 2., C2 is high level, C1, C3, C4 are low level, and N-1OUT is low level, and N+1OUT is low level.T2, T3, T4, T5, T6, T7 end, and PU point current potential continues to raise, and T1 conducting, the C2 being in high level outputs to OUTPUT by T1.
3., C3 is high level to drop-down sub, C1, C2, C4 are low level, and N-1OUT is low level, and N+1OUT is high level.T1, T2, T3, T4, T7 end, and are in C3 control T5, T6 conducting of high level, and output low level signal is to PU node and OUTPUT node respectively, keep PU node and OUTPUT node to be in low level.
4., C4 is high level to drop-down sub, and C1, C2, C3 are low level, and N-1OUT is low level, and N+1OUT is low level.T1, T2, T3, T5, T6 end, and are in C4 control T4, T7 conducting of high level, and the T4 of conducting exports the low level of N+1OUT to PU node, keeps PU node to be in low level.And the T7 of conducting exports VSS low level signal to OUTPUT node, OUTPUT node is kept to be in low level.
5., C1 is high level to drop-down sub, and C2, C3, C4 are low level, N-1OUT is low level, and T1, T4, T5, T6, T7 end, and are in C1 control T2, T3 conducting of high level, the T3 of conducting exports the low level of N-1OUT to PU node, keeps PU node to be in low level.And the T2 of conducting exports VSS low level signal to OUTPUT node, OUTPUT node is kept to be in low level.
Said process 3.-4.-5. moving in circles (can find, the situation discontinuously arranged in time that said process is mentioned before being exactly the embodiment of the present invention, but this does not affect PU node and OUTPUT node is in low level in the whole drop-down stage), until upper level output node N-1OUT exports high level next time.
Illustrate that the beneficial effect of the embodiment of the present invention is as follows below in conjunction with above-mentioned example.
In above-mentioned example, in the drop-down stage, the grid of the TFT in drop-down subelement only has the time of 1/3 to be in high level state, therefore be in for high level state relative to prior art in the whole drop-down stage, the grid reducing TFT is in the time of high level state, slow down the speed that TFT is aging;
In above-mentioned example, in the drop-down stage, PU stage and OUTPUT node are carried out repeatedly drop-down, decrease the burr of output node output signal at the corresponding levels of drop-down stage.
In above-mentioned example, each drop-down subelement includes 3 TFT, but due to the TFT in the multiplexing existing shift register of these TFT, therefore, the increase of integral device quantity is not a lot, reduces costs;
The embodiment of the present invention additionally provides a kind of gate driver circuit, comprises multistage shift register cell as above.
As shown in Figure 3, for utilizing the structural representation of the gate driver circuit of the shift register cell of the specific embodiment of the invention, it comprises multi-stage shift register unit, and wherein the output of upper level is as the input of next stage, and the output of next stage simultaneously feeds back to again upper level and resets.
The embodiment of the present invention additionally provides a kind of display device, comprises above-mentioned gate driver circuit.
More than illustrate just illustrative for the purpose of the present invention; and nonrestrictive, those of ordinary skill in the art understand, when not departing from the spirit and scope that claims limit; many amendments, change or equivalence can be made, but all will fall within the scope of protection of the present invention.
Claims (3)
1. a shift register cell, described shift register cell has a capacitor cell, one end of described capacitor cell is connected with output node at the corresponding levels, the other end is connected with pull-up node, described shift register cell also comprises the second drop-down unit for the first drop-down unit of the current potential of drop-down described output node at the corresponding levels and the current potential for drop-down described pull-up node, it is characterized in that, described first drop-down unit comprises at least two the first transistors, described second drop-down unit comprises at least two transistor secondses, when described output node at the corresponding levels is in the drop-down stage, described at least two the first transistors are in conducting state in turn under the control of each self-corresponding control signal, output low level signal is to described output node at the corresponding levels in turn, when described pull-up node is in the drop-down stage, described at least two transistor secondses are in conducting state in turn under the control of each self-corresponding control signal, and output low level signal is to described pull-up node in turn,
Wherein, the described drop-down stage refers to the time except the stage that described output node at the corresponding levels and upper level output node export high level signal;
Described shift register cell also comprises:
Transistor T3, source electrode is connected with upper level output node, and drain electrode is connected with described pull-up node, and grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level;
Described at least two transistor secondses comprise described transistor T3, and the low level signal that described pull-up node receives comprises the low level signal of the described upper level output node output exported by described transistor T3;
Or
Described shift register cell also comprises:
Transistor T2, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, and grid and a signal exported are in the signal output part sub-connection of high level when upper level output node exports high level;
Described at least two the first transistors comprise described transistor T2, and the low level signal that described output node at the corresponding levels receives comprises the cut-off signals exported by described transistor T2;
Or
Described at least two transistor secondses also comprise transistor T4, and source electrode is connected with next stage output node, and drain electrode is connected with pull-up node, grid and the signal output part sub-connection exporting the 4th control signal; The low level signal that described pull-up node receives comprises the low level signal of the described next stage output node output exported by described transistor T4;
Or
Described shift register cell also comprises:
Transistor T1, source electrode is connected with described output node at the corresponding levels with the signal output part sub-connection exporting the second control signal, drain electrode, and grid is connected with pull-up node; When output node at the corresponding levels needs to export high level signal, described second control signal is in high level;
Described at least two the first transistors comprise:
Transistor T2, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the first control signal;
Transistor T6, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 3rd control signal;
Transistor T7, source electrode receives cut-off signals, and drain electrode is connected with output node at the corresponding levels, grid and the signal output part sub-connection exporting the 4th control signal;
Described at least two transistor secondses comprise:
Transistor T3, source electrode is connected with upper level output node, and drain electrode is connected with pull-up node, grid and the signal output part sub-connection exporting the first control signal;
Transistor T4, source electrode is connected with next stage output node, and drain electrode is connected with pull-up node, grid and the signal output part sub-connection exporting the 4th control signal;
Transistor T5, source electrode is connected with pull-up node with the signal output part sub-connection exporting cut-off signals, drain electrode, grid and the signal output part sub-connection exporting the 3rd control signal;
Wherein:
The signal dutyfactor of described first control signal, the second control signal, the 3rd control signal, the 4th control signal is 1/4, and is in the time period non-overlapping copies of high level;
When upper level output node exports high level, described first control signal is in high level;
When next stage output node exports high level, described 3rd control signal is in high level.
2. a gate driver circuit, is characterized in that, comprises multistage shift register cell as claimed in claim 1.
3. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310052893.XA CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
| PCT/CN2013/074001 WO2014124570A1 (en) | 2013-02-18 | 2013-04-10 | Shift register unit, grid drive circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310052893.XA CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
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| Publication Number | Publication Date |
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| CN103137061A CN103137061A (en) | 2013-06-05 |
| CN103137061B true CN103137061B (en) | 2015-12-09 |
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| CN201310052893.XA Active CN103137061B (en) | 2013-02-18 | 2013-02-18 | Shift register cell, gate driver circuit and display device |
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| CN (1) | CN103137061B (en) |
| WO (1) | WO2014124570A1 (en) |
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| CN104376826B (en) * | 2014-11-20 | 2017-02-01 | 深圳市华星光电技术有限公司 | Shifting register unit, grid driving circuit and displaying device |
| CN104575436B (en) * | 2015-02-06 | 2017-04-05 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN104766573B (en) * | 2015-03-10 | 2017-05-10 | 昆山龙腾光电有限公司 | Gate drive circuit and display device |
| CN105469754B (en) * | 2015-12-04 | 2017-12-01 | 武汉华星光电技术有限公司 | Reduce the GOA circuits of feed-trough voltage |
| CN105390086B (en) * | 2015-12-17 | 2018-03-02 | 武汉华星光电技术有限公司 | Gate driving circuit and the display using gate driving circuit |
| TWI562114B (en) * | 2015-12-30 | 2016-12-11 | Au Optronics Corp | Shift register and shift register circuit |
| CN105427825B (en) * | 2016-01-05 | 2018-02-16 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method and gate driving circuit |
| CN105810166B (en) * | 2016-05-23 | 2019-06-04 | 信利（惠州）智能显示有限公司 | Shift register cell circuit, shift register and its liquid crystal display |
| CN106531048B (en) * | 2016-11-29 | 2020-03-27 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit, display panel and driving method |
| CN106601179B (en) * | 2017-02-24 | 2019-11-22 | 京东方科技集团股份有限公司 | Shifting deposit unit, shift register, gate driving circuit and display panel |
| CN106898322B (en) | 2017-03-29 | 2020-01-21 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN107248401B (en) * | 2017-08-08 | 2020-04-03 | 京东方科技集团股份有限公司 | GOA circuit, driving method thereof and display device |
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| CN103137061A (en) | 2013-06-05 |
| WO2014124570A1 (en) | 2014-08-21 |
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