WO2014124570A1

WO2014124570A1 - Shift register unit, grid drive circuit and display device

Info

Publication number: WO2014124570A1
Application number: PCT/CN2013/074001
Authority: WO
Inventors: 吴博; 祁小敬; 聂磊森
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2013-02-18
Filing date: 2013-04-10
Publication date: 2014-08-21
Also published as: CN103137061B; CN103137061A

Abstract

A shift register unit, a grid drive circuit and a display device. The shift register unit has a capacitor unit (C), an end of the capacitor unit (C) being connected to a current-stage output node (OUTPUT), and the other end thereof being connected to a pull-up node (PU). The shift register unit also comprises a first pull-down unit and a second pull-down unit, the first pull-down unit comprising at least two first transistors (T2, T6 and T7), and the second pull-down unit comprising at least two second transistors (T3, T4 and T5). When the current-stage output node (OUTPUT) is in a pull-down stage, the at least two first transistors (T2, T6 and T7) are in a conductive state under the control of respective corresponding control signals in turn to output a low-level signal in turn to the current-stage output node (OUTPUT); and when the pull-up node (PU) is in a pull-down stage, the at least two second transistors (T3, T4 and T5) are in a conductive state under the control of respective corresponding control signals in turn to output a low-level signal in turn to the pull-up node (PU).

Description

Shift register unit, gate drive circuit and display device

The present invention relates to a shift register technique, and more particularly to a shift register unit, a gate drive circuit and a display device. Background technique

The integrated gate shift register integrates the gate pulse output registers on the panel, saving IC and reducing cost. There are many ways to implement the integrated gate shift register, which can include different transistors and capacitors. The commonly used 12T1C, 9T1C, 13T1C and other structures.

In general, a shift register is composed of multi-stage shift register units, and each stage shift register unit outputs a high level signal only in a very short time, and outputs a low level signal at other times. Usually the VSS signal.

The prior art shift register has at least the disadvantage of a low product life, which is explained below. As mentioned above, each stage of the shift register unit outputs a high level signal only in a very short time, and outputs a low level signal at other times. To ensure that the shift register unit outputs a low level signal, The pull-up node and the output node need to output a low-level signal, usually vss. That is to say, the pull-up node and the output node output a low-level signal for a very long time, which usually accounts for more than 99%.

At the same time, the VSS signal is output through the pull-down transistor, which requires the pull-down transistor to be in a high-level state to output the VSS signal to the pull-up node and the output node.

From the above description, it can be found that the gate of the pull-down transistor is in a high state for a long time, which causes the pull-down transistor to age faster than other transistors in the shift register unit, shortening the service life of the product. Summary of the invention

It is an object of embodiments of the present invention to provide a shift register unit, a gate drive circuit, and a display device to improve the lifetime of the shift register.

In order to achieve the above object, an embodiment of the present invention provides a shift register unit, wherein the shift register unit has a capacitor unit, one end of the capacitor unit is connected to the output node of the current level, and the other end is connected to the pull-up node. The shift register unit further includes a pull-down of the output of the current stage a first pull-down unit of a potential of the node and a second pull-down unit for pulling down a potential of the pull-up node, the first pull-down unit comprising a first set of transistors having at least two transistors, the second pulldown The unit includes a second group of transistors having at least two transistors. When the output node of the current stage is in a pull-down phase, the first group of transistors are turned on under the control of respective control signals, and the output is low in turn. Leveling the signal to the output node of the current stage; when the pull-up node is in the pull-down phase, the second group of transistors are turned on under the control of respective control signals, and output a low-level signal in turn Said pull up the node.

The shift register unit described above, further comprising:

The first transistor T1 has a source connected to a signal output terminal of the output second control signal, a drain connected to the output node of the current stage, and a gate connected to the pull-up node; when the output node of the stage needs to output a high level signal, The second control signal is at a high level;

The third transistor T3 has a source connected to the upper output node, a drain connected to the pull-up node, and a gate and an output signal outputting a signal at a high level when the output node of the upper stage outputs a high level. Connection

The second group of transistors includes the third transistor T3, and the low level signal received by the pull-up node includes a low level signal output by the upper output node output by the third transistor T3. .

In the above shift register unit, the second group of transistors further includes a fourth transistor T4, the drain is connected to the next-stage output node, the source is connected to the pull-up node, and the gate and the signal outputting the fourth control signal are The output terminal is connected; the low level signal received by the pull-up node includes a low level signal output by the next-stage output node output by the fourth transistor T4.

The shift register unit described above, further comprising:

The second transistor T2 has a drain receiving a turn-off signal, a source connected to the output node of the current stage, and a gate and an output signal connected to a signal output terminal at a high level when the output node of the upper stage outputs a high level;

The first group of transistors includes the second transistor T2, and the low level signal received by the current stage output node includes an off signal output by the second transistor (T2).

The shift register unit described above, wherein

The first set of transistors includes:

a second transistor T2, the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate being connected to the signal output terminal outputting the first control signal; a sixth transistor T6, the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate being connected to the signal output terminal outputting the third control signal;

The seventh transistor T7 has a drain receiving a turn-off signal, a source connected to the output node of the current stage, and a gate connected to a signal output terminal outputting the fourth control signal;

The second set of transistors includes:

a third transistor T3, the source is connected to the upper output node, the drain is connected to the pull-up node, and the gate is connected to the signal output terminal outputting the first control signal;

a fourth transistor T4, the drain is connected to the next-stage output node, the source is connected to the pull-up node, and the gate is connected to the signal output terminal outputting the fourth control signal;

The fifth transistor T5 has a drain connected to the signal output terminal of the output turn-off signal, a source connected to the pull-up node, and a gate connected to the signal output terminal outputting the third control signal;

among them:

The signal duty ratios of the first control signal, the second control signal, the third control signal, and the fourth control signal are 1/4, and the periods in the high level do not overlap each other;

When the output node of the upper stage outputs a high level, the first control signal is at a high level; when the output node of the stage needs to output a high level signal, the second control signal is at a high level; When high, the third control signal is at a high level.

In order to achieve the above objectives, an embodiment of the present invention further provides a gate driving circuit including a plurality of shift register units according to the claims.

In order to achieve the above objectives, an embodiment of the present invention further provides a display device including the above-described gate driving circuit.

Embodiments of the invention have at least one of the following beneficial effects:

In the embodiment of the present invention, the plurality of TFTs in the pull-down unit are turned on in turn (that is, the gate turns are in a high level control). Therefore, in the pull-down phase, the gate of the pull-down transistor is only in a high state for a part of time. The gate duty cycle voltage of the pull-down transistor is lowered, the life of the pull-down transistor is increased, and the lifetime of the entire shift register unit is improved.

In the embodiment of the present invention, the plurality of TFTs in the pull-down unit are turned on to output a low-level signal to the node to be pulled down, and the pull-down node is pulled down multiple times to reduce the glitch of the output signal of the shift register unit in the pull-down phase;

In the embodiment of the present invention, a part of the plurality of TFTs in the pull-down unit is an existing TFT in the multiplexed shift register unit, which reduces the number of components, reduces the cost, and also shifts the embodiment of the present invention. The bit register unit facilitates a narrower panel border. DRAWINGS

1 is a block diagram showing the structure of a shift register unit according to an embodiment of the present invention;

Figure 2 is a timing chart showing the signal of the shift register unit shown in Figure 1;

FIG. 3 is a block diagram showing the structure of a shift register according to an embodiment of the present invention. detailed description

In the shift register unit, the gate driving circuit and the display device of the embodiment of the invention, each of the pull-down units corresponding to the node to be pulled down (the output node of the current stage and the pull-up node) includes at least two TFTs, so that the node to be pulled down When it is required to be controlled by the low level signal, at least two TFTs included in the pull-down unit may be turned on in turn, output a low level signal to the node to be pulled down, and reduce the TFT gate in the pull-down unit to operate in a high level state. Time, slowing down the aging speed of the TFT in the pull-down unit and increasing the service life of the entire shift register unit.

Before the embodiments of the present invention are further described in detail, the concepts related to the embodiments of the present invention are described below.

Taking the nth stage shift register unit as an example, the working process is as follows, which is generally divided into the following four stages:

Stage A, the n-1th output node n-1 outputs a high level, at which time the level of the PU node is initially raised by the high level signal outputted by the output node of the upper stage;

In stage B, the PU node that continues to be raised opens a TFT, and outputs a high level signal to the output node of the current stage, so that the output node of the nth stage shift register unit outputs a high level signal;

In stage C, the output node of the n+1th stage outputs a high level signal, and the PU node of the nth stage shift register unit and the output node of the current stage are pulled low by the low level signal;

In phase D, until the next n-1th output node n-1 outputs a high level, the PU node of the nth stage shift register unit and the output node of the current stage are pulled low by the low level signal.

In a particular embodiment of the invention, the pull down phase refers to phase C and phase D, i.e., the time other than the stage in which the output node of the primary stage and the output node of the upper stage output a high level signal.

The shift register unit of the embodiment of the invention has a capacitor unit, one end of the capacitor unit is connected to the output node of the current stage, and the other end is connected to the pull-up node, and the shift register unit further includes a pull-down unit for a first pull-down unit of the potential of the stage output node and for pulling up the pull-up a second pull-down unit of a potential of the node, wherein the first pull-down unit includes at least two first transistors, and the second pull-down unit includes at least two second transistors, where the output node of the current stage is in need of During the pull-down phase of the low-level signal control, the at least two first transistors are turned on in turn under the control of respective control signals, and alternately output a low-level signal to the output node of the current stage; When the pull-up node is in a pull-down phase that needs to be controlled by the low-level signal, the at least two second transistors are turned on under the control of respective control signals, and the low-level signal is alternately outputted to the pull-up node.

Here, first of all, it should be noted that the turn-on phase in the pull-down phase includes the following cases:

1. The turns are in the on state and continuously distributed in time; this distribution is easy to implement when designing the pull-down unit independently.

2. The turns are in the on state, but they are not continuously distributed in time. This distribution occurs when a TFT in an existing shift register unit needs to be multiplexed, as will be mentioned later in the 7T1C shift register.

In the shift register unit of the embodiment of the present invention, since each of the pull-down units is provided with multiple

TFTs, these TFTs are turned on in turn (that is, the gate turns in a high level control) to alternately output a low level signal to the corresponding node. Compared with the prior art, when the gate to be pulled down needs to be controlled by the low level signal, the gate of the pull-down transistor is always in a high state, and the TFT in the pull-down unit of the embodiment of the present invention is only partially high. The level state lowers the gate duty cycle voltage of the pull-down transistor, increasing the lifetime of the pull-down transistor, thereby increasing the lifetime of the entire shift register unit.

The following figure is taken as an example of the pull-down unit corresponding to the output node of this level.

Assuming that the gate driving circuit includes a 1024-stage shift register unit, according to the prior art method, the pull-down transistor is under the control of a high level signal during a working time of 99.9% (1023/1024) or more. .

It is assumed that in the method of the embodiment of the present invention, two TFTs are connected in parallel, the source thereof is connected to the VSS signal, and the drain is connected to the output node of the current stage, then when the output node of the current stage needs to be in the low level signal control, then the control is performed. The signals output to the gates of the two TFTs are alternately held at a high interval T at a time interval T, so that the VSS signal can be continuously outputted to the output node of the current stage, and at the same time, when the output node of the current stage needs to be under the control of the low level signal, The gate of each TFT is only under partial control of the high level signal, thus reducing the aging speed of the transistor, thereby improving the overall shift register unit. Life expectancy.

In the meantime, in the specific embodiment of the present invention, the PU node and the output node of the current stage are pulled down multiple times during the entire pull-down phase, which can reduce the glitch of the output signal of the shift register unit.

In a specific embodiment of the present invention, the first pull-down unit and the second pull-down unit may be specifically implemented in various manners, as explained below.

The first pull down unit and the second pull down unit each operate independently and have respective independent control signals. The number of TFTs of the first pull-down unit and the second pull-down unit may be the same or different. For example, the first pull-down unit has three TFTs, the source receives the VSS signal, and the drain is connected to the output node of the current stage, and the second pull-down unit has two TFTs, the source receives the VSS signal, and the drain and the pull-up Node connection.

Preferably:

The high-level signals of the three control signals corresponding to the three TFTs of the first pull-down unit do not overlap each other, but are continuously distributed throughout the pull-down phase of the output node of the current stage.

The high level signals of the two control signals corresponding to the two TFTs of the second pull-down unit do not overlap each other, but are continuously distributed throughout the pull-down phase of the pull-up node.

The control signals may have the same duty ratio or different duty ratios. For example, the two control signals XI and X2 of the two TFTs of the second pull-down unit do not overlap each other, and are output at the same level. The node needs to continuously distribute the low-level signal for a period of time, but the high-level duration of XI is longer than the high-level duration of XI.

For the first embodiment, each of the pull-down units work independently, which is not conducive to the overall arrangement of the control signals, and also requires more control signals, which leads to a complicated structure.

In the second embodiment, the number of TFTs in the pull-down unit is the same, so the TFTs in different pull-down units can be grouped into two groups, and each group of TFTs uses the same control signal, and the high-level distribution intervals of all the control signals do not overlap each other. However, the output node and the pull-up node of the current stage need to be continuously distributed within a time period controlled by the low-level signal.

Of course, the implementation of the pull-down unit in the embodiment of the present invention is not limited to the above implementation manner, and those skilled in the art may implement the above-mentioned pull-down unit in other manners according to the description of the embodiments of the present invention, which is not described in detail.

In a specific embodiment of the present invention, the above shift register unit further includes other TFTs a device, such as a TFT that is turned on when the output node of the upper stage outputs a high level signal and outputs the high level signal to the PU node for precharging, and, as in the precharge phase, outputs a low level signal. The TFT to the output node of this level.

In the specific embodiment of the present invention, the above-mentioned pull-down unit can be implemented by adding a new TFT to the existing components, but this will increase the number of TFTs and increase the complexity of implementation.

Therefore, in a specific embodiment of the present invention, further multiplexing of an existing TFT as a TFT in a pull-down unit is further considered to reduce the number of TFTs.

In a particular embodiment of the invention, one or more of the existing TFTs may be multiplexed to reduce the number of TFTs used by the shift register unit, several of which are described below.

The existing shift register unit includes a transistor T3 for outputting a high level signal outputted by the upper stage output node to the pull-up node for pre-charging when the upper stage output node outputs a high level signal, The source is connected to the upper output node, the drain is connected to the pull-up node, and the gate and an output signal are connected at a signal output terminal that is at a high level when the output node of the upper stage outputs a high level;

Considering that the shift register unit of the first stage is in the pull-down phase, the shift register unit of the first stage necessarily outputs a low level signal. Based on the above considerations, in the specific embodiment of the present invention, the transistor T3 is multiplexed as the second pull-down unit. a part of the circuit, that is, the at least two second transistors include the transistor T3, and the low level signal received by the pull-up node includes a low output of the upper-stage output node output by the transistor T3. Level signal.

The existing shift register further includes a transistor T4 for outputting a low level signal (off signal) to the output node of the current stage when the shift register of the stage is in the precharge stage, and the gate and the gate The output signal is connected to the signal output terminal that is at a high level when the output node of the upper stage outputs a high level; therefore, the output node of the upper stage outputs a high level, and the transistor T4 is controlled by the high level signal, and the output is turned on. A shutdown signal to the output node of this level.

In the prior art, the transistor T4 only needs to function in the pre-charging phase, and is in the off state in the pull-down phase. Therefore, in the specific embodiment of the present invention, the transistor T4 described above can also be multiplexed as the first pull-down. Part of the unit, namely:

The at least two first transistors include the transistor T2, and the low level signal received by the output node of the present stage includes an off signal output by the transistor T2.

In the prior art shift register unit, the high level signal outputted by the output node of the next stage is used as a reset signal of the shift register unit of the stage, taking into account the output of the output node of the next stage. In the pull-down phase of the shift register unit of the current stage, most of the time is in a low state, so in the specific embodiment of the present invention, the TFT for resetting in the prior art can also be multiplexed, but needs to be modified. The connection relationship of the TFT is used for the second pull-down unit. In the modified TFT, the signal output by the output node of the next stage is used as the pull-down signal. In this embodiment, the at least two second transistors further include a transistor. T4, the source is connected to the output node of the next stage, the drain is connected to the output node of the current stage, and the gate is connected with the signal output terminal of the output fourth control signal; the low level signal received by the pull-up node includes a low level signal output by the next stage output node output by the transistor (T4).

In the above various embodiments, the existing at least one transistor T2, Τ3 or Τ4 is multiplexed, and the entire shift register unit is reduced in the case of ensuring that the number of TFTs operating in each pull-down unit is sufficient. The number of devices used reduces cost and implementation complexity.

The operation and structure of the shift register unit of the embodiment of the present invention will be described in detail below with the 7T1C shift register unit implemented by four control signals.

As shown in FIG. 1, the 7T1C shift register unit of the embodiment of the present invention includes:

a level output node OUTPUT;

a capacitor unit C, one end of the capacitor unit C is connected to the output node OUTPUT of the current stage, and the other end is connected to the pull-up node PU;

The transistor T1 has a source connected to the signal output terminal of the output second control signal C2, a drain connected to the output node OUTPUT of the current stage, and a gate connected to the pull-up node PU; when the output node OUTPUT of the stage needs to output a high level In the signal, since the gate of the transistor T1 is controlled by the high level signal output by the PU node, the transistor T1 is turned on, and outputs the second control signal C2 that is currently in a high state;

Transistor T2, the drain receives the turn-off signal VSS, the source is connected to the output node OUTPUT of the current stage, and the gate is connected to the signal output terminal of the output first control signal C1; when the upper output node N-1 OUT outputs a high level In the signal, the gate of the transistor T2 is controlled by the signal C1 in a high state, the transistor T2 is turned on, and the output off signal VSS is outputted to the output node OUTPUT of the current stage;

The transistor T3 has a source connected to the upper output node N-1 OUT, a drain connected to the pull-up node PU, and a gate connected to a signal output terminal outputting the first control signal C1; when the upper output node N-1 When OUT outputs a high level signal, the gate of transistor T3 is controlled by signal C1 in a high state, transistor T3 is turned on, and a high level signal output by N-1 OUT is output to the PU node for precharging. In a specific embodiment of the present invention, the first pull-down unit for pulling down the potential of the output node OUTPUT of the present stage multiplexes the transistor T2, and uses the VSS signal to pull down the potential of the output node OUTPUT of the current stage, and is used for The second pull-down unit that pulls down the potential of the pull-up node PU multiplexes the transistor T3, and uses the VSS signal, the low-level signal outputted by the upper-stage output node N-1 OUT, and the next-stage output node N+1 OUT The output low level signal pulls down the potential of the pull-up node PU, as shown in FIG. 1, the first pull-down unit includes at least two first transistors: a transistor T2;

Transistor T6, the drain receives the turn-off signal, the source is connected to the output node of the current stage, and the gate is connected to the signal output terminal of the output third control signal;

Transistor T7, the drain receives the turn-off signal, the source is connected to the output node of the current stage, and the gate is connected to the signal output terminal of the output fourth control signal;

The at least two second transistors included in the second pull-down unit include:

Transistor T3;

Transistor T4, the drain is connected to the next-stage output node, the source is connected to the pull-up node, and the gate is connected to the signal output terminal of the output fourth control signal;

The transistor T5 has a drain connected to a signal output terminal of the output turn-off signal, a source connected to the pull-up node, and a gate connected to a signal output terminal outputting the third control signal;

among them:

The signal duty ratios of the first control signal C1, the second control signal C2, the third control signal C3, and the fourth control signal C4 are 1/4, and the periods of the high level do not overlap each other;

The operation of the above 7T1C shift register unit will be described in detail below with reference to the signal timing diagram shown in FIG.

First, it can be found that the duty ratios of Cl, C2, C3, and C4 are both 1/4, and the periods in which the high level is high do not overlap each other, and when the output node N-1 OUT of the upper stage outputs a high level, C1 is at a high level, and when the output node OUTPUT of this stage outputs a high level signal, C2 is at a high level, and when the next stage output node N+1 OUT outputs a high level, C3 is at a high level, and the remaining time C4 is at a high level. Level.

In the pre-charging phase Φ, C1 is high, C2, C3, C4 are low, N-1 OUT is high Level, N+I OUT is 氐 level. At JHI, Tl, Τ4, Τ5, Τ6, Τ7 are off, Τ2, Τ3 are on. Then, the high level signal output by N-1 OUT is output to the PU node through T3, the T1 gate is precharged, the PU point voltage rises, and T2 is turned on, and the VSS signal is output to OUTPUT, keeping OUTPUT low.

In the pull-up phase <2, C2 is high, Cl, C3, C4 are low, N-1 OUT is low, and N+1 0UT is low. T2, Τ3, Τ4, Τ5, Τ6, Τ7 are cut off, and the potential of the PU point continues to rise, T1 is turned on, and C2 at the high level is output to OUTPUT through T1.

Pull-down sub-phase Θ , C3 is high, Cl, C2, C4 are low, N-1 OUT is low, and N+1 0UT is high. Tl, Τ2, Τ3, Τ4, Τ7 are off, C3 control at high level T5, Τ6 are turned on, respectively output low-level signals to the PU node and OUTPUT node, keeping the PU node and the OUTPUT node at a low level.

In the pull-down sub-phase, C4 is high, Cl, C2, C3 are low, N-1 OUT is low, and N+1 0UT is low. Tl, Τ2, Τ3, Τ5, Τ6 are cut off, C4 control at high level T4, Τ7 is turned on, and 导4 output is turned on to low level of N+1 OUT to the PU node, keeping the PU node at a low level. The turned-on T7 outputs a VSS low signal to the OUTPUT node, keeping the OUTPUT node low.

Pull-down sub-stage 6), C1 is high level, C2, C3, C4 are low level, N-1 OUT is low level, Tl, Τ4, Τ5, Τ6, Τ7 are off, C1 control is at high level Τ2 Τ3 is turned on, and the turned-on Τ3 outputs a low level of N-1 OUT to the PU node, keeping the PU node at a low level. The turned-on T2 outputs a VSS low signal to the OUTPUT node, keeping the OUTPUT node low.

The above process 3) - - ® cycle back and forth (it can be found that the above process is the case of discontinuous distribution in time mentioned before the embodiment of the present invention, but this does not affect the PU node and the OUTPUT node are in low power throughout the pull-down phase. Flat) until the next higher output node N-10UT outputs a high level.

The beneficial effects of the embodiments of the present invention will be described below in conjunction with the above examples.

In the above example, in the pull-down phase, the gate of the TFT in the pull-down sub-cell is in a high state for only 1/3 of the time, and thus is in a high state state in the entire pull-down phase with respect to the prior art. , reducing the time when the gate of the TFT is in a high state, slowing down the aging speed of the TFT; in the above example, in the pull-down phase, the PU phase and the OUTPUT node are pulled down multiple times, reducing the pull-down phase The glitch of the output signal of the stage output node. In the above example, each of the pull-down sub-units includes three TFTs, but since these TFTs multiplex the TFTs in the existing shift registers, the overall number of devices is not increased by more than 4, which reduces the cost;

Embodiments of the present invention also provide a gate driving circuit including a plurality of stages of shift register units as described above.

3 is a schematic structural diagram of a gate driving circuit of a shift register unit using a specific embodiment of the present invention, which includes a multi-stage shift register unit, wherein an output of a previous stage is used as an input of a next stage, and The output of the next stage is fed back to the previous level for reset.

Embodiments of the present invention also provide a display device including the above-described gate driving circuit.

The above description is intended to be illustrative, and not restrictive, and many modifications, variations, etc. may be made without departing from the spirit and scope of the appended claims. Effective, but all fall within the scope of protection of the present invention.

Claims

Claim

A shift register unit, the shift register unit has a capacitor unit, one end of the capacitor unit is connected to an output node of the current stage, and the other end is connected to a pull-up node, and the shift register unit further includes a first pull-down unit for pulling down a potential of the output node of the current stage and a second pull-down unit for pulling down a potential of the pull-up node, wherein the first pull-down unit includes a first one having at least two transistors a set of transistors, the second pull-down unit includes a second set of transistors having at least two transistors, and when the output node of the current stage is in a pull-down phase, the first set of transistors are alternated under the control of respective control signals In a conducting state, a low-level signal is alternately outputted to the output node of the current stage; when the pull-up node is in a pull-down phase, the second group of transistors are turned on under the control of respective control signals. , alternately output a low level signal to the pull up node.

2. The shift register unit of claim 1, further comprising:

a third transistor (T3), the source is connected to the output node of the upper stage, the drain is connected to the pull-up node, and the signal of the gate and an output is at a high level when the output node of the upper stage outputs a high level. Output terminal connection;

The second group of transistors includes the third transistor (T3), and the low level signal received by the pull-up node includes the output of the upper-level output node output by the third transistor (T3) Low level signal.

3. The shift register unit of claim 1, further comprising:

a second transistor (T2), the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate and the output signal are connected at a signal output terminal that is at a high level when the output node of the upper stage outputs a high level;

The first group of transistors includes the second transistor (T2), and the low level signal received by the output node of the current stage includes an off signal output by the second transistor (T2).

4. The shift register unit according to claim 1, wherein the second group of transistors further comprises a fourth transistor (T4), the drain is connected to the next-stage output node, the source is connected to the pull-up node, and the gate is connected. The pole is connected to the signal output terminal that outputs the fourth control signal; the low level signal received by the pull-up node includes the low level output by the next-stage output node output by the fourth transistor (T4) signal.

5. The shift register unit of claim 1, further comprising: The first transistor (T1) has a source connected to the signal output terminal of the output second control signal, a drain connected to the output node of the current stage, and a gate connected to the pull-up node; the output node of the stage needs to output a high level signal The second control signal is at a high level;

The first set of transistors includes:

a second transistor (T2), the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate being connected to the signal output terminal outputting the first control signal;

a sixth transistor (T6), the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate being connected to the signal output terminal outputting the third control signal;

a seventh transistor (T7), the drain receiving the turn-off signal, the source being connected to the output node of the current stage, and the gate being connected to the signal output terminal outputting the fourth control signal;

The second set of transistors includes:

a third transistor (T3), the source is connected to the upper output node, the drain is connected to the pull-up node, and the gate is connected to the signal output terminal outputting the first control signal;

a fourth transistor (T4) having a drain connected to the next stage output node, a drain connected to the pull-up node, and a gate connected to a signal output terminal outputting the fourth control signal;

a fifth transistor (T5) having a drain connected to a signal output terminal of the output turn-off signal, a source connected to the pull-up node, and a gate connected to a signal output terminal outputting the third control signal;

among them:

When the output node of the upper stage outputs a high level, the first control signal is at a high level; and when the output node of the next stage outputs a high level, the third control signal is at a high level.

A gate driving circuit comprising a plurality of shift register units according to any one of claims 1-5.

A display device comprising the gate drive circuit of claim 6.