CN101425340B - Shifting cache apparatus - Google Patents
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- CN101425340B CN101425340B CN2008101838152A CN200810183815A CN101425340B CN 101425340 B CN101425340 B CN 101425340B CN 2008101838152 A CN2008101838152 A CN 2008101838152A CN 200810183815 A CN200810183815 A CN 200810183815A CN 101425340 B CN101425340 B CN 101425340B
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Abstract
The invention provides a shift buffer memory. The pull-down unit of the shift buffer memory at each level is controlled by the shift buffer memory of the same level, of the previous level and of the next two levels to enhance the pull-down and the voltage-stabilizing capacities of the pull-down unit. In this way, the circuit structure of shift buffer memory at each level can inhibit the impact of the coupled noises brought by clock pulse signals significantly without designing a larger compensation capacitor additionally, thereby the shift buffer memory at each level is allowed to be collocated with a smaller compensation capacitor to strengthen the output capacity of the shift buffer memory at each level.
Description
Technical field
The invention relates to a kind of shifting cache apparatus, and particularly relevant for a kind of shifting cache apparatus with the ability that suppresses coupled noise.
Background technology
In recent years, along with semiconductor science and technology is flourish, pocket electronic product and flat-panel screens product also rise thereupon.And in the middle of the type of numerous flat-panel screens, (Liquid CrystalDisplay LCD) based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, has become the main flow of display product to LCD immediately.Also, ordering about each tame manufacturer invariably and will and hang down the cost of manufacture development towards microminiaturization at the development technique of LCD also because of so.
For the cost of manufacture of LCD being forced down, existing partly manufacturer sees through amorphous silicon technology and directly make multistage amorphous silicon offset buffer (a-Si shift register) on glass substrate, uses to replace the known gate drivers of habitually practising (gate driver).Thus, can reach the cost of manufacture that reduces LCD.
Yet, output signal (that is sweep signal) less stable of traditional amorphous silicon shift cache circuit, it is easy to be subjected to the coupling of outside clock signal and produces excessive noise (can be regarded as coupled noise), thus the logic that leads to errors output.Tradition is in order to reduce the influence that this coupled noise brings, in each amorphous silicon circuit structure of shift buffer memory, all can design a bigger building-out capacitor suppressing this coupled noise, but practice fan-out capability that can increase the layout area of amorphous silicon offset buffer and weaken the amorphous silicon offset buffer like this.
Summary of the invention
In view of this, the invention provides a kind of shifting cache apparatus, it has both simultaneously the characteristic that suppresses coupled noise and high fan-out capability.
The invention provides a kind of shifting cache apparatus, it comprises the multistage offset buffer that is serially connected each other, and each offset buffer comprises a pull-up unit, a control module and a drop-down unit respectively.
In an one exemplary embodiment of the present invention, the pull-up unit of i level offset buffer can receive one first sweep signal that a clock pulse signal and (i-1) level offset buffer is exported accordingly, and provides according to this and draw signal and decision whether to export one second sweep signal on one.The control module of i level offset buffer can receive described clock signal and described on draw signal, and export one second control signal according to this.
The drop-down unit of i level offset buffer can couple the pull-up unit of i level offset buffer and the control module of control module and (i-1) level offset buffer, in order to receiving and to be controlled by one first control signal that the control module of described second control signal, (i-1) level offset buffer is exported, and one the 4th sweep signal exported of (i+2) level offset buffer.Wherein, when i level offset buffer was not exported described second sweep signal, the drop-down unit of i level offset buffer can cause the stable output of i level offset buffer one reference voltage, and i is the positive integer more than or equal to 2.
In an one exemplary embodiment of the present invention, the pull-up unit of i level offset buffer comprises the first transistor and transistor seconds.Wherein, the grid of the first transistor is coupled in its first leakage/source electrode, to receive described first sweep signal.The grid of transistor seconds couples the second leakage/source electrode of the first transistor, and the first leakage/source electrode of transistor seconds is in order to receive described clock signal, and the second leakage/source electrode of transistor seconds is then in order to export described second sweep signal.
In an one exemplary embodiment of the present invention, the pull-up unit of i level offset buffer more comprises electric capacity, and the one end couples the grid of transistor seconds, and its other end then is coupled to the second leakage/source electrode of transistor seconds.
In an one exemplary embodiment of the present invention, the control module of i level offset buffer comprises the 3rd transistor, the 4th transistor, the 5th transistor, and the 6th transistor.Wherein, the 3rd transistorized grid is coupled in its first leakage/source electrode, to receive described clock signal.The 4th transistorized grid draws signal in order to receive on described, and the 4th transistorized first leakage/source electrode couples the 3rd transistorized second leakage/source electrode, and the 4th transistorized second leakage/source electrode is then in order to receive described reference voltage.
The 5th transistorized grid couples the 3rd transistorized second leakage/source electrode, and the 5th transistorized first leakage/source electrode couples the 3rd transistorized first leakage/source electrode, and the 5th transistorized second leakage/source electrode is then in order to export described second control signal.The 6th transistorized grid draws signal in order to receive on described, and the 6th transistorized first leakage/source electrode couples the 5th transistorized second leakage/source electrode, and the 6th transistorized second leakage/source electrode is then in order to receive described reference voltage.
In an one exemplary embodiment of the present invention, the drop-down unit of i level offset buffer comprises the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor, and the 11 transistor.Wherein, the 7th transistorized grid is in order to receive described second control signal, and the 7th transistorized first leakage/source electrode couples the grid of transistor seconds, and the 7th transistorized second leakage/source electrode is then in order to receive described reference voltage.The 8th transistorized grid is in order to receive described second control signal, and the 8th transistorized first leakage/source electrode couples the second leakage/source electrode of transistor seconds, and the 8th transistorized second leakage/source electrode is then in order to receive described reference voltage.
The 9th transistorized grid is in order to receive described the 4th sweep signal, and the 9th transistorized first leakage/source electrode couples the grid of transistor seconds, and the 9th transistorized second leakage/source electrode is then in order to receive described reference voltage.The tenth transistorized grid is in order to receive described first control signal, and the tenth transistorized first leakage/source electrode couples the grid of transistor seconds, and the tenth transistorized second leakage/source electrode is then in order to receive described reference voltage.The 11 transistorized grid is in order to receive described first control signal, and the 11 transistorized first leakage/source electrode couples the second leakage/source electrode of transistor seconds, and the 11 transistorized second leakage/source electrode is then in order to receive described reference voltage.
In an one exemplary embodiment of the present invention, shifting cache apparatus proposed by the invention more comprises initial control module, couple the drop-down unit of the 1st grade of offset buffer, receive under the condition of n clock signal as if circulating with every n offset buffer, in order to the pull-up unit that receives an initial signal and n level offset buffer the clock signal of corresponding reception, and export an initial control signal according to this to the tenth and the 11 transistor in the drop-down unit of the 1st grade of offset buffer, wherein n is the positive integer more than or equal to 3.
In an one exemplary embodiment of the present invention, initial control module comprises the tenth two-transistor, the 13 transistor, the 14 transistor, and the 15 transistor.Wherein, the grid of the tenth two-transistor is coupled in its first leakage/source electrode, with the pull-up unit that receives n level offset buffer the clock signal that receives of correspondence.The 13 transistorized grid is in order to receive described start signal, and the 13 transistorized first leakage/source electrode couples the second leakage/source electrode of the tenth two-transistor, and the 13 transistorized second leakage/source electrode is then in order to receive described reference voltage.
The 14 transistorized grid couples the second leakage/source electrode of the tenth two-transistor, and the 14 transistorized first leakage/source electrode couples the first leakage/source electrode of the tenth two-transistor, and the 14 transistorized second leakage/source electrode is then in order to export described initial control signal.The 15 transistorized grid is in order to receive described start signal, and the 15 transistorized first leakage/source electrode couples the 14 transistorized second leakage/source electrode, and the 15 transistorized second leakage/source electrode is then in order to receive described reference voltage.
In an one exemplary embodiment of the present invention, above-mentioned the first to the 15 transistor is all the N transistor npn npn.
In an one exemplary embodiment of the present invention, shifting cache apparatus proposed by the invention is suitable for directly being configured on the glass substrate of a display panel, to drive the multi-strip scanning line in the described display panel.
In an one exemplary embodiment of the present invention, described display panel comprises display panels at least.
The drop-down unit of each grade offset buffer in the shifting cache apparatus provided by the present invention strengthens its ability drop-down and voltage stabilizing by the control that is subjected to the corresponding levels, previous stage and following two-stage shifting cache buffer.Thus, each grade circuit structure of shift buffer memory just can be under the condition that need not design a bigger building-out capacitor (that is not needing additionally to consume unnecessary layout area), the influence of the coupled noise that can suppress clock signal significantly and brought, thereby allow each grade offset buffer less building-out capacitor of can arranging in pairs or groups, use the fan-out capability that strengthens each grade offset buffer.
Description of drawings
Fig. 1 illustrates the block diagram into the shifting cache apparatus of the present invention's one one exemplary embodiment.
Fig. 2 illustrates the circuit diagram into the 2nd grade of offset buffer of the present invention's one one exemplary embodiment.
Fig. 3 illustrates the time sequences figure into the 2nd grade of offset buffer of the present invention's one one exemplary embodiment.
Fig. 4 illustrates the circuit diagram into the initial control module of the present invention's one one exemplary embodiment.
Drawing reference numeral:
100: shifting cache apparatus
SR1～SR4: offset buffer
ICU: initial control module
PU1～PU4: pull-up unit
CU1～CU4: control module
PD1～PD4: drop-down unit
N1～N15:N transistor npn npn
C: electric capacity
CLK1～CLK3: clock signal
STV: start signal
IP: initial control signal
P1～P4: control signal
PUS1～PUS4: on draw signal
G1～G4: sweep signal
VSS: reference voltage
T1～t7: time
Embodiment
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, at least one embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.
The invention provides a kind of shifting cache apparatus with the ability that suppresses coupled noise.Following content will encyclopaedize to those skilled in the relevant art of the present invention at technological means of the present invention and effect and consider and examine.In addition, all possibility parts use element/member of same numeral to represent identical or similar portions in graphic and embodiment.
Fig. 1 illustrates the block diagram into the shifting cache apparatus 100 of the present invention's one one exemplary embodiment.Please refer to Fig. 1, shifting cache apparatus 100 comprises the multistage offset buffer SR1～SRn that is serially connected each other (only show 4 grades of offset buffer SR1～SR4 among Fig. 1 and do explanation), and each offset buffer SR1～SR4 comprises pull-up unit, control module and drop-down unit respectively, that is: offset buffer SR1 comprises pull-up unit PU1, control module CU1 and drop-down unit PD1; Offset buffer SR2 comprises pull-up unit PU2, control module CU2 and drop-down unit PD2; Offset buffer SR3 comprises pull-up unit PU3, control module CU3 and drop-down unit PD3; And offset buffer SR4 comprises pull-up unit PU4, control module CU4 and drop-down unit PD4.
In this one exemplary embodiment, the pull-up unit of i level offset buffer can receive first sweep signal that a clock pulse signal and (i-1) level offset buffer is exported accordingly, and provide according to this draw signal and the decision whether export second sweep signal, wherein i is the positive integer more than or equal to 2.The control module of i level offset buffer can receive described clock signal and described on draw signal, and export second control signal according to this.
The drop-down unit of i level offset buffer can couple the pull-up unit of i level offset buffer and the control module of control module and (i-1) level offset buffer, in order to receiving and to be controlled by first control signal that the control module of described second control signal, (i-1) level offset buffer is exported, and the 4th sweep signal exported of (i+2) level offset buffer.Wherein, when i level offset buffer was not exported described second sweep signal, the drop-down unit of i level offset buffer can cause the stable output of i level offset buffer one reference voltage.
For instance, the pull-up unit PU2 of the 2nd grade of offset buffer SR2 can receive clock signal CLK2 and the 1st grade of sweep signal G1 that offset buffer SR1 is exported, and provides according to this and draw signal PUS2 and whether determine output scanning signal G2.The control module CU2 of the 2nd grade of offset buffer SR2 can receive clock signal CLK2 and on draw signal PUS2, and export control signal P2 according to this.
The drop-down unit PD2 of the 2nd grade of offset buffer SR2 can couple pull-up unit PU2 of self and the control module CU1 of control module CU2 and the 1st grade of offset buffer SR1, in order to receiving and to be controlled by the control signal P1 that the control module CU1 of control signal P2, the 1st grade of offset buffer SR1 is exported, and the 4th grade of sweep signal G4 that offset buffer SR4 is exported.Wherein, as the 2nd grade of offset buffer SR2 not during output scanning signal G2, the drop-down unit PD2 of the 2nd grade of offset buffer SR2 can cause the 2nd grade of offset buffer SR2 to stablize output reference voltage VSS.
In this and since this area have common knowledge technology personnel should be after reference Fig. 1 and the above-mentioned content that exemplifies, deductions/class is released the relation that couples between all the other offset buffers easily, so also no longer given unnecessary details it at this.Even, why can more understand as the 2nd grade of offset buffer SR2 not during output scanning signal G2 in order to allow this area have common knowledge technology personnel, the drop-down unit PD2 of the 2nd grade of offset buffer SR2 can cause the 2nd grade of offset buffer SR2 to stablize output reference voltage VSS.Following list is earlier done explanation with circuit structure and its operation principles of describing the 2nd grade of offset buffer SR2, and all the other circuit structure of shift buffer memory and its operation principles are all similar with the 2nd grade of offset buffer SR2.
Fig. 2 illustrates the circuit diagram into the 2nd grade of offset buffer SR2 of the present invention's one one exemplary embodiment.Please merge with reference to Fig. 1 and Fig. 2, based on above-mentioned one exemplary embodiment as can be known, offset buffer SR2 comprises pull-up unit PU2, control module CU2 and drop-down unit PD2.Wherein, pull-up unit PU2 comprises N transistor npn npn N1 and N2 and capacitor C (that is building-out capacitor).Wherein, the grid of N transistor npn npn N1 is coupled in its first leakage/source electrode, to receive the 1st grade of sweep signal G1 that offset buffer SR1 is exported.
The grid of N transistor npn npn N2 couples the first leakage/source electrode of the second leakage/source electrode, N transistor npn npn N2 of N transistor npn npn N1 in order to receive clock signal CLK2, and the second leakage/source electrode of N transistor npn npn N2 is then in order to output scanning signal G2.Wherein, the signal on the second leakage/source electrode of the grid of N transistor npn npn N2 and N transistor npn npn N1 is and draws signal PUS2.One end of capacitor C couples the grid of N transistor npn npn N2, and the other end of capacitor C then is coupled to the second leakage/source electrode of N transistor npn npn N2.
Control module CU2 comprises N transistor npn npn N3～N6.Wherein, the grid of N transistor npn npn N3 is coupled in its first leakage/source electrode, to receive clock signal CLK2.The grid of N transistor npn npn N4 couples the second leakage/source electrode of N transistor npn npn N3 in order to the first leakages/source electrode that draws signal PUS2, N transistor npn npn N4 on receiving, and the second leakage/source electrode of N transistor npn npn N4 is then in order to reception reference voltage VSS.
The grid of N transistor npn npn N5 couples the second leakage/source electrode of N transistor npn npn N3, the first leakage/source electrode of N transistor npn npn N5 couples the first leakage/source electrode of N transistor npn npn N3, and the second leakage/source electrode of N transistor npn npn N5 is then in order to output control signal P2.The grid of N transistor npn npn N6 couples the second leakage/source electrode of N transistor npn npn N5 in order to the first leakages/source electrode that draws signal PUS2, N transistor npn npn N6 on receiving, and the second leakage/source electrode of N transistor npn npn N6 is then in order to reception reference voltage VSS.
Drop-down unit PD2 comprises N transistor npn npn N7～N11.Wherein, the grid of N transistor npn npn N7 couples the grid of N transistor npn npn N2 in order to the first leakage/source electrode that receives control signal P2, N transistor npn npn N7, and the second leakage/source electrode of N transistor npn npn N7 is then in order to receive reference voltage VSS.The grid of N transistor npn npn N8 couples the second leakage/source electrode of N transistor npn npn N2 in order to the first leakage/source electrode that receives control signal P2, N transistor npn npn N8, and the second leakage/source electrode of N transistor npn npn N8 is then in order to receive reference voltage VSS.The grid of N transistor npn npn N9 couples the grid of N transistor npn npn N2 in order to the first leakage/source electrode that receives the 4th grade of the sweep signal G4 that offset buffer SR4 is exported, N transistor npn npn N9, and the second leakage/source electrode of N transistor npn npn N9 is then in order to receive reference voltage VSS.
The control signal P1 that the grid of N transistor npn npn N10 is exported in order to the control module CU1 that receives the 1st grade of offset buffer SR1, the first leakage/source electrode of N transistor npn npn N10 couple the grid of N transistor npn npn N2, and the second leakage/source electrode of N transistor npn npn N10 is then in order to receive reference voltage VSS.The control signal P1 that the grid of N transistor npn npn N11 is exported in order to the control module CU1 that receives the 1st grade of offset buffer SR1, the first leakage/source electrode of N transistor npn npn N11 couple the second leakage/source electrode of N transistor npn npn N2, and the second leakage/source electrode of N transistor npn npn N11 is then in order to receive reference voltage VSS.
Fig. 3 illustrates the time sequences figure into the 2nd grade of offset buffer SR2 of the present invention's one one exemplary embodiment.Please merge with reference to Fig. 1～Fig. 3, can know by the time sequences figure that Fig. 3 disclosed and to find out, when the grid of the N of pull-up unit PU2 transistor npn npn N1 and its first leakage/source electrode receive the 1st grade of sweep signal G1 that offset buffer SR1 is exported in time t1 the time, pull-up unit PU2 provided on draw the signal PUS2 can be by precharge, use the N transistor npn npn N4 and the N6 that open control module CU2.
Also also because of so, when clock pulse signal CLK2 when the time, t2 to t3 enabled, the second leakage/source electrode of the N transistor npn npn N2 of pull-up unit PU2 promptly can output scanning signal G2.And then, as the 4th grade of offset buffer SR4 during in time t4 output scanning signal G4, pull-up unit PU2 provided on draw signal PUS2 can be pulled down to reference voltage VSS, thereby close the N transistor npn npn N2 of pull-up unit PU2 and N transistor npn npn N4 and the N6 of control module CU2, use making the 2nd grade of offset buffer SR2 output reference voltage VSS.
On the other hand, because clock signal CLK1 can enable in time t4 to t6, so the control module CU1 of the 1st grade of offset buffer SR1 can provide control signal P1 to N transistor npn npn N10 among the drop-down unit PD2 and the grid of N11, thereby open N transistor npn npn N10 and N11 among the drop-down unit PD2.Afterwards, when clock pulse signal CLK2 when the time, t5 to t7 enabled, control module CU2 can provide control signal P2 to open N transistor npn npn N7 and the N8 of drop-down unit PD2.
Thus, the 2nd grade of offset buffer SR2 be not when answering output scanning signal G2, and the coupled noise of clock signal CLK2 (coupling noise) can be released into reference voltage VSS.In addition, after time t7, the coupled noise that is caused when clock signal CLK2 enables also can be released into reference voltage VSS.So, the coupled noise that clock signal CLK2 is caused can't have influence on the output logic state of sweep signal G2, using to cause does not need to design bigger capacitor C (that is not needing additionally to consume unnecessary layout area) to suppress coupled noise in the 2nd grade of offset buffer SR2, correct output scanning signal G2 yet.
At this, though above-mentioned one exemplary embodiment is only done explanation with circuit structure and its operation principles of describing the 2nd grade of offset buffer SR2, but all the other circuit structure of shift buffer memory and its operation principles are all similar with the 2nd grade of offset buffer SR2, so also no longer given unnecessary details it at this.
In addition, because the 1st grade of offset buffer SR1 do not have control signal that the upper level offset buffer provided N transistor npn npn N10 and the N11 to its drop-down unit PD1.Therefore, in this one exemplary embodiment, shifting cache apparatus 100 more can comprise an initial control module ICU, it can be coupled to the drop-down unit PD1 of the 1st grade of offset buffer SR1, the clock signal CLK3 that is received in order to the pull-up unit PU3 that receives start signal STV and 3rd level offset buffer SR3, and export initial control signal IP according to this to N transistor npn npn N10 and N11 among the drop-down unit PD1 of the 1st grade of offset buffer SR1.
Fig. 4 illustrates the circuit diagram into the initial control module ICU of the present invention's one one exemplary embodiment.Please merge with reference to Fig. 1～Fig. 4, in this one exemplary embodiment, initial control module comprises N transistor npn npn N12～N15.Wherein, the grid of N transistor npn npn N12 is coupled in its first leakage/source electrode, the clock signal CLK3 that is received with the pull-up unit PU3 that receives 3rd level offset buffer SR3.The grid of N transistor npn npn N13 couples the second leakage/source electrode of N transistor npn npn N12 in order to the first leakage/source electrode that receives start signal STV, N transistor npn npn N13, and the second leakage/source electrode of N transistor npn npn N13 is then in order to receive reference voltage VSS.
The grid of N transistor npn npn N14 couples the second leakage/source electrode of N transistor npn npn N12, the first leakage/source electrode of N transistor npn npn N14 couples the first leakage/source electrode of N transistor npn npn N12, and the second leakage/source electrode of N transistor npn npn N14 is then in order to output initial control signal IP.The grid of N transistor npn npn N15 couples the second leakage/source electrode of N transistor npn npn N14 in order to the first leakage/source electrode that receives start signal STV, N transistor npn npn N15, and the second leakage/source electrode of N transistor npn npn N15 is then in order to receive reference voltage VSS.In this one exemplary embodiment, the operation principles of the control module CU2 in initial control module ICU and the above-mentioned one exemplary embodiment is similar, so also no longer given unnecessary details it at this.
In addition, above-mentioned one exemplary embodiment is that example is done explanation with 3 clock signal CLK1～CLK3 all, but also can be clock signal more than 3, for example 4 clock signals in other one exemplary embodiment of the present invention.Clearer, should find out easily from the block diagram that Fig. 1 disclosed, per 3 offset buffers (for example SR1～SR3, SR4～SR6 ...) can circulation receive clock signal CLK1～CLK3, but in other one exemplary embodiment of the present invention, also can per 4 offset buffers (for example SR1～SR4, SR5～SR8 ...) circulating receives 4 clock signals, all are looked closely the actual design demand and decide it.
Moreover, it will be further appreciated that in this, receive under the condition of 4 clock signals as if circulating with per 4 offset buffers, then the grid of the N transistor npn npn N12 of initial control module ICU and its first leakage/source electrode just must transfer the 4th clock signal of reception to, but not the clock signal CLK3 that above-mentioned one exemplary embodiment is addressed.
In sum, the drop-down unit of each grade offset buffer in the shifting cache apparatus provided by the present invention strengthens its ability drop-down and voltage stabilizing by the control that is subjected to the corresponding levels, previous stage and following two-stage shifting cache buffer.Thus, each grade circuit structure of shift buffer memory just can be under the condition that need not design a bigger building-out capacitor (that is not needing additionally to consume unnecessary layout area), the influence of the coupled noise that can suppress clock signal significantly and brought, thereby allow each grade offset buffer less building-out capacitor of can arranging in pairs or groups, use the fan-out capability that strengthens each grade offset buffer.
In addition, because each grade offset buffer in the shifting cache apparatus provided by the present invention all possesses good inhibition coupled noise and high fan-out capability is arranged, therefore shifting cache apparatus proposed by the invention is well suited for directly being configured on the glass substrate of display panel (for example display panels), uses the multi-strip scanning line that drives in the display panel.Yet according to spirit of the present invention, so long as any electronic installation that need operate shifting cache mechanism is arranged, shifting cache apparatus provided by the present invention just is suitable for, so be not restriction to be applied in liquid crystal indicator.
In addition, under the condition that technological factor allows, each of above-mentioned one exemplary embodiment grade offset buffer more can be made up of the P transistor npn npn, and the one exemplary embodiment of these distortion also belongs to the category of institute of the present invention desire protection.Moreover; though the present invention discloses as above with a plurality of embodiment; right its is not in order to limit the present invention; any technician who has common knowledge in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim scope.
Claims (13)
1. a shifting cache apparatus is characterized in that, described shifting cache apparatus comprises:
The multistage offset buffer that is serially connected each other, each offset buffer comprise a pull-up unit, a control module and a drop-down unit respectively, wherein:
The pull-up unit of i level offset buffer can receive one first sweep signal that a clock pulse signal and i-1 level offset buffer are exported accordingly, and provides according to this and draw signal and decision whether to export one second sweep signal on one;
The control module of i level offset buffer can receive described clock signal and described on draw signal, and export one second control signal according to this; And
The drop-down unit of i level offset buffer can couple the pull-up unit of i level offset buffer and the control module of control module and i-1 level offset buffer, in order to receive and to be controlled by described second control signal, one first control signal that the control module of i-1 level offset buffer is exported, and one the 4th sweep signal exported of i+2 level offset buffer, wherein when i level offset buffer is not exported described second sweep signal, the drop-down unit of i level offset buffer can cause the stable output of i level offset buffer one reference voltage, and i is the positive integer more than or equal to 2.
2. shifting cache apparatus as claimed in claim 1 is characterized in that, the pull-up unit of i level offset buffer comprises:
One the first transistor, its grid is coupled in its first leakage/source electrode, to receive described first sweep signal; And
One transistor seconds, its grid couple the second leakage/source electrode of described the first transistor, and its first leakage/source electrode is in order to receive described clock signal, and its second leakage/source electrode is then in order to export described second sweep signal.
3. shifting cache apparatus as claimed in claim 2 is characterized in that, the pull-up unit of i level offset buffer more comprises:
One electric capacity, the one end couples the grid of described transistor seconds, and its other end then is coupled to the second leakage/source electrode of described transistor seconds.
4. shifting cache apparatus as claimed in claim 2 is characterized in that, described first with described transistor seconds be respectively a N transistor npn npn.
5. shifting cache apparatus as claimed in claim 2 is characterized in that, the control module of i level offset buffer comprises:
One the 3rd transistor, its grid is coupled in its first leakage/source electrode, to receive described clock signal;
One the 4th transistor, its grid draws signal in order to receive on described, and its first leakage/source electrode couples the described the 3rd transistorized second leakage/source electrode, and its second leakage/source electrode is then in order to receive described reference voltage;
One the 5th transistor, its grid couple the described the 3rd transistorized second leakage/source electrode, and its first leakage/source electrode couples the described the 3rd transistorized first leakage/source electrode, and its second leakage/source electrode is then in order to export described second control signal; And
One the 6th transistor, its grid draws signal in order to receive on described, and its first leakage/source electrode couples the described the 5th transistorized second leakage/source electrode, and its second leakage/source electrode is then in order to receive described reference voltage.
6. shifting cache apparatus as claimed in claim 5 is characterized in that, the described the 3rd is respectively a N transistor npn npn to described the 6th transistor.
7. shifting cache apparatus as claimed in claim 5 is characterized in that, the drop-down unit of i level offset buffer comprises:
One the 7th transistor, its grid is in order to receive described second control signal, and its first leakage/source electrode couples the grid of described transistor seconds, and its second leakage/source electrode is then in order to receive described reference voltage;
One the 8th transistor, its grid is in order to receive described second control signal, and its first leakage/source electrode couples the second leakage/source electrode of described transistor seconds, and its second leakage/source electrode is then in order to receive described reference voltage;
One the 9th transistor, its grid is in order to receive described the 4th sweep signal, and its first leakage/source electrode couples the grid of described transistor seconds, and its second leakage/source electrode is then in order to receive described reference voltage;
The tenth transistor, its grid is in order to receive described first control signal, and its first leakage/source electrode couples the grid of described transistor seconds, and its second leakage/source electrode is then in order to receive described reference voltage; And
The 11 transistor, its grid is in order to receive described first control signal, and its first leakage/source electrode couples the second leakage/source electrode of described transistor seconds, and its second leakage/source electrode is then in order to receive described reference voltage.
8. shifting cache apparatus as claimed in claim 7 is characterized in that, the described the 7th is respectively a N transistor npn npn to described the 11 transistor.
9. shifting cache apparatus as claimed in claim 7 is characterized in that, more comprises:
One initial control module, couple the drop-down unit of the 1st grade of offset buffer, receive under the condition of n clock signal as if circulating with every n offset buffer, in order to the pull-up unit that receives an initial signal and n level offset buffer the clock signal of corresponding reception, and export an initial control signal according to this to the tenth and the 11 transistor in the drop-down unit of the 1st grade of offset buffer, wherein n is the positive integer more than or equal to 3.
10. shifting cache apparatus as claimed in claim 9 is characterized in that, described initial control module comprises:
The tenth two-transistor, its grid is coupled in its first leakage/source electrode, with the pull-up unit that receives n level offset buffer the clock signal that receives of correspondence;
The 13 transistor, its grid is in order to receive described start signal, and its first leakage/source electrode couples the second leakage/source electrode of described the tenth two-transistor, and its second leakage/source electrode is then in order to receive described reference voltage;
The 14 transistor, its grid couple the second leakage/source electrode of described the tenth two-transistor, and its first leakage/source electrode couples the first leakage/source electrode of described the tenth two-transistor, and its second leakage/source electrode is then in order to export described initial control signal; And
The 15 transistor, its grid is in order to receive described start signal, and its first leakage/source electrode couples the described the 14 transistorized second leakage/source electrode, and its second leakage/source electrode is then in order to receive described reference voltage.
11. shifting cache apparatus as claimed in claim 10 is characterized in that, the described the 12 is respectively a N transistor npn npn to described the 15 transistor.
12. shifting cache apparatus as claimed in claim 10 is characterized in that, described shifting cache apparatus is suitable for directly being configured on the glass substrate of a display panel, to drive the multi-strip scanning line in the described display panel.
13. shifting cache apparatus as claimed in claim 12 is characterized in that, described display panel comprises a display panels at least.
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| CN2008101838152A CN101425340B (en) | 2008-12-09 | 2008-12-09 | Shifting cache apparatus |
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| CN101425340B true CN101425340B (en) | 2011-07-20 |
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| CN102237029B (en) * | 2010-04-23 | 2013-05-29 | 北京京东方光电科技有限公司 | Shift register and grid drive device and data line drive of liquid crystal display |
| TWI437824B (en) * | 2010-12-29 | 2014-05-11 | Au Optronics Corp | Shift register and driving method thereof |
| CN103137061B (en) * | 2013-02-18 | 2015-12-09 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN103400558B (en) * | 2013-07-31 | 2015-09-09 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit and display device |
| TWI529692B (en) * | 2014-07-10 | 2016-04-11 | 友達光電股份有限公司 | Driving circuit and display device |
| TWI524325B (en) * | 2014-09-10 | 2016-03-01 | 友達光電股份有限公司 | Shift register |
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