CN101727804B - Device and method for shifting and temporally storing - Google Patents
Device and method for shifting and temporally storing Download PDFInfo
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- CN101727804B CN101727804B CN200810201101XA CN200810201101A CN101727804B CN 101727804 B CN101727804 B CN 101727804B CN 200810201101X A CN200810201101X A CN 200810201101XA CN 200810201101 A CN200810201101 A CN 200810201101A CN 101727804 B CN101727804 B CN 101727804B
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Abstract
The invention relates to a device and a method for shifting and temporally storing. The device is mainly technically characterized by being provided with two NMOS transistors which are used for reducing the voltage level of a scanning signal outputted by a shift register in the device to the low-level grid voltage, wherein the conducting state of one of the NMOS transistors is controlled by a control unit and the conducting state of the other NMOS transistor is controlled by the frequency signal which is originally provided for the shift register or the frequency signal which is provided for the shift register after the phase of the shift register is reverted, therefore, the threshold voltage shift of the two NMOS transistors can be more moderate, and the two NMOS transistors can be more reliable. In addition, the shift register of the device needs to be internally provided with only one control unit, thus the overall layout area of the device can be reduced and the currently increasingly important narrower panel frame can be realized.
Description
Technical field
The invention relates to a kind of shift register device and method thereof; And particularly can promote the use reliability that the shift register interior liabilities draws the nmos pass transistor of reducing to the low level grid voltage with the voltage quasi position of its sweep signal of exporting, and can reach the shift register device and the method thereof of the narrow frame demand of the panel of being paid attention to day by day now again relevant for a kind of.
Background technology
In recent years, along with semiconductor science and technology is flourish, portable electronic product and flat-panel screens product also rise thereupon.And in the middle of the type of numerous flat-panel screens, (Liquid CrystalDisplay LCD) based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, has become the main flow of each display product to LCD immediately.Also, ordering about each tame manufacturer invariably and will hang down the cost of manufacture development towards more microminiaturized reaching to the development technique of LCD also because of so.
In order to reduce the cost of manufacture of LCD; Existing part manufacturer develops at display panels and adopts amorphous silicon (amorphous silicon; A-Si) under the condition of processing procedure, shift register (shift register) transfer that can the employed turntable driving IC of the scan-side that originally was disposed at display panels is inner directly is configured on the glass substrate (glass substrate) of display panels.Therefore, the employed turntable driving IC of scan-side that originally was disposed at display panels can omit, and uses the purpose that reaches the cost of manufacture that reduces LCD.
Fig. 1 illustrates the circuit block diagram that directly is configured in the shift register of being habitually practised on the glass substrate of display panels 100 for known.Fig. 2 illustrates the operation waveform diagram into the shift register 100 of Fig. 1.Please merge with reference to Fig. 1 and Fig. 2, at first, t between the first phase in during a picture (frame)
1When control module 101 receives time schedule controller (timing controller; Do not illustrate) the initial pulse STV that provided, when perhaps receiving the sweep signal G (n-1) that is exported from previous stage shift register (not illustrating), control module 101 can produce two control signal CS
1With CS
2, to cause nmos pass transistor T
AConducting, and nmos pass transistor T
BEnd, so capacitor C t between this first phase
1Can store a high levle grid voltage V earlier
GHElectric charge in wherein.
Then, the second phase t in during same picture
2, control module 101 still can produce two control signal CS
1With CS
2, to cause nmos pass transistor T
AConducting, and nmos pass transistor T
BEnd, but because capacitor C t between the first phase
1The time stored a high levle grid voltage V
GHElectric charge, so control module 101 is in second phase t
2The control signal CS that is produced
1Voltage quasi position can be promoted to the high levle grid voltage V of about twice
GH, so can be so that the voltage quasi position of the sweep signal Gn that shift register 100 is exported reaches high levle grid voltage V more easily
GH
And then, the second phase t in during same picture
2Afterwards, the control signal CS that produced of control module 101
1With CS
2Can stablely respectively be in low level grid voltage V
GLWith high levle grid voltage V
GHThe voltage quasi position state, and must wait until t between the first phase during the next picture
1With second phase t
2Shi Caihui makes change once more.Therefore, according to what the foregoing description content can be learnt be nmos pass transistor T
BT between the first phase in only can be during each picture
1With second phase t
2Shi Caihui ends, and all can conducting during all the other, and the voltage quasi position of using the sweep signal Gn that is responsible for shift register 100 is exported draws reduces to low level grid voltage V
GL
So under this situation, nmos pass transistor T
BProbably cause its quick aging under the conducting state for a long time, and causing its use reliability to descend.Moreover, more can cause nmos pass transistor T
BElectronics capture effect (charge trapping effect) phenomenon add evil, and make nmos pass transistor T
BLimit voltage (threshold voltage Vth) can be along with quicken increasing under the long conducting state.So, just, can make nmos pass transistor T
BThe voltage quasi position of the sweep signal Gn that is responsible for shift register 100 is exported draws reduces to low level grid voltage V
GLAbility go wrong.
Also also because of like this; The problem that very likely takes place is exactly the sweep signal G (n+1) that can make the pixel mistake that originally open corresponding to sweep signal Gn write the next stage shift register to be exported and the corresponding required data voltage of opening of pixel, and then the image frame that causes LCD to show takes place unusual.
And in order to improve above-mentioned mentioned problem; Just someone's voltage quasi position of proposing to be responsible for the sweep signal that shift register exports draws the nmos pass transistor of reducing to the low level grid voltage to set up several more; And the control module of arranging in pairs or groups separately; Use the voltage quasi position that causes the same time that the sweep signal that a nmos pass transistor is responsible for shift register is exported is only arranged and draw and reduce to the low level grid voltage, solve above-mentioned mentioned problem by this.
Fig. 3 illustrates the circuit block diagram for the shift register 300 that can solve shift register 100 shortcomings that Fig. 1 discloses, and it mainly is that the voltage quasi position of the sweep signal Gn that exported when shift register 300 must draw and reduces to low level grid voltage V
GLThe time, control module 301a and 301b can take the operating mode of dividing the work, and are used in the same time and only utilize nmos pass transistor T
2With T
6One of them, the voltage quasi position of the sweep signal Gn that is responsible for shift register 300 is exported draws reduces to low level grid voltage V
GL, so can solve the shortcoming that shift register 100 is derived.
Fig. 4 illustrates the nmos pass transistor T into the shift register 100 that is directed against Fig. 1
BNmos pass transistor T with the shift register 300 of Fig. 3
2, T
6Stress (stress) test pattern.Please with reference to Fig. 4, the transverse axis of the stress test figure that Fig. 4 disclosed represent the time (hour), and the longitudinal axis is represented nmos pass transistor T
B, T
2, T
6Limit voltage (Vth) drift value (voltage), wherein horizontal, the longitudinal axis all adopts log unit (log scale).In addition, increase in time and soaring solid line 401 is the nmos pass transistor T of shift register 100
BLimit voltage (Vth) drift value, and increase in time and soaring dotted line 402 is the nmos pass transistor T of shift register 300
2, T
6Limit voltage (Vth) drift value.
Can obviously find out the nmos pass transistor T of shift register 300 for the content of Fig. 4 explanation and the Fig. 4 that arranges in pairs or groups according to above-mentioned
2, T
6Limit voltage (Vth) drift value ease up in the nmos pass transistor T of shift register 100
BLimit voltage (Vth) drift value.Therefore, nmos pass transistor T
2, T
6Use reliability just can promote, so nmos pass transistor T
2, T
6The voltage quasi position of the sweep signal Gn that is responsible for shift register 300 is exported draws reduces to low level grid voltage V
GLAbility also can increase thereupon.
Though the shift register 300 that Fig. 3 disclosed can overcome the shortcoming that shift register 100 is derived, the voltage quasi position of the sweep signal Gn that is responsible for shift register 300 is exported draws reduces to low level grid voltage V
GLNmos pass transistor T
2, T
6, must arrange in pairs or groups separately a control module 301a and 301b, it is many so can to make just that layout (layout) area of shift register 300 increases, and the demand of the narrow frameization of panel that this phenomenon and being unfavorable for is paid attention to now day by day.
Summary of the invention
In view of this; In order to want to reach the purpose of the narrow frame demand of the panel of being paid attention to day by day now, and can take into account simultaneously again and promote the use reliability that the shift register interior liabilities draws the voltage quasi position of its sweep signal of exporting the nmos pass transistor of reducing to the low level grid voltage.Therefore; The present invention proposes the shift register device on a kind of glass substrate that directly is configured in display panels; It has most the shift registers that are serially connected each other; And each shift register comprises the first transistor, transistor seconds, the 3rd transistor, energy storage component, and control module.
In one embodiment of the invention, the first leakage/source electrode of the first transistor is in order to receiving the first frequency signal, and the grid of the first transistor is in order to receiving first control signal, and the second leakages/source electrode of the first transistor is in order to the generation sweep signal.First leakage/the source electrode of transistor seconds electrically connects the second leakage/source electrode of the first transistor; The grid of transistor seconds is in order to receive the second frequency signal; And the second leakage/source electrode of transistor seconds is in order to receive the first frequency signal, and wherein the phase differential of first frequency signal and second frequency signal is 180 to spend.
The 3rd transistorized first leakage/source electrode electrically connects the second leakages/source electrode of the first transistor, and the 3rd transistorized grid is in order to receiving second control signal, and the 3rd transistorized second leakage/source electrode is in order to reception low level grid voltage.Energy storage component is electrically connected between the grid and the second leakage/source electrode of the first transistor.Control module can be according to first frequency signal, second frequency signal, low level grid voltage and start signal, and produces first control signal and second control signal.
In one embodiment of the invention; Shift register proposed by the invention can utilize the first transistor that the voltage quasi position of said sweep signal is pulled up to the high levle grid voltage during a picture, and utilizes transistor seconds and the 3rd transistor timesharing that the voltage quasi position of said sweep signal is drawn and reduce to the low level grid voltage.
In one embodiment of the invention, control module comprises the 4th transistor, the 5th transistor, the 6th transistor, and the 7th transistor.Wherein, the 4th transistorized first leakage/source electrode is in order to receive start signal, and the 4th transistorized grid is in order to reception second frequency signal, and the 4th transistorized second leakage/source electrode electrically connects the grid of the first transistor, in order to produce first control signal.The 5th transistorized grid electrically connects the 4th transistorized second leakage/source electrode; The 5th transistorized first leakage/source electrode is in order to receive the low level grid voltage; And the 5th transistorized second leakage/source electrode electrically connects the 3rd transistorized grid, in order to produce second control signal.
The 6th transistorized grid electrically connects the 5th transistorized second leakage/source electrode, and the 6th transistorized first leakage/source electrode electrically connects the 4th transistorized second leakage/source electrode, and the 6th transistorized second leakage/source electrode is in order to receive the low level grid voltage.The 7th transistorized grid and the first leakage/source electrode are electrically connected to each other together, and in order to reception first frequency signal, and the 7th transistorized second leakage/source electrode electrically connects the 5th transistorized second leakage/source electrode.
In one embodiment of the invention, above-mentioned display panels adopts amorphous silicon processing procedure mode to be made.Therefore, above-mentioned the first transistor, above-mentioned transistor seconds, above-mentioned the 3rd transistor, above-mentioned the 4th transistor, above-mentioned the 5th transistor, above-mentioned the 6th transistor and above-mentioned the 7th transistor are nmos pass transistor.
From another viewpoint, the present invention provides a kind of display panels with shift register device that the invention described above proposes, and the LCD with this display panels.
From another viewpoint, the present invention proposes a kind of shift register method again, and it is applicable to like above-mentioned shift register device proposed by the invention.Shift register method proposed by the invention comprises the following steps: at first; Between the first phase in during said picture; When start signal and the activation simultaneously of second frequency signal; First control signal and second control signal that cause control module to produce are respectively activation and energy dissipating, use to utilize transistor seconds that the voltage quasi position of sweep signal is drawn to reduce to the low level grid voltage.Then; The second phase in during said picture; When start signal and the energy dissipating simultaneously of second frequency signal; First control signal and second control signal that cause control module to produce are respectively activation and energy dissipating, use and utilize the first transistor that the voltage quasi position of sweep signal is pulled up to the high levle grid voltage.
Afterwards; Between the third phase in during said picture; When start signal and second frequency signal are respectively energy dissipating and activation; Cause first control signal and the energy dissipating simultaneously of second control signal that control module produces, use and utilize transistor seconds that the voltage quasi position of sweep signal is drawn to reduce to the low level grid voltage.At last; Between the fourth phase in during said picture; When start signal and the energy dissipating simultaneously of second frequency signal; First control signal and second control signal that cause control module to produce are respectively energy dissipating and activation, use to utilize the 3rd transistor that the voltage quasi position of sweep signal is drawn to reduce to the low level grid voltage.
Shift register device proposed by the invention and method thereof; It mainly is that to draw the nmos pass transistor of reducing to the low level grid voltage to set up the voltage quasi position of being responsible for the sweep signal that shift register exports be two; One of them nmos pass transistor is to see through control module to control its conducting state, and another nmos pass transistor is to see through originally to provide to shift register required frequency signal or its anti-phase frequency signal later to control its conducting state.
Therefore, the voltage quasi position of being responsible for the sweep signal that shift register exports draws the limit voltage drift value of these two nmos pass transistors of reducing to the low level grid voltage more to ease up, and can promote its use reliability widely by this.In addition, because each shift register register inside only is provided with a control module,, can reach the demand of the narrow frameization of being paid attention to day by day now of panel by this so the whole layout area of shift register device proposed by the invention just can reduce.
Description of drawings
Fig. 1 illustrates the circuit block diagram that directly is configured in the shift register of being habitually practised on the glass substrate of display panels 100 for known;
Fig. 2 illustrates the operation waveform diagram into the shift register 100 of Fig. 1;
Fig. 3 illustrates the circuit block diagram for the shift register 300 that can solve shift register 100 shortcomings that Fig. 1 discloses;
Fig. 4 illustrates the nmos pass transistor T into the shift register 100 that is directed against Fig. 1
BNmos pass transistor T with the shift register 300 of Fig. 3
2, T
6Stress test figure;
Fig. 5 illustrates the circuit block diagram into the shift register device 500 of one embodiment of the invention;
Fig. 6 illustrates each the shift register SR into shift register device 500 inside
1～SR
3More detailed circuit diagram;
Fig. 7 illustrates the time sequential routine figure into the shift register device 500 of Fig. 5;
Fig. 8 illustrates and is the shift register SR to Fig. 6
1～SR
3Nmos pass transistor T
2', T
5' and T
8' be respectively receiving frequency signals CKB/CK and low level grid voltage V at its second leakage/source electrode
GLStress (stress) test pattern.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended graphicly, elaborates as follows.
Embodiment
The technological effect that the present invention desired to reach; Be mainly and promote the use reliability that the shift register interior liabilities draws the nmos pass transistor of reducing to the low level grid voltage with the voltage quasi position of its sweep signal of exporting, and more can reach the demand of the narrow frameization of being paid attention to day by day now of panel.And following content will encyclopaedize to the technical characterictic of this case, has common knowledge the knowledgeable and considers and examines to offer field of the present invention.
Fig. 5 illustrates the circuit block diagram into the shift register device 500 of one embodiment of the invention.Please with reference to Fig. 5; The shift register device 500 of present embodiment is for directly to be formulated on the glass substrate (glass substrate) of display panels (not illustrating); And have most the shift registers that conform to the interior number of scanning lines of display panels in it; In order to produce sweep signal in regular turn to corresponding scanning line, use and open or close the pixel that is coupled on the sweep trace.
In addition, above-mentioned display panels is to adopt amorphous silicon (a-Si) processing procedure mode to be made.And the spirit in order to explain conveniently that institute of the present invention desire is set forth supposes earlier that in this sweep trace in display panels always has 3, so 500 of the shift register devices of present embodiment have 3 shift register SR
1～SR
3, but the present invention is not restricted to this.
In present embodiment, shift register SR
1 Comprise control module 501a, transistor T
1'～T
3', and energy storage component C
1Wherein, control module 501a can be according to frequency signal CKB, frequency signal CK, low level grid voltage V
GLReach the initial pulse STV that time schedule controller (timing controller does not illustrate) is provided, and produce control signal CS
1With control signal CS
2, wherein the phase differential of frequency signal CKB and frequency signal CK is 180 degree, and also can be provided by time schedule controller.
In addition, transistor T
1' the first leakage/source electrode in order to receiving frequency signals CK, transistor T
1' grid in order to receive control signal CS
1, and transistor T
1' the second leakage/source electrode in order to produce sweep signal G
1Transistor T
2' the first leakage/source electrode electrically connect transistor T
1The second leakage/source electrode, transistor T
2' grid in order to receiving frequency signals CKB, and transistor T
2' the second leakage/source electrode in order to receiving frequency signals CK.Transistor T
3' the first leakage/source electrode electrically connect transistor T
1' the second leakage/source electrode, transistor T
3' grid in order to receive control signal CS
2, and transistor T
3' the second leakage/source electrode in order to receive low level grid voltage V
GLEnergy storage component C
1Be electrically connected at transistor T
1' grid and the second leakage/source electrode between, and can utilize capacitor (capacitor) to realize.
Moreover, shift register SR
1During a picture, can utilize transistor T
1' with sweep signal G that it produced
1Voltage quasi position be pulled up to high levle grid voltage (V
GH), and utilize transistor T
2' and transistor T
3' timesharing is sweep signal G that it produced
1Voltage quasi position draw and reduce to low level grid voltage (V
GL).
In present embodiment, shift register SR
2 Comprise control module 501b, transistor T
4'～T
6', and energy storage component C
2Wherein, control module 501b can be according to frequency signal CKB, frequency signal CK, low level grid voltage V
GLAnd shift register SR
1The sweep signal G that is exported
1, and produce control signal CS
3With control signal CS
4
In addition, transistor T
4' the first leakage/source electrode in order to receiving frequency signals CKB, transistor T
4' grid in order to receive control signal CS
3, and transistor T
4' the second leakage/source electrode in order to produce sweep signal G
2Transistor T
5' the first leakage/source electrode electrically connect transistor T
4' the second leakage/source electrode, transistor T
5' grid in order to receiving frequency signals CK, and transistor T
5' the second leakage/source electrode in order to receiving frequency signals CKB.Transistor T
6' the first leakage/source electrode electrically connect transistor T
4' the second leakage/source electrode, transistor T
6' grid in order to receive control signal CS
4, and transistor T
6' the second leakage/source electrode in order to receive low level grid voltage V
GLEnergy storage component C
2Be electrically connected at transistor T
4' grid and the second leakage/source electrode between, and can utilize capacitor to realize equally.
Moreover, shift register SR
2During a picture, can utilize transistor T
4' with sweep signal G that it produced
2Voltage quasi position be pulled up to high levle grid voltage (V
GH), and utilize transistor T
5' and transistor T
6' timesharing is sweep signal G that it produced
2Voltage quasi position draw and reduce to low level grid voltage (V
GL).
In present embodiment, shift register SR
3 Comprise control module 501c, transistor T
7'～T
9', and energy storage component C
3Wherein, control module 501c can be according to frequency signal CKB, frequency signal CK, low level grid voltage V
GLAnd shift register SR
2The sweep signal G that is exported
3, and produce control signal CS
5With control signal CS
6
In addition, transistor T
7' the first leakage/source electrode in order to receiving frequency signals CK, transistor T
7' grid in order to receive control signal CS
5, and transistor T
7' the second leakage/source electrode in order to produce sweep signal G
3Transistor T
8' the first leakage/source electrode electrically connect transistor T
7' the second leakage/source electrode, transistor T
8' grid in order to receiving frequency signals CKB, and transistor T
8' the second leakage/source electrode in order to receiving frequency signals CK.Transistor T
9' the first leakage/source electrode electrically connect transistor T
7' the second leakage/source electrode, transistor T
9' grid in order to receive control signal CS
6, and transistor T
9' the second leakage/source electrode in order to receive low level grid voltage V
GLEnergy storage component C
3Be electrically connected at transistor T
7' grid and the second leakage/source electrode between, and can utilize capacitor to realize equally.
Moreover, shift register SR
3During a picture, can utilize transistor T
7' with sweep signal G that it produced
3Voltage quasi position be pulled up to high levle grid voltage (V
GH), and utilize transistor T
8' and transistor T
9' timesharing is sweep signal G that it produced
3Voltage quasi position draw and reduce to low level grid voltage (V
GL).
Fig. 6 illustrates each the shift register SR into shift register device 500 inside
1～SR
3More detailed circuit diagram.Please merge with reference to Fig. 5 and Fig. 6, in present embodiment, control module 501a～501c is by transistor T
10"～T
13" constituted.Wherein, transistor T
10" the first leakage/source electrode in order to the reception initial pulse STV/ sweep signal G of correspondence
1/ sweep signal G
2, transistor T
10" grid in order to the receiving frequency signals CKB/CK of correspondence, and transistor T
10" the second leakage/source electrode can be corresponding be electrically connected to transistor T
1'/T
4'/T
7' grid, and in order to the generation control signal CS of correspondence
1/ CS
3/ CS
5
Transistor T
11" grid electrically connect transistor T
10" the second leakage/source electrode, transistor T
11" the first leakage/source electrode in order to receive low level grid voltage V
GL, and transistor T
11" the second leakage/source electrode can be corresponding be electrically connected to transistor T
3'/T
6'/T
9' grid, and in order to the generation control signal CS of correspondence
2/ CS
4/ CS
6Transistor T
12" grid electrically connect transistor T
11" the second leakage/source electrode, transistor T
12" the first leakage/source electrode electrically connect transistor T
10" this second leakage/source electrode, and transistor T
12" the second leakage/source electrode in order to receive low level grid voltage V
GLTransistor T
13" the grid and the first leakage/source electrode be electrically connected to each other together, in order to the receiving frequency signals CKB/CK of correspondence, and transistor T
13" the second leakage/source electrode electrically connect transistor T
11" the second leakage/source electrode.
And what deserves to be mentioned is earlier at this, because display panels adopts amorphous silicon (a-Si) processing procedure mode to be made, so above-mentioned transistor T
1'～T
9' and T
10"～T
13" be all nmos pass transistor.In addition; In order to want to explain clearly that the shift register device 500 of present embodiment can reach set technological effect; Below will arrange in pairs or groups time sequential routine of shift register device 500 schemes to do explanation further, uses letting the technician in field of the present invention know the spirit that institute of the present invention desire is set forth.
Fig. 7 illustrates the time sequential routine figure into the shift register device 500 of Fig. 5.Please merge with reference to Fig. 5～Fig. 7, at first what deserves to be mentioned is, the accurate position of the frequency signal CKB of present embodiment and the logic high voltage of frequency signal CK is set at can be with the high levle grid voltage V of pixel unlatching
GH, and the accurate position of the logic low-voltage of frequency signal CKB and frequency signal CK is set at the low level grid voltage V that can pixel be closed
GL
Therefore, (frame period) F during a picture
1T between the interior first phase
1' beginning, because shift register SR
1So initial pulse STV that is received and frequency signal CKB activation simultaneously is shift register SR
1The control signal CS that internal control unit 501a is produced
1With control signal CS
2Can be respectively activation and energy dissipating.By this, transistor T
2' can be responsible for sweep signal G
1Voltage quasi position draw and reduce to low level grid voltage V
GL, and make energy storage component C
1T between this first phase
1' can store a high levle grid voltage V earlier
GHElectric charge in wherein.
Then, F during same frame
1Interior second phase t
2', because shift register SR
1So initial pulse STV that is received and frequency signal CKB energy dissipating simultaneously is shift register SR
1The control signal CS that internal control unit 501a is produced
1With control signal CS
2Can be respectively activation and energy dissipating, but because energy storage component C
1T between the first phase
1' time stored a high levle grid voltage V
GHElectric charge in wherein, so control module 501a is in second phase t
2' the control signal CS that produced
1Voltage quasi position can be promoted to the high levle grid voltage V of about twice
GH, to provide to transistor T
1' grid.By this, transistor T
1' can be responsible for shift register SR
1The sweep signal G that is exported
1Voltage quasi position be pulled up to high levle grid voltage V
GH
Afterwards, F during same frame
1T between the interior third phase
3', because shift register SR
1The initial pulse STV and the frequency signal CKB that are received are respectively energy dissipating and activation, so shift register SR
1The control signal CS that internal control unit 501a is produced
1With control signal CS
2Energy dissipating simultaneously.By this, transistor T
2' can be responsible for sweep signal G
1Voltage quasi position draw and reduce to low level grid voltage V
GL
At last, F during same frame
1T between the interior fourth phase
4', because shift register SR
1So initial pulse STV that is received and frequency signal CKB energy dissipating simultaneously is shift register SR
1The control signal CS that internal control unit 501a is produced
1With control signal CS
2Can be respectively energy dissipating and activation.By this, transistor T
3' can be responsible for sweep signal G
1Voltage quasi position draw and reduce to low level grid voltage V
GL
So know F during a picture according to above-mentioned
1In, be responsible for shift register SR
1The sweep signal G that is exported
1Voltage quasi position draw and reduce to low level grid voltage V
GLAssembly can be dispensed to nmos pass transistor T
2' and T
3'.Therefore, along with shift register SR
1Running time remaining when increasing, nmos pass transistor T
2' and T
3' the limit voltage drift value will relatively ease up.
In addition, because nmos pass transistor T
2' the second leakage/source electrode be receiving frequency signals CK, so can cause nmos pass transistor T
2' electronics capture effect (charge trapping effect) phenomenon improve manyly, and make nmos pass transistor T
2' the limit voltage drift value more can be along with quicken increasing under the long conducting state, so nmos pass transistor T
2' use reliability just can promote widely.
The same time, F during same frame
1T between the interior first phase
1', because shift register SR
2The sweep signal G that is received
1With frequency signal CK energy dissipating simultaneously, so shift register SR
2The control signal CS that internal control unit 501b is produced
3With control signal CS
4Can be respectively energy dissipating and activation.By this, transistor T
6' can be responsible for sweep signal G
2Voltage quasi position draw and reduce to low level grid voltage V
GL
Then, F during same frame
1Interior second phase t
2', because shift register SR
2The sweep signal G that is received
1With frequency signal CK activation simultaneously, so shift register SR
2The control signal CS that internal control unit 501b is produced
3With control signal CS
4Can be respectively activation and energy dissipating.By this, transistor T
5' can be responsible for sweep signal G
2Voltage quasi position draw and reduce to low level grid voltage V
GL, and make energy storage component C
2In this second phase t
2' can store a high levle grid voltage V earlier
GHElectric charge in wherein.
Afterwards, F during same frame
1T between the interior third phase
3', because shift register SR
2The sweep signal G that is received
1During with frequency signal CK energy dissipating simultaneously, so shift register SR
2The control signal CS that internal control unit 501b is produced
3With control signal CS
4Can be respectively activation and energy dissipating, but because energy storage component C
2In second phase t
2' time stored a high levle grid voltage V
GHElectric charge in wherein, so control module 501b t between the third phase
3' the control signal CS that produced
3Voltage quasi position can be promoted to the high levle grid voltage V of about twice
GH, to provide to transistor T
4' grid.By this, transistor T
4' can be responsible for sweep signal G
2Voltage quasi position be pulled up to high levle grid voltage V
GH
At last, F during same frame
1T between the interior fourth phase
4', because shift register SR
2The sweep signal G that is received
1Be respectively energy dissipating and activation with frequency signal CK, so shift register SR
2The control signal CS that internal control unit 501b is produced
3With control signal CS
4Energy dissipating simultaneously.By this, transistor T
5' can be responsible for sweep signal G
2Voltage quasi position draw and reduce to low level grid voltage V
GL
So know F during a picture according to above-mentioned
1In, be responsible for shift register SR
2The sweep signal G that is exported
2Voltage quasi position draw and reduce to low level grid voltage V
GLAssembly can be dispensed to nmos pass transistor T
5' and T
6'.Therefore, along with shift register SR
2Running time remaining when increasing, nmos pass transistor T
5' and T
6' the limit voltage drift value will relatively ease up.
In addition, because nmos pass transistor T
5' the second leakage/source electrode be receiving frequency signals CKB, so can cause nmos pass transistor T
5' electronics capture effect (charge trapping effect) phenomenon improve manyly, and make nmos pass transistor T
5' the limit voltage drift value more can be along with quicken increasing under the long conducting state, so nmos pass transistor T
5' use reliability just can promote widely.
The same time, F during same frame
1T between the interior first phase
1', because shift register SR
3The sweep signal G that is received
2When being respectively energy dissipating and activation, so shift register SR with frequency signal CKB
3The control signal CS that internal control unit 501c is produced
5With control signal CS
6Energy dissipating simultaneously.By this, transistor T
8' can be responsible for sweep signal G
3Voltage quasi position draw and reduce to low level grid voltage V
GL
Then, F during same frame
1Interior second phase t
2', because shift register SR
3The sweep signal G that is received
2With frequency signal CKB energy dissipating simultaneously, so shift register SR
3The control signal CS that internal control unit 501c is produced
5With control signal CS
6Can be respectively energy dissipating and activation.By this, transistor T
9' can be responsible for sweep signal G
3Voltage quasi position draw and reduce to low level grid voltage V
GL
Afterwards, F during same frame
1T between the interior third phase
3', because shift register SR
3The sweep signal G that is received
2With frequency signal CKB activation simultaneously, so shift register SR
3The control signal CS that internal control unit 501c is produced
5With control signal CS
6Be respectively activation and energy dissipating.By this, transistor T
8' can be responsible for sweep signal G
3Voltage quasi position draw and reduce to low level grid voltage V
GL, and make energy storage component C
3T between this third phase
3' can store a high levle grid voltage V earlier
GHElectric charge in wherein.
At last, F during same frame
1T between the interior fourth phase
4', because shift register SR
3The sweep signal G that is received
2With frequency signal CKB energy dissipating simultaneously, so shift register SR
3The control signal CS that internal control unit 501c is produced
5With control signal CS
6Can be respectively activation and energy dissipating, but because energy storage component C
3T between the third phase
3' time stored a high levle grid voltage V
GHElectric charge in wherein, so control module 501c t between the fourth phase
4' the control signal CS that produced
5Voltage quasi position can be promoted to the high levle grid voltage V of about twice
GH, to provide to transistor T
7' grid.By this, transistor T
7' can be responsible for sweep signal G
3Voltage quasi position be pulled up to high levle grid voltage V
GH
So know F during a picture according to above-mentioned
1In, be responsible for shift register SR
3The sweep signal G that is exported
3Voltage quasi position draw and reduce to low level grid voltage V
GLAssembly can be dispensed to nmos pass transistor T
8' and T
9'.Therefore, along with shift register SR
3Running time remaining when increasing, nmos pass transistor T
8' and T
9' the limit voltage drift value will relatively ease up.
In addition, because nmos pass transistor T
8' the second leakage/source electrode be receiving frequency signals CK, so can cause nmos pass transistor T
8' electronics capture effect (charge trapping effect) phenomenon improve manyly, and make nmos pass transistor T
8' the limit voltage drift value more can be along with quicken increasing under the long conducting state, so nmos pass transistor T
8' use reliability just can promote widely.
In addition, because the transistor T in control module 501a～501c
13" be connected into the pattern that diode connects (Diode connected), so can be so that control signal CS
2, CS
4With CS
6Voltage quasi position can be lower than high levle grid voltage V
GHVoltage quasi position, so can cause nmos pass transistor T
3', T
6' and T
9' serviceable life prolong.
Moreover, it will be further appreciated that, do not limit nmos pass transistor T according to spirit of the present invention
2', T
5' and T
8' the second leakage/source electrode must receiving frequency signals CKB/CK.Clearer, the nmos pass transistor T of the foregoing description
2', T
5' and T
8' the second leakage/source electrode also can receive low level grid voltage V
GL, and can cause shift register device 500 can reach set technological effect equally.
Fig. 8 illustrates and is the shift register SR to Fig. 6
1～SR
4Nmos pass transistor T
2', T
5' and T
8' be respectively receiving frequency signals CKB/CK and low level grid voltage V at its second leakage/source electrode
GLStress (stress) test pattern.Please with reference to Fig. 8, the transverse axis of the stress test figure that Fig. 8 disclosed is represented the time (little, time), and the longitudinal axis is represented nmos pass transistor T
2', T
5' and T
8' limit voltage (Vth) drift value (voltage).Wherein, increase in time and soaring solid line 801 is nmos pass transistor T
2', T
5' and T
8' limit voltage (Vth) drift value that under the condition of receiving frequency signals CKB/CK, measured of the second leakage/source electrode, and increase in time and soaring dotted line 802 is nmos pass transistor T
2', T
5' and T
8' the second leakage/source electrode receiving low level grid voltage V
GLCondition under limit voltage (Vth) drift value that measured.
So can obviously find out nmos pass transistor T for the content of Fig. 8 explanation and the Fig. 8 that arranges in pairs or groups according to above-mentioned
2', T
5' and T
8' limit voltage (Vth) drift value that under the condition of receiving frequency signals CKB/CK, measured of the second leakage/source electrode be lower than nmos pass transistor T
2', T
5' and T
8' the second leakage/source electrode receiving low level grid voltage V
GLCondition under limit voltage (Vth) drift value that measured.
Therefore; Shift register proposed by the invention is if compare with the shift register that prior art is disclosed, and it is good and long that the use reliability of shift register proposed by the invention and serviceable life all can come than the shift register that prior art disclosed.Moreover, because shift register inside proposed by the invention only need dispose a control module,, can reach the demand of the narrow frameization of being paid attention to day by day now of panel by this so the whole layout area of shift register device proposed by the invention just can reduce.In view of the above, display panels and the LCD thereof as if the glass substrate that shift register device proposed by the invention directly is configured in display panels promptly belongs to the category that institute of the present invention desire is protected.
Except the shift register device of the foregoing description, the present invention also proposes a kind of shift register method in addition.The details of this shift register method has been contained among the embodiment of above-mentioned shift register device all; Therefore; In correlative technology field of the present invention, having common knowledge the knowledgeable has seen after the explanation of front; Should implement this shift register method easily, so the details of this shift register driving method is not just given unnecessary details at this.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (7)
1. a shift register device is disposed on the glass substrate of a display panels, it is characterized in that this shift register device comprises:
A most shift register be serially connected each other, and each shift register comprise:
One the first transistor, the first leakage/source electrode of this first transistor be in order to receiving a first frequency signal, and the grid of this first transistor is in order to receiving one first control signal, and the second leakage/source electrode of this first transistor is in order to produce the one scan signal;
One transistor seconds; First leakage/the source electrode of this transistor seconds electrically connects the second leakage/source electrode of this first transistor; The grid of this transistor seconds is in order to receive a second frequency signal; And the second leakage/source electrode of this transistor seconds is in order to receive this first frequency signal, and wherein the phase differential of this first frequency signal and this second frequency signal is 180 degree;
One the 3rd transistor; The 3rd transistorized first leakage/source electrode electrically connects the second leakage/source electrode of this first transistor; The 3rd transistorized grid is in order to receiving one second control signal, and the 3rd transistorized second leakage/source electrode is in order to receive a low level grid voltage;
One energy storage component, it is electrically connected between the grid and the second leakage/source electrode of this first transistor;
One control module in order to according to this first frequency signal, this second frequency signal, this low level grid voltage and an initial signal, and produces this first control signal and this second control signal; This control module further comprises:
One the 4th transistor; The 4th transistorized first leakage/source electrode is in order to receive this start signal; The 4th transistorized grid is in order to receiving this second frequency signal, and the 4th transistorized second leakage/source electrode electrically connects the grid of this first transistor, in order to produce this first control signal;
One the 5th transistor; The 5th transistorized grid electrically connects the 4th transistorized second leakage/source electrode; The 5th transistorized first leakage/source electrode is in order to receive this low level grid voltage; And the 5th transistorized second leakage/source electrode electrically connects the 3rd transistorized grid, in order to produce this second control signal;
One the 6th transistor; The 6th transistorized grid electrically connects the 5th transistorized second leakage/source electrode; The 6th transistorized first leakage/source electrode electrically connects the 4th transistorized second leakage/source electrode, and the 6th transistorized second leakage/source electrode is in order to receive this low level grid voltage; And
One the 7th transistor, the 7th transistorized grid and the first leakage/source electrode are electrically connected to each other together, and in order to receiving this first frequency signal, and the 7th transistorized second leakage/source electrode electrically connects the 5th transistorized second leakage/source electrode;
Wherein, This shift register utilizes this first transistor that the voltage quasi position of this sweep signal is pulled up to a high levle grid voltage during a picture, and utilizes this transistor seconds and the 3rd transistor timesharing that the voltage quasi position of this sweep signal is drawn and reduce to this low level grid voltage.
2. shift register device as claimed in claim 1 is characterized in that, this display panels adopts amorphous silicon processing procedure mode to be made.
3. shift register device as claimed in claim 2 is characterized in that, this first transistor, this transistor seconds, the 3rd transistor, the 4th transistor, the 5th transistor, the 6th transistor and the 7th transistor are nmos pass transistor.
4. shift register device as claimed in claim 1 is characterized in that this energy storage component comprises a capacitor.
5. display panels with shift register device as claimed in claim 1.
6. LCD with display panels as claimed in claim 5.
7. shift register method, it is applicable to shift register device as claimed in claim 1, it is characterized in that, this shift register method comprises the following steps:
Between the first phase in during this picture; When this start signal and the activation simultaneously of this second frequency signal; This first control signal and this second control signal that cause this control module to produce are respectively activation and energy dissipating, use to utilize this transistor seconds that the voltage quasi position of this sweep signal is drawn to reduce to this low level grid voltage;
Second phase in during this picture; When this start signal and the energy dissipating simultaneously of this second frequency signal; This first control signal and this second control signal that cause this control module to produce are respectively activation and energy dissipating, use and utilize this first transistor that the voltage quasi position of this sweep signal is pulled up to a high levle grid voltage;
Between the third phase in during this picture; When this start signal and this second frequency signal are respectively energy dissipating and activation; Cause this first control signal and the energy dissipating simultaneously of this second control signal that this control module produces, use and utilize this transistor seconds that the voltage quasi position of this sweep signal is drawn to reduce to this low level grid voltage; And
Between the fourth phase in during this picture; When this start signal and the energy dissipating simultaneously of this second frequency signal; This first control signal and this second control signal that cause this control module to produce are respectively energy dissipating and activation, use to utilize the 3rd transistor that the voltage quasi position of this sweep signal is drawn to reduce to this low level grid voltage.
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| CN103021358B (en) * | 2012-12-07 | 2015-02-11 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving circuit and display device |
| CN104157232B (en) * | 2014-08-01 | 2016-08-17 | 合肥京东方光电科技有限公司 | Gating drive circuit, gating driving method, array base palte and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690347B2 (en) * | 2001-02-13 | 2004-02-10 | Samsung Electronics Co., Ltd. | Shift register and liquid crystal display using the same |
| CN1794332A (en) * | 2004-12-22 | 2006-06-28 | 阿尔卑斯电气株式会社 | Driver circuit, shift register, and liquid crystal driver circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690347B2 (en) * | 2001-02-13 | 2004-02-10 | Samsung Electronics Co., Ltd. | Shift register and liquid crystal display using the same |
| CN1794332A (en) * | 2004-12-22 | 2006-06-28 | 阿尔卑斯电气株式会社 | Driver circuit, shift register, and liquid crystal driver circuit |
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Effective date of registration: 20230511 Address after: No. two, No. 1188 West Ring Road, Shengze Town, Wujiang District, Jiangsu, Suzhou Patentee after: Suzhou Shengze science and Technology Pioneer Park Development Co.,Ltd. Address before: 215217, 88 East Road, Tongli District, Wujiang Economic Development Zone, Jiangsu, China Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |