CN103117260A - Welding spot structure - Google Patents

Welding spot structure Download PDF

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Publication number
CN103117260A
CN103117260A CN2011103621734A CN201110362173A CN103117260A CN 103117260 A CN103117260 A CN 103117260A CN 2011103621734 A CN2011103621734 A CN 2011103621734A CN 201110362173 A CN201110362173 A CN 201110362173A CN 103117260 A CN103117260 A CN 103117260A
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CN
China
Prior art keywords
type
pad
solder
array
substrate
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CN2011103621734A
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Chinese (zh)
Inventor
洪荣华
王珺
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复旦大学
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Priority to CN2011103621734A priority Critical patent/CN103117260A/en
Publication of CN103117260A publication Critical patent/CN103117260A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

The invention discloses a welding spot structure which comprises a first-class welding spot array and a plurality of second-class welding spots, wherein the second-class welding spots are distributed on the outer circle of the first-class welding spot array, the first-class welding spot array enables a semiconductor chip to be in electrical and mechanical connection with a substrate, and the second-class welding spots enable the semiconductor chip to be in mechanical connection with the substrate. As the plurality of second-class welding spots are installed on the outer circle of the first-class welding spot array, rigidity of the whole welding spot structure is increased, stress and strain on key welding spots are decreased, time of crack generation is delayed, reliability of the key welding spots is improved, and therefore service life of a whole packaging device is prolonged.

Description

一种焊点结构 One kind of solder joint

技术领域 FIELD

[0001] 本发明涉及半导体封装技术领域,尤其涉及一种增强可靠性的焊点结构。 [0001] The present invention relates to semiconductor packaging technology, and particularly relates to enhancement in reliability of the solder joint.

背景技术 Background technique

[0002] 随着电子信息产业的日新月异,组装密度越来越高,诞生了新型SMT、MCM技术,微电子器件中的焊点也越来越小,对可靠性要求日益提高。 [0002] With the ever-changing electronic information industry, more and more high packing density, the birth of a new SMT, MCM technology, microelectronic devices are getting smaller and smaller joints, increasing reliability requirements. 电子封装中广泛采用的SMT封装技术及芯片尺寸封装(CSP)、焊球阵列(BGA)等封装技术均通过焊点直接实现器件与基板之间的电及机械连接(主要承受剪切应变),焊点的质量与可靠性决定了电子产品的质量。 The electronic package SMT is widely used in packaging technology and a chip size package (the CSP), ball grid array (BGA) packages such techniques are direct electrical and mechanical connection between the device and the substrate (mainly subjected to shear strain) by solder, the quality and reliability of solder joints determines the quality of electronic products.

[0003] 封装器件在实际使用中,通电与否和周围温度的变化使其经历了温度循环的过程。 [0003] In actual use, the packaged device, and the energization or not ambient temperature changes it undergoes a temperature cycle process. 在温度循环过程中焊点可能会发生疲劳失效。 In the temperature cycling solder fatigue may occur failure. 焊点的失效电连接短路或电阻过大,导致器件不能实现预定功能,无法使用。 Solder electrically connecting the short-circuit failure or the resistance is too large, resulting in the device can not realize the predetermined function can not be used. 因此如何保证焊点的质量是一个重要问题。 Therefore, how to ensure the quality of solder joints is an important issue.

[0004] 关于现有的芯片封装结构请参考图1及图2,其中,图1为现有的芯片封装结构的侧面示意图,图2为现有的芯片封装结构的正面示意图,如图1及图2所示,现有的芯片封装结构包括基板100、焊点阵列110(图中仅示意了4X4焊点阵列)以及半导体芯片120,所述焊点阵列110将所述基板100及所述半导体芯片120进行电性连接及机械连接。 [0004] For the conventional chip packaging structure Referring to FIG. 1 and 2, wherein FIG. 1 is a side configuration of a conventional chip package schematic, FIG. 2 is a schematic front structure of a conventional chip package of FIG. 1, and As shown in FIG., a conventional chip package structure 100 includes two, pad array 110 (only illustrates a 4X4 Grid array) 120 and the semiconductor chip, the pad array 110 to the substrate 100 and the semiconductor substrate chip 120 is electrically and mechanically connected. 并且,所述焊点阵列110中的每个焊点都起到电性连接及机械连接的作用。 And wherein each of the solder pad array 110 are electrically connected and acts as the mechanical connection. 其中,位于芯片封装结构中心点几何距离最远处的焊点(即边角位置的焊点)称为关键焊点111,由于这些关键焊点111上的应力相比其它内部焊点上的应力更大、非弹性应变能密度更高,因而容易产生疲劳裂纹并拓展,最终导致器件失效。 Wherein the geometric center point of the chip package farthest from the pads (i.e., pads corner position) known as a key pad 111, the other internal stress due to the stress on solder joints 111 as compared to these key larger, higher density non-elastic strain energy, and thus prone to fatigue cracks develop, eventually leading to failure of the device.

[0005] 因此,为了提高器件的可靠性,应该重点关注边角位置的关键焊点,尽量减小其热应力和应变能密度的大小。 [0005] Accordingly, in order to improve the reliability of the device, the corner joints should focus on key position, which minimize thermal stress and strain energy density size. 除了边角位置的关键焊点,焊点阵列中的其它外圈焊点上的应力也较大,也应引起关注。 In addition to the stress on the other outer pad key pad, the position of the corner joints in the array is large, it is also of concern.

[0006] 为了提高焊点的可靠性,在现有的研究中,有学者提出用改变焊点几何尺寸(包括焊点的高度、直径和形状)与焊料种类的方法提高焊点的可靠性。 [0006] In order to improve the reliability of the solder joint in the conventional studies, has been suggested that by varying the geometry of the pad (including the height, diameter and shape of the solder) and solder type method for improving solder joint reliability. 此种方法虽然可行,但削弱了工艺的兼容性,增加了成本。 Although this method is feasible, but weakened the compatibility process, increasing the cost. 此外,这种方法的适用性有限,且必须先研究封装结构的可靠性和焊点几何尺寸、焊料种类的关系,过程繁琐并增加了成本。 Furthermore, the applicability of this method is limited, and must Relationship and reliability of the solder joint geometry of the package, solder type, complicated process and increases the cost. 另外,增加底部填充料也是增加焊点可靠性的一种方法。 Further, increasing the underfill is a method of increasing the reliability of the solder joint. 本专利的方法可以同时采用底部填充料方法,获得更高的焊点可靠性。 The method of this patent may be employed at the same time the bottom of the filler methods to achieve higher reliability of solder joints.

[0007] 因此,如何有效地提高芯片封装结构中的焊点的可靠性成为目前业界亟需解决的关键技术问题。 [0007] Therefore, how to effectively improve the chip packaging structure of the solder joint reliability of the key technologies needed to solve the industry's problems.

发明内容 SUMMARY

[0008] 本发明的目的在于提供一种焊点结构,以提高芯片封装结构中的焊点的可靠性。 [0008] The object of the present invention to provide a solder joint, to improve reliability of the chip package structure of the solder joint.

[0009] 为解决上述问题,本发明提出一种焊点结构,位于一基板上,用于将半导体芯片连接至所述基板上,其中,所述焊点结构包括: [0009] In order to solve the above problems, the present invention provides a solder joint, is located on a substrate, for connecting the semiconductor chip onto the substrate, wherein the solder joint comprises:

[0010] 第一类焊点阵列,将所述半导体芯片与所述基板进行电性连接及机械连接;[0011] 多个第二类焊点,分布于所述第一类焊点阵列的外圈,将所述半导体芯片与所述基板进行机械连接。 [0010] The first pad array, the semiconductor chip and the substrate electrical and mechanical connection; [0011] a plurality of second type pads distributed in the first type of outer pad array ring, the semiconductor chip is connected mechanically to the substrate.

[0012] 可选的,所述第一类焊点阵列包括多个关键焊点,所述关键焊点的位置距离所述焊点阵列的中心的距离最远;其中,所述第二类焊点分布于所述关键焊点的外圈。 [0012] Optionally, the first type of pad array including a plurality of key pads, key pads of the farthest distance from the center of the pad array; wherein said second type of welding points distributed in the outer ring of the key pad.

[0013] 可选的,所述每个关键焊点的外圈分布有一个或多个所述第二类焊点。 [0013] Optionally, each of the outer profile of the key pads of one or more of said second type of pad.

[0014] 可选的,所述第二类焊点的几何尺寸与所述第一类焊点阵列中的焊点的几何尺寸相同。 [0014] Alternatively, the second type of solder joint geometry with the first type of solder pad array of the same geometry.

[0015] 可选的,所述第二类焊点的焊料与所述第一类焊点阵列中的焊点的焊料相同。 [0015] Alternatively, the second type of solder pads and solder pads in the array of the first type the same solder.

[0016] 可选的,所述第二类焊点之间的最短距离与所述第一类焊点阵列中的焊点之间的 [0016] Alternatively, the shortest distance between the second type between the first pad type solder pad array with

最短距离相等。 Equal to the shortest distance.

[0017] 可选的,所述第二类焊点的制备工艺与所述第一类焊点阵列中的焊点的制备工艺相同,且同时完成。 [0017] Alternatively, the second type and the preparation process of the first type of weld preparation solder joints of the same array, and completed simultaneously.

[0018] 与现有技术相比,本发明提供的焊点结构包括第一类焊点阵列及多个第二类焊点,所述第二类焊点分布于所述第一类焊点阵列的外圈,所述第一类焊点阵列将所述半导体芯片与所述基板进行电性连接及机械连接,所述第二类焊点将所述半导体芯片与所述基板进行机械连接,通过在所述第一类焊点阵列的外圈设置多个第二类焊点,缓解了所述第一类焊点阵列中的关键焊点的应力和应变,使所述关键焊点上的应力和应变减小,增加结构刚度,延后了裂纹产生的时间,提高了关键焊点的可靠性,从而使整个封装器件的寿命也得到提闻。 [0018] Compared with the prior art, the present invention provides a solder joint comprising a plurality of a first type and a second array of solder pads category, the second category to the first category profile pad pad array an outer ring, the first type of pad array of the semiconductor chip and the substrate are electrically and mechanically connected to the second type of mechanical connection pads of the semiconductor chip and the substrate, by a plurality of pads disposed in a second type of outer pad array of the first type, the key pad to alleviate the first pad array type stress and strain, the stress on the key pad and strain decreases, increasing structural rigidity, the delay time of cracks, improve the reliability of the key pad, so that the life of the packaged device also mention smell.

附图说明 BRIEF DESCRIPTION

[0019] 图1为现有的芯片封装结构的侧面示意图; [0019] FIG. 1 is a side configuration of a conventional chip package schematic;

[0020] 图2为现有的芯片封装结构的正面不意图; [0020] FIG 2 is not intended to be the front of a conventional chip packaging structure;

[0021] 图3为本发明第一个实施例提供的焊点结构的侧面示意图; [0021] FIG. 3 is a schematic side joint structure according to another embodiment of the present invention, first;

[0022] 图4为本发明第一个实施例提供的焊点结构的正面示意图; [0022] FIG. 4 is a schematic front structure of a pad provided in a first embodiment of the present invention;

[0023] 图5为本发明第二个实施例提供的焊点结构的正面示意图; [0023] FIG 5 second positive solder joint according to an embodiment of the present invention, a schematic diagram;

[0024] 图6为本发明第三个实施例提供的焊点结构的正面示意图。 [0024] FIG third positive solder joint according to an embodiment of the schematic diagram of the present invention.

具体实施方式 Detailed ways

[0025] 以下结合附图和具体实施例对本发明提出的焊点结构作进一步详细说明。 [0025] The following specific examples in conjunction with the accompanying drawings and described in further detail of the solder joint proposed by the invention. 根据下面说明和权利要求书,本发明的优点和特征将更清楚。 The following description and the appended claims, features and advantages of the present invention will be apparent. 需说明的是,附图均采用非常简化的形式且均使用非精准的比率,仅用于方便、明晰地辅助说明本发明实施例的目的。 It should be noted that the drawings are used in a very simplified form and are using a non-precise ratio, for convenience only, assist clarity purpose of illustrating an embodiment of the present invention.

[0026] 本发明的核心思想在于,提供一种焊点结构,包括第一类焊点阵列及多个第二类焊点,所述第二类焊点分布于所述第一类焊点阵列的外圈,所述第一类焊点阵列将所述半导体芯片与所述基板进行电性连接及机械连接,所述第二类焊点将所述半导体芯片与所述基板进行机械连接,通过在所述第一类焊点阵列的外圈设置多个第二类焊点,从而分担了所述第一类焊点阵列中的关键焊点的应力和应变,使所述关键焊点上的应力和应变减小,延后了裂纹产生的时间,提高了关键焊点的可靠性,从而使整个封装器件的寿命也得到提闻。 [0026] The core idea of ​​the invention is to provide a solder joint, comprising a plurality of a first type and a second type of pad array pads of the second type to the first type of solder pads distributed array an outer ring, the first type of pad array of the semiconductor chip and the substrate are electrically and mechanically connected to the second type of mechanical connection pads of the semiconductor chip and the substrate, by an outer ring disposed in the first type of the plurality of second pad array type pads, thereby sharing the key pad of the pad array of the first type of stress and strain, so that the key pad of reduced stress and strain, cracks delay time, improving the reliability of the key pad, so that the life of the packaged device also mention smell. [0027] 实施例1 [0027] Example 1

[0028] 请参考图3及图4,其中,图3为本发明第一个实施例提供的焊点结构的侧面示意图,图4为本发明第一个实施例提供的焊点结构的正面示意图,如图3及图4所示,本发明第一个实施例提供的焊点结构,位于一基板200上,用于将半导体芯片210连接至所述基板200上,其中,所述焊点结构包括: [0028] Please refer to FIG. 3 and FIG. 4, wherein FIG. 3 is a first side joint structure according to another embodiment of FIG. 4 is a schematic of a positive solder joint according to an embodiment of the invention, a schematic invention, , as shown in FIG. 3 and FIG. 4, a solder joint according to an embodiment of the present invention positioned on a substrate 200, 210 for connection to the semiconductor chip 200 on the substrate, wherein the solder joint include:

[0029] 第一类焊点阵列220,将所述半导体芯片210与所述基板200进行电性连接及机械连接;其中,所述第一类焊点阵列220包括多个关键焊点221,所述关键焊点221的位置距离所述焊点阵列的中心的距离最远; [0029] The first pad array 220, the semiconductor chip 210 and the substrate 200 for electrical and mechanical connection; wherein the first type of pad array 220 comprises a plurality of key pads 221, the said key pad 221 furthest distance from the position of the center of the pad array;

[0030] 多个第二类焊点230,分布于所述第一类焊点阵列220的外圈,将所述半导体芯片210与所述基板200进行机械连接。 [0030] The second type of the plurality of pads 230 distributed in the first type of outer pad array 220, the semiconductor chip 210 and the substrate 200 is mechanically connected. 具体地,所述每个关键焊点221的外圈分布一个第二类焊点230。 In particular, each of the key pad 221 of the outer ring of a second type of pad 230 distributed. 需说明的是,所述第二类焊点230仅将所述半导体芯片210与所述基板200进行机械连接,并不进行电性连接,因此所述第二类焊点230的存在和损坏并不会对器件的正常工作造成影响。 It should be noted that only the second type of pad 230 and the semiconductor chip 210 is mechanically connected to the substrate 200 is not electrically connected, and therefore the presence of the second type and the pads 230 and damage It will not affect the normal operation of the device.

[0031] 通过在所述关键焊点221的外圈设置一个第二类焊点230,从而分担了所述第一类焊点阵列220中的关键焊点221的应力和应变,使所述关键焊点221上的应力和应变减小,延后了裂纹产生的时间,提高了关键焊点221的可靠性,从而使整个封装器件的寿命也得到提闻。 [0031] In the key pad by the outer ring 221 is provided a second type of pad 230, thereby sharing the key pad in the pad array 220 of the first type of stress and strain 221, the key stress and strain on the pad 221 is reduced, the delay time of cracks, improving the reliability of the key pad 221, so that the life of the packaged device also mention smell.

[0032] 进一步地,所述第二类焊点230的几何尺寸与所述第一类焊点阵列220中的焊点的几何尺寸相同;所述第二类焊点230的焊料与所述第一类焊点阵列220中的焊点的焊料相同;所述第二类焊点230之间的最短距离与所述第一类焊点阵列220中的焊点之间的最短距离也相等;从而使得所述第二类焊点230的制备工艺与所述焊点阵列220中的焊点的制备工艺兼容。 [0032] Further, the second type of the same geometric dimensions of the solder pads 230 and the first pad array 220 type geometry; the second type with the first solder pad 230 a class of the same pad array 220 of solder joints; shortest distance between said second type of pad 230 and the shortest distance between the solder pad array 220 of the first type are equal; whereby such that the second type of process for manufacturing pads prepared with the pad array 220 of pads 230 compatible.

[0033] 进一步地,所述第二类焊点230的制备工艺与所述第一类焊点阵列220中的焊点的制备工艺相同,且同时完成。 [0033] Further, the second type of pad 230 Preparation of solder joints and production process of the first array 220 in the same class, and completed simultaneously.

[0034] 实施例2 [0034] Example 2

[0035] 请参考图5,图5为本发明第二个实施例提供的焊点结构的正面示意图,如图5所示,实施例2与实施例1的不同之处在于,所述第一类焊点阵列220中的每个关键焊点221的外围分布有多个第二类焊点230 (图中仅示意3个)。 [0035] Please refer to FIG. 5, FIG. 5 is a schematic front view of the solder joint of the second embodiment of the invention provides, as shown in FIG. 5, the embodiment 2 differs from the embodiment 1, the first class pad array 220 of each of the key pad 221 of the periphery of the second type are distributed a plurality of pads 230 (only schematically in FIG. 3). 通过在每个关键焊点221的外围分布有多个第二类焊点230,从而更好地缓解了所述第一类焊点阵列220中的关键焊点221的应力和应变。 By the periphery of each key pads 221 are distributed a plurality of second type of pad 230, in order to better mitigate the key pad of the pad array 220 of the first type of stress and strain 221. 并且,所述第二类焊点230之间的最短距离d2与所述第一类焊点阵列220中的焊点之间的最短距离Cl1相等。 And equal to the shortest distance between Cl1 shortest distance d2 between the pad 230 and the second type of solder pad array 220 of the first type.

[0036] 除此之外,实施例2与实施例1均相同,因此不再赘述。 [0036] In addition, Example 2 and Example 1 are the same, thus omitted.

[0037] 实施例3 [0037] Example 3

[0038] 请参考图6,图6为本发明第三个实施例提供的焊点结构的正面示意图,如图6所示,实施例3与实施例1的不同之处在于,所述第二类焊点230分布在所述第一类焊点阵列220的外圈,即所述第一类焊点阵列220中的每个外围焊点的旁边均分布有一个第二类焊点230 ;从而不仅分担了所述第一类焊点阵列220中的关键焊点221的应力和应变,对所述关键焊点221起到保护的作用,而且也保护了所述第一类焊点阵列220中的所有应力相对较大的焊点。 [0038] Please refer to FIG. 6, FIG. 6 is a front pad structure provides a schematic view of a third embodiment of the present invention, shown in FIG. 6, Example 3 and Example 1, except that the second class pads 230 distributed in the first type of outer pad array 220, i.e., the peripheral side of each of the first type of solder pad array 220 are distributed in a second type of pad 230; thereby not only share the key pad of the pad array 220 in the first type of stress and strain 221, the key pad 221 serves to protect, but also protects the pad 220 in the array of the first type All stress relatively large pad. [0039] 除此之外,实施例3与实施例1均相同,因此不再赘述。 [0039] In addition, Example 3 and Example 1 are the same, thus omitted.

[0040] 综上所述,本发明提供了一种焊点结构,包括第一类焊点阵列及多个第二类焊点,所述第二类焊点分布于所述第一类焊点阵列的外圈,所述第一类焊点阵列将所述半导体芯片与所述基板进行电性连接及机械连接,所述第二类焊点将所述半导体芯片与所述基板进行机械连接,通过在所述第一类焊点阵列的外圈设置多个第二类焊点,从而分担了所述第一类焊点阵列中的关键焊点的应力和应变,使所述关键焊点上的应力和应变减小,延后了裂纹产生的时间,提高了关键焊点的可靠性,从而使整个封装器件的寿命也得到提高。 [0040] In summary, the present invention provides a solder joint comprising a plurality of a first type and a second type of pad array pads of the second type to the first type of solder pads distributed outer array, said first array of the pad type semiconductor chip and the substrate are electrically and mechanically connected to the second type of mechanical connection pads of the semiconductor chip and the substrate, by providing a plurality of second type of the first type of outer pads in the pad array, whereby the first type of sharing the key pad array solder joint stress and strain, so that the key pad the stress and strain is reduced, the delay time of cracks, improve the reliability of the key pad, so that the life of the packaged device is also improved.

[0041] 显然,本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。 [0041] Obviously, those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (7)

1.一种焊点结构,位于一基板上,用于将半导体芯片连接至所述基板上,其特征在于,包括: 第一类焊点阵列,将所述半导体芯片与所述基板进行电性连接及机械连接; 多个第二类焊点,分布于所述第一类焊点阵列的外圈,将所述半导体芯片与所述基板进行机械连接。 A solder structure located on a substrate, for connecting the semiconductor chip onto the substrate, characterized by comprising: a first pad array type, the semiconductor chip and the substrate are electrically and mechanical connection; a second plurality of pads type, distributed in the first type of outer pad array, the semiconductor chip is mechanically connected to the substrate.
2.如权利要求1所述的焊点结构,其特征在于,所述第一类焊点阵列包括多个关键焊点,所述关键焊点的位置距离所述焊点阵列的中心的距离最远;其中,所述第二类焊点分布于所述关键焊点的外圈。 2. The solder joint according to claim 1, wherein the first type comprises a plurality of key pad array pads, key pads of the uppermost position of the distance from the center of the pad array far; wherein the second type of key pads distributed in the outer ring of the solder joint.
3.如权利要求2所述的焊点结构,其特征在于,所述每个关键焊点的外圈分布有一个或多个所述第二类焊点。 Solder joint according to claim 2, wherein each of said outer profile has one or more key pads of the second type of pad.
4.如权利要求1至3任一项所述的焊点结构,其特征在于,所述第二类焊点的几何尺寸与所述第一类焊点阵列中的焊点的几何尺寸相同。 4. A solder joint according to any one of claims 1 to claim 3, wherein said second type of pad identical geometry with the first type of solder pad array geometry.
5.如权利要求1至3任一项所述的焊点结构,其特征在于,所述第二类焊点的焊料与所述第一类焊点阵列中的焊点的焊料相同。 5. A solder joint according to any one of claims 1 to claim 3, characterized in that the same type of the second solder pad of the first type of pad array solder joints.
6.如权利要求1至3任一项所述的焊点结构,其特征在于,所述第二类焊点之间的最短距离与所述第一类焊点阵列中的焊点之间的最短距离相等。 6. A solder joint 1-1 according to claims 1-3, characterized in that, between the shortest distance between the first pad of the second type based solder pad array with equal to the shortest distance.
7.如权利要求1至3任一项所述的焊点结构,其特征在于,所述第二类焊点的制备工艺与所述第一类焊点阵列中的焊点的制备工艺相同,且同时完成。 1 to 7. The solder joint according to any one of claims 3, wherein the second type of the same manufacturing process and manufacturing process of the first type solder pad array solder joint, and at the same time to complete.
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