CN103117260A - Welding spot structure - Google Patents
Welding spot structure Download PDFInfo
- Publication number
- CN103117260A CN103117260A CN2011103621734A CN201110362173A CN103117260A CN 103117260 A CN103117260 A CN 103117260A CN 2011103621734 A CN2011103621734 A CN 2011103621734A CN 201110362173 A CN201110362173 A CN 201110362173A CN 103117260 A CN103117260 A CN 103117260A
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- Prior art keywords
- solder joint
- pad array
- welding spot
- equations
- crucial
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention discloses a welding spot structure which comprises a first-class welding spot array and a plurality of second-class welding spots, wherein the second-class welding spots are distributed on the outer circle of the first-class welding spot array, the first-class welding spot array enables a semiconductor chip to be in electrical and mechanical connection with a substrate, and the second-class welding spots enable the semiconductor chip to be in mechanical connection with the substrate. As the plurality of second-class welding spots are installed on the outer circle of the first-class welding spot array, rigidity of the whole welding spot structure is increased, stress and strain on key welding spots are decreased, time of crack generation is delayed, reliability of the key welding spots is improved, and therefore service life of a whole packaging device is prolonged.
Description
Technical field
The present invention relates to the semiconductor packaging field, relate in particular to a kind of welding spot structure that strengthens reliability.
Background technology
Along with making rapid progress of electronics and information industry, packaging density is more and more higher, the New type of S that has been born MT, MCM technology, and the solder joint in microelectronic component is also more and more less, and reliability requirement is improved day by day.The encapsulation technologies such as the SMT encapsulation technology that extensively adopts in Electronic Packaging and chip size packages (CSP), welded ball array (BGA) all directly realize electricity and mechanical connection (mainly bearing shear strain) between device and substrate by solder joint, and the quality and reliability of solder joint has determined the quality of electronic product.
Packaging in actual use, the variation of whether switching on environment temperature makes it experience the process of temperature cycles.Fatigue failure may occur in solder joint in the temperature cycles process.Inefficacy electrical connection short circuit or the resistance of solder joint are excessive, cause device can not realize predetermined function, can't use.Therefore how to guarantee that the quality of solder joint is a major issue.
Please refer to Fig. 1 and Fig. 2 about existing chip-packaging structure, wherein, Fig. 1 is the side schematic view of existing chip-packaging structure, Fig. 2 is the front schematic view of existing chip-packaging structure, as shown in Figures 1 and 2, existing chip-packaging structure comprises substrate 100, pad array 110 (only illustrated in figure 4 * 4 pad array) and semiconductor chip 120, and described pad array 110 is electrically connected described substrate 100 and described semiconductor chip 120 and mechanical connection.And each solder joint in described pad array 110 plays the effect of electric connection and mechanical connection.Wherein, the solder joint (being the solder joint of corner location) that is positioned at chip-packaging structure central point geometric distance farthest is called crucial solder joint 111, because the stress on these crucial solder joints 111 compares that stress on other inner solder joint is larger, inelastic strain is can density higher, thereby easily produce fatigue crack and expand, finally cause component failure.
Therefore, in order to improve device reliability, should pay close attention to the crucial solder joint of corner location, reduce the size of its thermal stress and strain energy density as far as possible.Except the crucial solder joint of corner location, the stress on other outer ring solder joint in pad array is also larger, also should cause concern.
In order to improve the reliability of solder joint, in existing research, there is the scholar to propose with changing the reliability of solder joint physical dimension (height, diameter and the shape that comprise solder joint) with the method raising solder joint of scolder kind.Although this kind method is feasible, weakened the compatibility of technique, increased cost.In addition, the applicability of this method is limited, and must first study the relation of the reliability of encapsulating structure and solder joint physical dimension, scolder kind, and process is loaded down with trivial details and increased cost.In addition, increasing underfill material is also a kind of method that increases welding spot reliability.The method of this patent can adopt the underfill material method simultaneously, obtains higher welding spot reliability.
Therefore, the reliability that how effectively to improve the solder joint in chip-packaging structure becomes the key technical problem that present industry is needed solution badly.
Summary of the invention
The object of the present invention is to provide a kind of welding spot structure, to improve the reliability of the solder joint in chip-packaging structure.
For addressing the above problem, the present invention proposes a kind of welding spot structure, is positioned on a substrate, is used for semiconductor chip is connected to described substrate, and wherein, described welding spot structure comprises:
First kind pad array is electrically connected described semiconductor chip and described substrate and mechanical connection;
A plurality of Equations of The Second Kind solder joints are distributed in the outer ring of described first kind pad array, and described semiconductor chip and described substrate are carried out mechanical connection.
Optionally, described first kind pad array comprises a plurality of crucial solder joints, and the distance at the center of the described pad array of positional distance of described crucial solder joint farthest; Wherein, described Equations of The Second Kind solder joint is distributed in the outer ring of described crucial solder joint.
Optionally, the outer ring of described each crucial solder joint is distributed with one or more described Equations of The Second Kind solder joints.
Optionally, the physical dimension of the solder joint in the physical dimension of described Equations of The Second Kind solder joint and described first kind pad array is identical.
Optionally, the scolder of the solder joint in the scolder of described Equations of The Second Kind solder joint and described first kind pad array is identical.
Optionally, the beeline between the solder joint in the beeline between described Equations of The Second Kind solder joint and described first kind pad array equates.
Optionally, the preparation technology of the solder joint in the preparation technology of described Equations of The Second Kind solder joint and described first kind pad array is identical, and completes simultaneously.
compared with prior art, welding spot structure provided by the invention comprises first kind pad array and a plurality of Equations of The Second Kind solder joint, described Equations of The Second Kind solder joint is distributed in the outer ring of described first kind pad array, described first kind pad array is electrically connected described semiconductor chip and described substrate and mechanical connection, described Equations of The Second Kind solder joint carries out mechanical connection with described semiconductor chip and described substrate, by the outer ring in described first kind pad array, a plurality of Equations of The Second Kind solder joints are set, alleviated the stress and strain of the crucial solder joint in described first kind pad array, stress and strain on described crucial solder joint is reduced, increase the rigidity of structure, delayed the time that crackle produces, improved the reliability of crucial solder joint, thereby also be improved in the life-span of whole packaging.
Description of drawings
Fig. 1 is the side schematic view of existing chip-packaging structure;
Fig. 2 is the front schematic view of existing chip-packaging structure;
The side schematic view of the welding spot structure that Fig. 3 provides for first embodiment of the invention;
The front schematic view of the welding spot structure that Fig. 4 provides for first embodiment of the invention;
The front schematic view of the welding spot structure that Fig. 5 provides for second embodiment of the invention;
The front schematic view of the welding spot structure that Fig. 6 provides for third embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the welding spot structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only is used for convenient, the purpose of the aid illustration embodiment of the present invention lucidly.
core concept of the present invention is, a kind of welding spot structure is provided, comprise first kind pad array and a plurality of Equations of The Second Kind solder joint, described Equations of The Second Kind solder joint is distributed in the outer ring of described first kind pad array, described first kind pad array is electrically connected described semiconductor chip and described substrate and mechanical connection, described Equations of The Second Kind solder joint carries out mechanical connection with described semiconductor chip and described substrate, by the outer ring in described first kind pad array, a plurality of Equations of The Second Kind solder joints are set, thereby shared the stress and strain of the crucial solder joint in described first kind pad array, stress and strain on described crucial solder joint is reduced, delayed the time that crackle produces, improved the reliability of crucial solder joint, thereby also be improved in the life-span of whole packaging.
Embodiment 1
Please refer to Fig. 3 and Fig. 4, wherein, the side schematic view of the welding spot structure that Fig. 3 provides for first embodiment of the invention, the front schematic view of the welding spot structure that Fig. 4 provides for first embodiment of the invention, as shown in Figures 3 and 4, the welding spot structure that first embodiment of the invention provides, be positioned on a substrate 200, be used for semiconductor chip 210 is connected to described substrate 200, wherein, described welding spot structure comprises:
First kind pad array 220 is electrically connected described semiconductor chip 210 and mechanical connection with described substrate 200; Wherein, described first kind pad array 220 comprises a plurality of crucial solder joints 221, and the distance at the center of the described pad array of positional distance of described crucial solder joint 221 farthest;
A plurality of Equations of The Second Kind solder joints 230 are distributed in the outer ring of described first kind pad array 220, and described semiconductor chip 210 is carried out mechanical connection with described substrate 200.Particularly, Equations of The Second Kind solder joint 230 of the outer ring of described each crucial solder joint 221 distribution.It should be noted that, described Equations of The Second Kind solder joint 230 only carries out mechanical connection with described semiconductor chip 210 with described substrate 200, is not electrically connected, and therefore the existence of described Equations of The Second Kind solder joint 230 and damage can't impact the normal operation of device.
By the outer ring at described crucial solder joint 221, an Equations of The Second Kind solder joint 230 is set, thereby shared the stress and strain of the crucial solder joint 221 in described first kind pad array 220, stress and strain on described crucial solder joint 221 is reduced, delayed the time that crackle produces, improved the reliability of crucial solder joint 221, thereby the life-span of whole packaging also is improved.
Further, the physical dimension of the solder joint in the physical dimension of described Equations of The Second Kind solder joint 230 and described first kind pad array 220 is identical; The scolder of the solder joint in the scolder of described Equations of The Second Kind solder joint 230 and described first kind pad array 220 is identical; Beeline between solder joint in beeline between described Equations of The Second Kind solder joint 230 and described first kind pad array 220 also equates; Thereby make the preparation technology of described Equations of The Second Kind solder joint 230 and preparation technology's compatibility of the solder joint in described pad array 220.
Further, the preparation technology of the solder joint in the preparation technology of described Equations of The Second Kind solder joint 230 and described first kind pad array 220 is identical, and completes simultaneously.
Please refer to Fig. 5, the front schematic view of the welding spot structure that Fig. 5 provides for second embodiment of the invention, as shown in Figure 5, embodiment 2 is with the difference of embodiment 1, and the periphery of each the crucial solder joint 221 in described first kind pad array 220 is distributed with a plurality of Equations of The Second Kind solder joints 230 (only illustrating 3 in figure).Be distributed with a plurality of Equations of The Second Kind solder joints 230 by the periphery at each crucial solder joint 221, thereby alleviated better the stress and strain of the crucial solder joint 221 in described first kind pad array 220.And, the beeline d between described Equations of The Second Kind solder joint 230
2And the beeline d between the solder joint in described first kind pad array 220
1Equate.
In addition, embodiment 2 is all identical with embodiment 1, therefore repeats no more.
Embodiment 3
Please refer to Fig. 6, the front schematic view of the welding spot structure that Fig. 6 provides for third embodiment of the invention, as shown in Figure 6, embodiment 3 is with the difference of embodiment 1, described Equations of The Second Kind solder joint 230 is distributed in the outer ring of described first kind pad array 220, and namely the side of each the peripheral solder joint in described first kind pad array 220 is distributed with an Equations of The Second Kind solder joint 230; Thereby not only shared the stress and strain of the crucial solder joint 221 in described first kind pad array 220, described crucial solder joint 221 has been played the effect of protection, and protected the relatively large solder joint of all stress in described first kind pad array 220.
In addition, embodiment 3 is all identical with embodiment 1, therefore repeats no more.
in sum, the invention provides a kind of welding spot structure, comprise first kind pad array and a plurality of Equations of The Second Kind solder joint, described Equations of The Second Kind solder joint is distributed in the outer ring of described first kind pad array, described first kind pad array is electrically connected described semiconductor chip and described substrate and mechanical connection, described Equations of The Second Kind solder joint carries out mechanical connection with described semiconductor chip and described substrate, by the outer ring in described first kind pad array, a plurality of Equations of The Second Kind solder joints are set, thereby shared the stress and strain of the crucial solder joint in described first kind pad array, stress and strain on described crucial solder joint is reduced, delayed the time that crackle produces, improved the reliability of crucial solder joint, thereby also be improved in the life-span of whole packaging.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. a welding spot structure, be positioned on a substrate, is used for semiconductor chip is connected to described substrate, it is characterized in that, comprising:
First kind pad array is electrically connected described semiconductor chip and described substrate and mechanical connection;
A plurality of Equations of The Second Kind solder joints are distributed in the outer ring of described first kind pad array, and described semiconductor chip and described substrate are carried out mechanical connection.
2. welding spot structure as claimed in claim 1, is characterized in that, described first kind pad array comprises a plurality of crucial solder joints, and the distance at the center of the described pad array of positional distance of described crucial solder joint farthest; Wherein, described Equations of The Second Kind solder joint is distributed in the outer ring of described crucial solder joint.
3. welding spot structure as claimed in claim 2, is characterized in that, the outer ring of described each crucial solder joint is distributed with one or more described Equations of The Second Kind solder joints.
4. welding spot structure as described in the claims 1 to 3 any one, is characterized in that, the physical dimension of the solder joint in the physical dimension of described Equations of The Second Kind solder joint and described first kind pad array is identical.
5. welding spot structure as described in the claims 1 to 3 any one, is characterized in that, the scolder of the solder joint in the scolder of described Equations of The Second Kind solder joint and described first kind pad array is identical.
6. welding spot structure as described in the claims 1 to 3 any one, is characterized in that, the beeline between the solder joint in the beeline between described Equations of The Second Kind solder joint and described first kind pad array equates.
7. welding spot structure as described in the claims 1 to 3 any one, is characterized in that, the preparation technology of the solder joint in the preparation technology of described Equations of The Second Kind solder joint and described first kind pad array is identical, and completes simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103621734A CN103117260A (en) | 2011-11-16 | 2011-11-16 | Welding spot structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103621734A CN103117260A (en) | 2011-11-16 | 2011-11-16 | Welding spot structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103117260A true CN103117260A (en) | 2013-05-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103621734A Pending CN103117260A (en) | 2011-11-16 | 2011-11-16 | Welding spot structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971949A (en) * | 2016-01-14 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953589A (en) * | 1996-12-30 | 1999-09-14 | Anam Semiconductor Inc. | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same |
| TW445612B (en) * | 2000-08-03 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Solder ball array structure to control the degree of collapsing |
| US6655022B1 (en) * | 1998-09-24 | 2003-12-02 | Intel Corporation | Implementing micro BGA assembly techniques for small die |
| CN2879422Y (en) * | 2005-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Conducting cushion configuration of grid array package |
| CN101593734A (en) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | Flip-Chip Using and semiconductor die package |
-
2011
- 2011-11-16 CN CN2011103621734A patent/CN103117260A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953589A (en) * | 1996-12-30 | 1999-09-14 | Anam Semiconductor Inc. | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same |
| US6655022B1 (en) * | 1998-09-24 | 2003-12-02 | Intel Corporation | Implementing micro BGA assembly techniques for small die |
| TW445612B (en) * | 2000-08-03 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Solder ball array structure to control the degree of collapsing |
| CN2879422Y (en) * | 2005-10-11 | 2007-03-14 | 威盛电子股份有限公司 | Conducting cushion configuration of grid array package |
| CN101593734A (en) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | Flip-Chip Using and semiconductor die package |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971949A (en) * | 2016-01-14 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| CN106971949B (en) * | 2016-01-14 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
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Application publication date: 20130522 |
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