CN103116379A - Self-calibration current source system - Google Patents
Self-calibration current source system Download PDFInfo
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- CN103116379A CN103116379A CN2013100314678A CN201310031467A CN103116379A CN 103116379 A CN103116379 A CN 103116379A CN 2013100314678 A CN2013100314678 A CN 2013100314678A CN 201310031467 A CN201310031467 A CN 201310031467A CN 103116379 A CN103116379 A CN 103116379A
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- self calibration
- current source
- resistance
- resistance array
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Abstract
The invention provides a self-calibration current source system which comprises a current source and further comprises a self-calibration resistance array, a comparator and a control module. The self-calibration resistance array is arranged to be connected with an interior resistance array of the current source, the comparator compares voltage of the self-calibration resistance array and voltage of an output terminal resistor of a chip, and the control module receives a comparing result of the comparator and outputs a control signal to control the self-calibration resistance array and the interior resistance array which is connected with the self-calibration resistance array. The self-calibration current source system can conduct automatically adjusting so as to enable resistance of the interior resistance array to be matched with resistance of the output terminal resistor.
Description
Technical field
The present invention relates to the current source correlation technique, more specifically, relate to the relevant design of current source reference resistance.
Background technology
Moore's Law is satisfied in the development of integrated circuit industry, and the established technology size reduces with the speed in per generation 30%, and the density of integrated circuit increases with 2 times of speed, and guarantees the transistor performance steady-state growth.But dwindling of process brought larger technological fluctuation, and this technological fluctuation mainly comes from manufacturing process.
Fig. 1 is conventional high-precision current source, and it for example is applied in Low Voltage Differential Signal numeral output analog to digital conversion (ADC) chip.Shown in the conventional current source in, V
GBThis ADC chip internal band-gap circuit output voltage, R
External12 is precision resister, and it arranges the outside conduct of current source with reference to resistance.In practical application, not all situation all allows at chip pin outer setting non-essential resistance R
External12.If R can not be set
External12, have to replace this non-essential resistance R with the internal resistance of this chip
External12, thus cause the output Iout of current source extremely responsive to technique, voltage and temperature (PVT:Process, Voltage, Temperature).
Therefore, for the current source that relates to CMOS technique, in the situation that there is no external reference resistance, its characteristic will fluctuate along with the variation of technique, temperature, voltage.In some situation, use the analog core module of the high-speed ﹠ resolution ADC of this current source, will face serious hydraulic performance decline such as sampling hold circuit etc.
Summary of the invention
In view of this, the invention provides a kind of self calibration current source system, can be applied in Low Voltage Differential Signal numeral output modulus conversion chip, this self calibration current source system comprises current source, also comprise: the self calibration electric resistance array, it arranges in the mode related with the internal resistance array of described current source; Comparer compares the voltage of the outlet terminal resistance of the voltage of described self calibration electric resistance array and described chip; Control module, it receives the comparative result of described comparer, exports accordingly control signal to control self calibration electric resistance array and the described internal resistance array related with described self calibration electric resistance array.
Preferably, in self calibration current source of the present invention system, the cell resistance in described self calibration electric resistance array is corresponding one by one with the cell resistance in described internal resistance array.
Preferably, in self calibration current source of the present invention system, the resistance value of each cell resistance in described internal resistance array be the cell resistance in the self calibration electric resistance array corresponding with it resistance value k doubly.
Preferably, self calibration current source of the present invention system also comprises the first switching device group, and it is arranged between described internal resistance array and described control module, and according to described control signal on-off; And the second switch set of devices, it is arranged between described self calibration electric resistance array and described control module, and according to described control signal on-off.
Preferably, in self calibration current source of the present invention system, each switching device in described the first switching device group is separately positioned between a cell resistance and described control module of described internal resistance array, each switching device in described second switch set of devices is separately positioned between cell resistance and control module of self calibration electric resistance array, thereby makes the switching device in the first switching device group corresponding one by one with switching device in the second switch device.
Preferably, in calibration current origin system of the present invention, the control signal of each switching device in described the first switching device group is identical with the control signal with switching device corresponding to this switching device in the second switch set of devices.
Preferably, in calibration current origin system of the present invention, described control module is made of up-down counter and steering logic.
Preferably, in calibration current origin system of the present invention, described comparer is two differential clocks latched comparators.
In current source of the present invention system, be that outlet terminal resistance is as reference resistance with existing standard port, and the magnitude of voltage of the self calibration electric resistance array of its voltage and the set internal resistance array that is associated with current source is compared, thereby adjust the current source internal resistance by this comparative result, can control and keep thus one PVT insensitive current source system be need not additionally at chip port, non-essential resistance to be set.
Description of drawings
Fig. 1 is conventional high-precision current source.
Fig. 2 is the structural representation of self calibration current source according to an embodiment of the invention system.
Fig. 3 is the circuit diagram of a concrete example of self calibration current source shown in Figure 2 system.
Embodiment
Now further illustrate by reference to the accompanying drawings the present invention.It will be appreciated by those skilled in the art that, below just in conjunction with embodiment, purport of the present invention is carried out non-limitative illustration, the scope that the present invention advocates is definite by appended claim, and any modification, change that does not break away from spirit of the present invention all should be contained by claim of the present invention.
Of the present inventionly focus on utilizing the existing outlet terminal resistance of chip as reference resistance, and in current source inside, the self calibration electric resistance array is set, thereby make the inside all-in resistance of current source approach gradually reference resistance.
Fig. 2 is the structural representation of self calibration current source according to an embodiment of the invention system.As example, this paper describes in Low Voltage Differential Signal (LVDS) numeral output analog to digital conversion (ADC) chip with this current source system applies, but not as limit.For for purpose of brevity, hereinafter " Low Voltage Differential Signal (LVDS) numeral output analog to digital conversion (ADC) chip " is called LVDS ADC chip.
As shown in Figure 2, the self calibration current source system 20 that is applied in LVDS ADC chip comprises current source basic structure, self calibration electric resistance array 201, voltage comparator 204 and control module 206.Current source basic structure and conventional current source are basic identical, and itself are not emphasis of the present invention place, just do not add to describe at this.Self calibration electric resistance array 201 is associated with the internal resistance array 202 of current source, make thus 206 pairs of self calibration electric resistance arrays 201 of control module the control action linkability act on internal resistance array 202.The voltage 203V of the outlet terminal resistance 203 of the voltage 201V of self-calibration circuit array 201 and LVDS ADC chip is fed to voltage comparator 204.204 couples of voltage 202V of voltage comparator and 203V compare, and send comparative result to control module 206.Control module 206 is controlled the self calibration electric resistance array according to this comparative result, and control simultaneously the internal resistance array 202 related with this self calibration electric resistance array 201, the resistance value that makes the total resistance value of this internal resistance array approach gradually the outlet terminal resistance 203 of LVDS ADC chip.
As example, control module 206 is electrically connected by the first switching device group 501 and internal resistance array 202, is electrically connected by second switch set of devices 502 and self calibration electric resistance array 201.The first switching device group 501 and second switch set of devices 502 all receive the control signal from control module 206, and are switched on or switched off according to this signal.According to an example of the present invention, self calibration electric resistance array 201 arranges in the mode corresponding with internal resistance array 202, and any one cell resistance that this corresponded manner makes control module control in the self calibration electric resistance array just can be controlled cell resistance corresponding with this cell resistance in the internal resistance array equally.Cell resistance in self calibration electric resistance array 201 can be a resistance, also can be in parallel by a plurality of resistance or series connection and the unit that forms.In each example of this paper, cell resistance is the cell array that consists of electric resistance array.
Fig. 3 is the circuit diagram of a concrete example of self calibration current source shown in Figure 2 system.In this example, voltage comparator 204 is embodied as two differential clocks latched comparators 304, and control module 206 is made of up-down counter and steering logic.As shown in the figure, internal resistance array 202 comprises resistance kR1, kR2, kR3, kR4 and kR5 in parallel, resistance kR2, kR3, kR4 and kR5 are electrically connected by the first switching device group 501 and control module 206, example ground, resistance kR2, kR3, kR4 and kR5 are respectively by be for example first switching device 5012,5013,5014 and 5015 and control module 206 electric connections of PMOS pipe.Self calibration electric resistance array 201 is realized in this example as follows: it is arranged on the earth terminal of current source basic structure in the mode corresponding to internal resistance array 202, comprise the cell resistance of five parallel connections, is calibrated resistance R1, R2, R3, R4 and R5 successively; The resistance value of the resistance kR1 of internal resistance array 202 be self calibration electric resistance array 201 resistance R 1 k doubly, the resistance value of resistance kR2 be self calibration electric resistance array 201 resistance R 2 k doubly, the like, resistance kR3 be R3 k doubly, resistance kR4 be R4 k doubly, resistance kR5 be R5 k doubly.Resistance R 2, R3, R4 and R5 in self calibration electric resistance array 201 is electrically connected by second switch set of devices 502 and control module 206, example ground, resistance R 2, R3, R4 and the R5 in self calibration electric resistance array 201 is respectively by being for example that the second switch device 5022,5023,5024 and 50255 of PMOS pipe is electrically connected to control module 206.the switching device 5012 of the first switching device group 501 and the switching device 5022 of second switch set of devices 502 all are electrically connected to the first control end 00 of control module 206, the switching device 5013 of the first switching device group 501 and the switching device 5023 of second switch set of devices 502 all are electrically connected to the second control end 01 of control module 206, the switching device 5014 of the first switching device group 501 and the switching device 5024 of second switch set of devices 502 all are electrically connected to the 3rd control end 02 of control module 206, the switching device 5015 of the first switching device group 501 and the switching device 5025 of second switch set of devices 502 all are electrically connected to the 3rd control end 03 of control module 206, control module 206 can be controlled self calibration electric resistance array 201 and internal resistance array 202 simultaneously thus.In this example, resistance kR1, kR2, kR3, kR4 and kR5 are the cell resistance that consists of the internal resistance array, and resistance R 2, R3, R4 and R5 are the cell resistance that consists of the self calibration electric resistance array.
The voltage of self calibration electric resistance array 201 is I
0* R
T, I wherein
0LVDS direct current output driving current, R
TTotal resistance value for self calibration electric resistance array 201.The outside outlet terminal resistance 203 of LVDS ADC chip is R
L, its voltage is I
0* R
L, I wherein
0LVDS direct current output driving current, R
LResistance value for terminal resistance 203.The voltage 201V of self calibration electric resistance array 201 and the voltage 203V of terminal resistance 203 are fed to two differential clocks latched comparators 304.The comparative result of two differential clocks latched comparators 304 is fed to control module 206.
After example but without limitation, current source system powered on, in the initial clock period, in the situation that clock is 0, two differential clocks latched comparators 304 were output as Q and keep its state; At clock=1, two differential clocks latched comparators 304 compare the voltage 201V of self calibration electric resistance array 201 and the voltage 203V of terminal resistance 203, and comparative result Q is fed to control module 206.Comprised two continuous clocks during the cycle at Q=1, the counter in control module 206 adds 1; Keep two continuous clocks during the cycle at Q=0, this counter subtracts 1; When Q=1 comprises a clock period and when next clock period Q=0, the output terminal 00,01 of control module 206,02 and 03 remains unchanged.In the situation that the internal logic circuit of control module 206 finds that this output terminal 00,01,02 and 03 remains unchanged, i.e. the state of a control signal locking switch of mark and forbid self calibration electric resistance array 201 with conserver power source.
Under the output terminal 00,01,02 and 03 of control module 206 is controlled, be for example that each switching device of PMOS switch is connected, the total resistance value that internal resistance array kR1, kR2, kR3, kR4 and kR5 consist of moves closer to non-essential resistance R
LIn the present invention, resistance R
TWith resistance R
LThe comparison precision, that is the precision of two differential clocks latched comparators 304 is higher, the output terminal of the resistance number in electric resistance array and control module 206 is just more.
As mentioned above, due to the incidence relation of self calibration electric resistance array and internal resistance array, make self calibration electric resistance array and terminal resistance R
LComparative result can act on the internal resistance array by control module 206.And the internal resistance array is when being adjusted, and the self calibration loop is controlled the effect of module 206 simultaneously, and the self calibration loop that is controlled will be further and terminal resistance R
LCompare, thereby according to this comparative result, adjust the internal resistance array, until the resistance value of internal resistance array and terminal resistance R
LQuite.
Although described the present invention in conjunction with concrete example, it will be appreciated by those skilled in the art that, each parts in example are not limited with parts described herein, only need to reach corresponding function and get final product.For example, the first switching device group and second switch set of devices can adopt other can reach the device of on-off function.
Claims (8)
1. a self calibration current source system, comprise current source, it is characterized in that, described self calibration current source system also comprises:
The self calibration electric resistance array, it arranges in the mode related with the internal resistance array of described current source;
Comparer, its voltage with the outlet terminal resistance of the voltage of described self calibration electric resistance array and described chip compares; And
Control module, it receives the comparative result of described comparer, exports accordingly control signal to control self calibration electric resistance array and the described internal resistance array related with described self calibration electric resistance array.
2. self calibration current source as claimed in claim 1 system, is characterized in that, the cell resistance in described self calibration electric resistance array is corresponding one by one with the cell resistance in described internal resistance array.
3. self calibration current source as claimed in claim 2 system, is characterized in that, the resistance value of each cell resistance in described internal resistance array be the cell resistance in the self calibration electric resistance array corresponding with it resistance value k doubly.
4. self calibration current source as claimed in claim 2 system, is characterized in that, described self calibration current source system also comprises:
The first switching device group, it is arranged between described internal resistance array and described control module, and according to described control signal on-off; And
The second switch set of devices, it is arranged between described self calibration electric resistance array and described control module, and according to described control signal on-off.
5. self calibration current source as claimed in claim 4 system, it is characterized in that, each switching device in described the first switching device group is separately positioned between a cell resistance and described control module of described internal resistance array, each switching device in described second switch set of devices is separately positioned between cell resistance and control module of self calibration electric resistance array, thereby makes the switching device in the first switching device group corresponding one by one with switching device in the second switch device.
6. self calibration current source as claimed in claim 5 system, is characterized in that, the control signal of each switching device in described the first switching device group is identical with the control signal with switching device corresponding to this switching device in the second switch set of devices.
7. self calibration current source as claimed in claim 1 system, is characterized in that, described control module is made of up-down counter and steering logic.
8. self calibration current source as claimed in claim 1 system, is characterized in that, described comparer is two differential clocks latched comparators.
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|---|---|---|---|
| CN201310031467.8A CN103116379B (en) | 2013-01-28 | 2013-01-28 | Self-calibration current source system |
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|---|---|---|---|
| CN201310031467.8A CN103116379B (en) | 2013-01-28 | 2013-01-28 | Self-calibration current source system |
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| CN103116379A true CN103116379A (en) | 2013-05-22 |
| CN103116379B CN103116379B (en) | 2015-04-01 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014114004A1 (en) * | 2013-01-28 | 2014-07-31 | 香港中国模拟技术有限公司 | Self-calibration current source system |
| CN104181473A (en) * | 2014-08-25 | 2014-12-03 | 长沙瑞达星微电子有限公司 | Current source calibrating circuit |
| CN105119594A (en) * | 2015-07-30 | 2015-12-02 | 中国电子科技集团公司第五十八研究所 | High-speed serial port load automatic calibration circuit |
| CN107229302A (en) * | 2017-06-30 | 2017-10-03 | 西安理工大学 | The on-chip system of voltage controlled current source drive circuit and put forward high-precision method using it |
| CN112485499A (en) * | 2020-12-29 | 2021-03-12 | 深圳市芯天下技术有限公司 | Test method and device for automatic calibration of reference current, storage medium and terminal |
| CN113342100A (en) * | 2020-03-03 | 2021-09-03 | 瑞昱半导体股份有限公司 | Bias current generating circuit |
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| JPH02288616A (en) * | 1989-04-28 | 1990-11-28 | Hitachi Ltd | Self-calibration type d/a converter and self-calibration type a/d converter using the d/a converter |
| CN101320278A (en) * | 2008-06-25 | 2008-12-10 | 苏州中科半导体集成技术研发中心有限公司 | CMOS reference source |
| CN101571709A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Method and circuit for regulating loads of dynamic self-adaptation terminal |
| TW201041317A (en) * | 2009-05-15 | 2010-11-16 | Realtek Semiconductor Corp | Self-calibrated current source and DAC using the same and operation method thereof |
| CN203191868U (en) * | 2013-01-28 | 2013-09-11 | 香港中国模拟技术有限公司 | Self-calibration current source system |
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2013
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Patent Citations (5)
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| JPH02288616A (en) * | 1989-04-28 | 1990-11-28 | Hitachi Ltd | Self-calibration type d/a converter and self-calibration type a/d converter using the d/a converter |
| CN101320278A (en) * | 2008-06-25 | 2008-12-10 | 苏州中科半导体集成技术研发中心有限公司 | CMOS reference source |
| TW201041317A (en) * | 2009-05-15 | 2010-11-16 | Realtek Semiconductor Corp | Self-calibrated current source and DAC using the same and operation method thereof |
| CN101571709A (en) * | 2009-06-11 | 2009-11-04 | 和芯微电子(四川)有限公司 | Method and circuit for regulating loads of dynamic self-adaptation terminal |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014114004A1 (en) * | 2013-01-28 | 2014-07-31 | 香港中国模拟技术有限公司 | Self-calibration current source system |
| CN104181473A (en) * | 2014-08-25 | 2014-12-03 | 长沙瑞达星微电子有限公司 | Current source calibrating circuit |
| CN105119594A (en) * | 2015-07-30 | 2015-12-02 | 中国电子科技集团公司第五十八研究所 | High-speed serial port load automatic calibration circuit |
| CN107229302A (en) * | 2017-06-30 | 2017-10-03 | 西安理工大学 | The on-chip system of voltage controlled current source drive circuit and put forward high-precision method using it |
| CN113342100A (en) * | 2020-03-03 | 2021-09-03 | 瑞昱半导体股份有限公司 | Bias current generating circuit |
| CN113342100B (en) * | 2020-03-03 | 2023-03-14 | 瑞昱半导体股份有限公司 | Bias current generating circuit |
| CN112485499A (en) * | 2020-12-29 | 2021-03-12 | 深圳市芯天下技术有限公司 | Test method and device for automatic calibration of reference current, storage medium and terminal |
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| CN103116379B (en) | 2015-04-01 |
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