CN103107776B - A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof - Google Patents
A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof Download PDFInfo
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Abstract
The band that the present invention discloses a kind of super low-power consumption leads to frequency discrimination method and comprises: band logical frequency discriminator configuration frequency discrimination parameter configuration word; Start the detection to input signal and counting; Detect that spectral artifacts passes through to reset again to count, filter out-band is disturbed outward and in-band noise; Detect that the rising edge count value of normal signal and clock count value and relative set value are made comparisons to judge, within the setting clock cycle, meet parameter setting values scope, produce high level enable signal, enable storbing gate allows input signal to export, and realizes arousal function.A kind of band of super low-power consumption leads to frequency discriminator, comprise numerical frequency comparator and state machine, numerical frequency comparator is its configuration frequency discrimination parameter value by state machine, according to input signal detection count value and clock count value, make comparisons with corresponding configuration value, generate enable signal, filter out-band is disturbed outward and in-band noise signal, and judgement is selected input signal also.Super low-power consumption band leads to frequency discriminator and is widely used in Internet of Things and wireless sense network as waking receiver up.
Description
Technical field
The invention belongs to radio communication and CMOS integrated circuit (IC) design field, particularly low-power consumption frequency discriminator field, the band being specially a kind of super low-power consumption leads to frequency discriminator and method.
Background technology
Wireless communication receiver is in the receiver structure of current main flow, all take down-conversion scheme, radiofrequency signal is after low noise amplifier amplifies, deliver to frequency mixer together with local oscillation signal, carry out lower mixing, obtain Low Medium Frequency or zero intermediate frequency signals, again after complex filter, suppress image signal, then after automatic growth control, export to baseband processor through A/D.This scheme receiving sensitivity is good, and signal to noise ratio is high, suppress Image interference strong, but this structure needs frequency synthesizer to provide local oscillation signal, according to more than applicable cases circuit power consumption is from 10mA to 100mA not etc., there is the defect that circuit power consumption is large.
In the Internet of Things applied widely or wireless sense network, a lot of node or equipment are all by powered battery, one piece of battery needs maintenance equipment service time of 5 ~ 10 years, in the application of this super low-power consumption, the guarantee equipment most of the time is needed to be close, only when being waken up, main circuit is just opened and is carried out transceiving data, other time only wake receiver up and work always.Adopt the function waking receiver up of awakening technology similar with common receiver, from the radio frequency signal of several GHz, demodulating modulation signal or data, judge whether to comprise wake-up signal, opening main circuit for determining whether, carry out data transmit-receive work.Wake receiver up and there is characteristics of energy saving, but but very harsh to the power consumption requirements waking receiver up, and circuit power consumption should at below 10uA.Obviously, adopt the wireless communication receiver of down-conversion scheme above can not meet the super low-power consumption requirement adopting and wake receiver up at all.
Summary of the invention
The band that an object of the present invention is to provide a kind of super low-power consumption leads to frequency discrimination method, with arrange frequency discrimination parameter configuration value be that frequency discrimination condition is led to the band of supplied with digital signal, compared by condition, generation wakes enable signal up, control to export supplied with digital signal, otherwise close and export supplied with digital signal, realize the Energy Saving Control waking receiver up, reach the object of super low-power consumption.Another object is that the band of openly a kind of super low-power consumption leads to frequency discriminator, it comprises numerical frequency comparator and state machine, the band of super low-power consumption is adopted to lead to frequency discrimination method, realize the arousal function waking receiver up, the noise that energy inhibition zone is disturbed outward or is externally received in band and the noise jamming due to low consumption circuit itself, and meet receiving sensitivity requirement, make reception function in the power consumption of below 10uA, from GHz radio frequency signal, demodulate modulating data or signal.
Object and the above-mentioned technical problem of invention are realized by technical scheme below.
The band of super low-power consumption leads to a frequency discriminator, and it is, the band of the super low-power consumption of modular structure leads to the logical frequency discriminator of frequency discriminator abbreviation band and comprises numerical frequency comparator and state machine; Wherein
The input of numerical frequency comparator connects the output of previous stage radio-frequency front-end process comparator, and the output of numerical frequency comparator connects the input of rear stage digital baseband processor, exports the input data from previous stage output for gating; Enable control end and the reseting controling end of state machine are connected enable control line and the reset control line of rear stage digital baseband processor respectively, the counting of state machine and the counting of reset control line linking number word frequency comparator and reseting controling end, the frequency discrimination parameter configuration end of the frequency discrimination parameter configuration line linking number word frequency comparator of state machine; The logical frequency discriminator output of band, for waking control end up, wakes control signal Y up for exporting one.
Described band leads to frequency discriminator, and it is that described numerical frequency comparator comprises falling edge detectors, rising edge counter, reset unit, clock counter, comparator, parameters dispensing unit, enable storbing gate; Wherein
Through the input data cube computation falling edge detectors input of radio-frequency front-end process, an output connect state machine of falling edge detectors, this rising edge detects output and is used for making state machine enter count status, and open corresponding rising edge counter and clock counter counting, another output of falling edge detectors connects the input of rising edge counter, the digital control configuration words P of the configuration end connect state machine of falling edge detectors, falling edge detectors also has an output to connect the input of reset unit, the reset terminal of the output connect state machine of reset unit, for the non-homogeneous consecutive hours of rising edge being detected when falling edge detectors, control reset unit and export reset signal to state machine, make state machine warm reset, the input end of clock of clock counter connects reference clock signal, the starting end of clock counter, stop end and reset terminal connect state machine start count, the control signal end stopping counting and reset, the configuration words end connect state machine configuration words ER of parameters dispensing unit, DUP, DDN, parameters configuration for completing the logical frequency discriminator of band controls, an output of parameters dispensing unit connects clock counter, for arranging clock counter counting preset value, another output of parameters dispensing unit connects an input of comparator, for arranging comparator preset value, output and the parameters dispensing unit parameter configuration end of clock counter are connected two inputs of comparator respectively, deliver to comparator for the count value of clock counter and the preset value of setting to compare, comparator exports and connects enable storbing gate input, input data are also connected to another input of enable storbing gate, the output high potential of comparator is as enable signal, for controlling enable storbing gate, data strobe will be inputted and export, the output of comparator is also as frequency discrimination index signal simultaneously, for exporting wake-up signal.
Described band leads to frequency discriminator, and it is that described clock counter comprises frequency divider, the frequency multiplier sum counter be sequentially connected in series; Reference clock access frequency divider, frequency division is connected with frequency parameter control end parameters dispensing unit ER configuration end, counter controls end connect state machine start counting, stop counting and reset terminal, counter output connection comparator; Frequency division and the frequency parameter of clock counter arrange end and are connected parameters dispensing unit, the frequency division of clock counter and frequency parameter are configured by parameters dispensing unit ER configuration words, determine that reference clock carries out frequency dividing ratio and times frequency ratio of frequency division, for determining frequency discrimination error precision.
Described band leads to frequency discriminator, it is that described state machine is be integrated in the microprocessor in the logical frequency discriminator sheet of band, state machine connects enable signal EN from the outer digital baseband processor of sheet and reset signal RES, connect the output signal from the falling edge detectors of numerical frequency comparator, rising edge counter, reset unit, state machine exports and starts to count, stops counting and the rising edge counter of control signal wire linking number word frequency comparator resetted and the control end of clock counter simultaneously; The operating state of state machine comprises idle IDLE state, counting COUNTER state, terminates FINISH state, and state machine realizes the conversion of three kinds of operating states according to frequency discrimination work requirements.
The band of super low-power consumption leads to a frequency discrimination method, comprises the following steps:
(1) frequency discrimination parameter is configured by the state machine of the logical frequency discriminator of band;
Be numerical frequency comparator arrangement frequency discrimination parameter by the state machine of the logical frequency discriminator of band, in the memory of state machine, have frequency discrimination parameter configuration table, state machine according to radio-frequency transmitter frequency discrimination requirement, by output one group of frequency discrimination parameter configuration word of tabling look-up; Power on when chip or receive reset signal, one group of frequency discrimination parameter configuration word is configured to numerical frequency comparator;
When radio frequency front end chip powers on or receive the reset signal from digital baseband processor, the frequency discrimination parameter configuration of the logical frequency discriminator of band is started by state machine, state machine recalls one group of frequency discrimination parameter configuration word by lookup table mode and sends to numerical frequency comparator from frequency discrimination parameter configuration table, completes the frequency discrimination parameter configuration of the logical frequency discriminator of band; Frequency discrimination parameter configuration table is worked out with the corresponding frequency discrimination parameter setting values counted by the frequency discrimination demand of working frequency range scope, frequency discrimination data length and frequency discrimination error precision, one group of frequency discrimination parameter comprises reference clock counting upper limit value and lower limit value, the reference clock maximum count value of a clock cycle and rising edge count number set value;
(2) rising edge of input data is detected;
Detecting the rising edge from the input data of radio-frequency (RF) front-end circuit, when the first rising edge being detected, starting a rising edge counting number, detect each rising edge of input data, count value adds 1; Start to count reference clock signal simultaneously;
By falling edge detectors to its rising edge of input Data Detection from radio-frequency (RF) front-end circuit, when first rising edge being detected, falling edge detectors detects and outputs to state machine, state machine enters count status, rising edge counter and clock counter start counting separately, falling edge detectors, according to the frequency discrimination error precision of setting, realizes the detection of corresponding precision, meets the frequency discrimination requirement of different demand radio-frequency transmitter to input data; Detect each rising edge of input data and do to judge to input data;
(3) detect each rising edge of input data and do to judge to input data;
Detect each rising edge of input data and do to judge to input data, if the rising edge number that falling edge detectors exports is discontinuous, detection determines the discontinuous or duty cycle square wave of square-wave signal not to then sending a count signal again, state machine is done filtering and is resetted, and goes to step (2) and again detects input data rising edge; Then go to step if not (4);
If detect, initial square-wave signal is discontinuous or duty cycle square wave is not right, state machine makes filtering reset processing, make the input signal that square-wave signal is discontinuous or square wave is not right, can not export from the logical phase discriminator of band, realize the bandpass filtering to the noise signal in the interference signal outside band and band;
(4) judge whether rising edge count value reaches settings;
Rising edge count value adds 1, and judges whether rising edge count value reaches settings; If so, state machine exports and stops counting controling signal, and reference clock counter stops counting; Otherwise go to step (2);
When rising edge counter count value reaches the logical frequency discrimination parameter setting values of band, rising edge counter also stops counting.
(5) reference clock count value is judged whether within working frequency range upper and lower limit respective value scope;
Reference clock count value send comparator, and making comparisons with corresponding frequency discrimination parameter configuration value judges; If within the clock cycle of setting, reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator exports high level; Otherwise output low level, returns step (2);
Within the clock cycle of setting, rising edge count value does not meet parameter setting values, then output low level, wakes receiver up and does not possess wake-up condition;
(6) export high level do the control of enable gating and realize arousal function;
By enable unit, enable control treatment is carried out to comparator output level and input data, when comparator exports high level, selected input data, and export wake-up signal, realize arousal function; Otherwise block input data not export, realize the outer interference of band and in-band noise filtering function.
The logical frequency discriminator of band can make a good job of as wake module and wake controlling functions up, perform not arousal function time, other power consumption module of receiver is in resting state, thus obtains the energy-saving effect of super low-power consumption.Data Modulation is to the carrier transmit of high frequency, after antenna receives, the envelope signal comprising noise is demodulated through RF envelope wave detector, envelope signal is after amplifier amplifies, be converted to containing noise at interior data-signal through comparator, again after being with logical frequency discriminator frequency discrimination, the interference noise outside filter out-band, exports baseband signal to digital baseband processor process.
Described band leads to frequency discrimination method, and it is that step (1) described state machine configuration frequency discrimination parameter comprises following content:
1) working frequency range scope configuration; Modulating data operating frequency is waken up, the operating frequency upper limit value and lower limit value of configuration frequency discriminator according to concrete;
2) the input data length of frequency discrimination is configured; According to the data frame format waking modulating data up of input digital modulation data, configure band leads to the input data length that frequency discriminator receives digital modulation signals;
3) the reference clock number ER of the limits of error is configured; Under the prerequisite not affecting receiving sensitivity, do the configuration of frequency discrimination error precision according to the bit error rate requirement of system;
4) rising edge count number set value P is configured; Under guarantee wakes the prerequisite of the receiver error rate up, namely input data decision length received to operating rate and is configured;
5) scope of configurable clock generator count number set value; According to 1) working frequency range scope configurable clock generator count number set value.
Described band leads to frequency discrimination method, and it is that the first rising edge of step (2) and (3) described detection input data and each rising edge comprise following control content:
1) falling edge detectors does not detect the rising edge of first input data, and state machine is in idle IDLE state;
2) falling edge detectors detects the rising edge of first input data, exports and starts detection signal, and state machine is in counting COUNTER state;
3) falling edge detectors detects the rising edge of each input data;
A. falling edge detectors exports and send rising edge counter to a rising edge counting number:
B. reference clock send clock counter to a clock counting number:
4) if falling edge detectors detects that initial square-wave signal is discontinuous or square wave is not right,
A. falling edge detectors exports a signal to reset unit:
B. reset unit exports reseting request signal to state machine;
C. state machine exports reset signal, controls rising edge counter and clock counter clearing, and falling edge detectors restarts to detect input data;
4) the frequency discrimination data length completing configuration detects, and state machine is in and terminates FINISH state.
Described band leads to frequency discrimination method, and it is that step (4) is described and judges whether rising edge counter count value reaches settings and comprise following control content:
1) state machine does not receive rising edge counter and exports count completion signal, judge rising edge counter count value < settings, state machine continues to wait for that rising edge counter exports count completion signal, and rising edge counter continues counting, and clock counter continues counting;
2) state machine receives rising edge counter and exports count completion signal, judges rising edge counter count value >=settings;
3) state machine exports and stops count signal, and rising edge counter stops counting, and clock counter stops counting;
4) clock counter count value is delivered to the comparator reference clock number settings corresponding with the working frequency range upper and lower limit of setting and is made comparisons and judge, if count value is within the scope of working frequency range, then exports high level index signal, and enable output data; Otherwise maintain low level output index signal, and by counter resets, restart falling edge detectors, if rising edge counter does not reach preset value, then go to step (2) and continue counting.
Described band leads to frequency discrimination method, and it is that step (5) is described and judges whether reference clock count value comprises following content within working frequency range upper and lower limit respective value scope:
1) comparator is made comparisons to reference clock count value and corresponding frequency discrimination parameter configuration value and is judged;
2) if within the clock cycle of setting, reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator exports as high level;
3) within the clock cycle of setting, rising edge count value does not meet parameter setting values, and reference clock count value is not within working frequency range upper and lower limit respective value scope, and comparator exports as low level, then do not possess wake-up condition.
Described band leads to frequency discrimination method, and it is that step (6) described output high level is made enable gating and controlled and realize arousal function to comprise following content:
1) when comparator exports as high level, control enable storbing gate as enable gating signal and realize being with logical frequency discriminator gated data to export, gated data is transferred to the digital baseband processor of next stage, and gated data once transfers;
2) simultaneously, comparator exports as high level, possesses wake-up condition, and export wake-up signal to receiver, arousal function is used for realizing low-power consumption;
3) next stage digital baseband processor receives the gated data that the logical frequency discriminator of band once transmits, and feedback sends reset signal to frequency discriminator, starts the new frequency discrimination once inputting data and judgement.
Substantial effect of the present invention is:
1, to solve in Internet of Things or wireless sense network the very rigors waking receiver super low-power consumption up, make the power consumption waking receiver up be less than 5uA.
When 2, frequency discrimination judgement being carried out to the input signal received or data, inhibition zone can disturb outward and in-band noise signal, overcome the problem of the AF panel degradation that low-power consumption brings.
3, the band that super low-power consumption band leads to frequency discriminator leads to frequency discrimination and noise jamming suppresses, and is conducive to the performance at utmost ensureing front stage circuits, makes receiver obtain higher receiving sensitivity and the lower error rate.
4, circuit adopts standard CMOS to realize, and be convenient to Integrated manufacture, cost is low, and reliability is high.
5, super low-power consumption band leads to frequency discrimination method and frequency discriminator and can be widely used in the different communication system required in Internet of Things and wireless sense network, provides feasible technological approaches for super low-power consumption receives.
Accompanying drawing explanation
Fig. 1 a is a kind of super low-power consumption AM receiver composition frame chart leading to frequency discriminator with band of the present invention;
The another kind of super low-power consumption AM receiver composition frame chart leading to frequency discriminator with band of the present invention of Fig. 1 b:
In Fig. 1 a and Fig. 1 b :-11-reception antenna, 12-radio-frequency (RF) front-end circuit, 120-differentiator, 121-RF envelope wave detector, 122-amplifier, 123-comparator, the logical frequency discriminator of 13-band, 131-numerical frequency comparator, 132-state machine, 14-digital baseband processor.
Fig. 2 a is the forming circuit block diagram that the band of first embodiment of the invention leads to frequency discriminator;
Fig. 2 b is the forming circuit block diagram that the band of second embodiment of the invention leads to frequency discriminator;
In Fig. 2 a and Fig. 2 b :-21-numerical frequency comparator, 22-state machine, 211-falling edge detectors, 212-rising edge counter, 213-reset unit, 214-clock counter, 215-comparator, 216-parameters dispensing unit, 217-enable storbing gate, EN-enable signal, RST-from the reset signal of baseband processor, ER-error precision configuration words, DUP-upper frequency limit configuration words, DDN-lower-frequency limit configuration words, P-rising edge counter configuration words, the wake-up signal that Y-frequency discrimination judgement exports.
Fig. 3 is the state machine state transition diagram that the band of the embodiment of the present invention leads to frequency discriminator
In Fig. 3: 31-Idle state (IDLE), 32-counting state (COUNTER), 33-ending state (FINISH)
Fig. 4 is the workflow diagram of the embodiment of the present invention.
Fig. 5 a is the simulation waveform figure that the band of the embodiment of the present invention leads to that frequency discriminator inputs data 13KHz.
Fig. 5 b is the simulation waveform figure that the band of the embodiment of the present invention leads to that frequency discriminator inputs data 8KHz.
Embodiment
Below according to embodiment by reference to the accompanying drawings, specific implementation of the present invention is described in detail, makes technical scheme of the present invention, beneficial effect further illustrated.
The super low-power consumption AM receiver of the present invention the 1st embodiment forms block diagram as shown in Figure 1a, reception antenna 11 receives brewed amplitude modulated radio frequency signal, RF envelope wave detector 12 demodulates envelope modulated signal or the data of low frequency from amplitude modulated carrier signal, after amplifier 13 gain is amplified, deliver to comparator 14 and be quantified as digital signal.Radio frequency and AFE (analog front end) comprise structure and the circuit realiration that RF envelope wave detector 12, amplifier 13 and comparator 14 all adopt super low-power consumption, and total power consumption is within 3uA.In the digital signal that comparator 14 exports, also include the interference signal outside band and noise, also comprise because radio frequency and AFE (analog front end) adopt ultralow Consumption, the digital noise signal exported through comparator 14 that internal noise causes, digital signal and digital noise signal are delivered to the logical frequency discriminator 15 of band and are carried out frequency discrimination and filtering process, filter out-band is disturbed outward and digital noise signal, export to digital baseband processor 16 again, while the receiving sensitivity performance ensureing complete machine, control to receive error rates of data in low scope.
The super low-power consumption FM receiver of the present invention the 2nd embodiment forms block diagram as shown in Figure 1 b, in order to reach the receiver of super low-power consumption, on the basis that Fig. 1 a AM receiver is formed, one-level differentiator 10 is accessed between antenna 11 and RF envelope wave detector 12, frequency-modulated carrier signal is become FMAM carrier signal by differentiator 10, and reception process below receives by AM receiver.The AM receiver of the course of work below and Fig. 1 a is similar, no longer describes in detail.
The band of first embodiment of the invention leads to frequency discriminator and forms block diagram as shown in Figure 2 a, and it comprises numerical frequency comparator 21 and state machine 22.Numerical frequency comparator 21 comprises falling edge detectors 211, rising edge counter 212, reset unit 213, clock counter 214, comparator 215, parameters dispensing unit 216 and exports the enable storbing gate 217 of data.Input data DATA IN connects falling edge detectors 211, the output of falling edge detectors 211 is given rising edge counter 212, is exported and give reset unit 213 and carry out signal judgement simultaneously, falling edge detectors 211 exports and also gives state machine 22 simultaneously, 211 first rising edge exported as beginning detection signal, export and start frequency discrimination control signal by state machine.The output feedack of rising edge counter 212 is to state machine, output and result are also delivered to state machine by reset unit, reference clock delivers to clock counter, comparator is delivered to together with the settings that its output and parameters configure, enable storbing gate 217 is delivered to as the enable gating signal exporting data, input data DATA IN is connected to enable storbing gate 217 signal input part simultaneously, when enable gating signal is high level, enable storbing gate 217 output allows input data pass through, the band that enable storbing gate 217 exports leads to frequency discriminator and exports data DATA OUT, that filter out-band disturbs the input data with in-band noise outward.State machine 22 Enable Pin and reset terminal receive enable signal EN from digital baseband processor and reset signal RES, the reset signal that the count completion signal that state machine 22 also receives detection signal that the falling edge detectors 211 from numerical frequency comparator 21 exports, rising edge counter 212 exports, reset unit 213 export, carry out process judgement to received signal, state machine 22 outputs signal to comprise and starts to count and stop the control signal of counting to clock counter 214, and band is led to the reset signal of frequency discriminator.The simultaneously output of comparator is frequency discrimination judgement output signal Y, for as waking output signal up.
Composition graphs 2a and embodiment 1 are described further the logical frequency discriminator technical scheme of band.The digital signal that in Fig. 1 a or Fig. 1 b, comparator 123 exports, the logical frequency discriminator of band is delivered to as input data DATA IN, if the falling edge detectors 211 of numerical frequency comparator 21 detects first rising edge of input data, then export the enabling signal of " starting to detect " to state machine 22, state machine 22 processes the control signal exporting " starting to count ", rising edge counter 212 starts to count input data rising edge, and clock counter 214 starts to count reference clock simultaneously.Meanwhile, input data are delivered to reset unit 213 and are carried out signal decision, if there is discontinuous signal in input data, namely before and after, the interval of pulse exceedes default scope, or when the duty ratio of input data does not meet the demands, reset unit 213 exports high level to state machine, and state machine leads to frequency discriminator to whole band and resets, and restarts the judgement of new round frequency discrimination.If judgement input data signal is continuous, reset unit 213 output low level, then rising edge counter 212 adds 1, reset unit makes signal decision successively, if the count value of rising edge counter 212 does not arrive rising edge counter configuration words P preset value, reset unit 213 exports and maintains low level, and rising edge counter 212 constantly adds 1.When the count value of rising edge counter 212 arrives rising edge counter configuration words P preset value, then reset unit 213 exports high level signal to state machine 22, state machine 22 exports and stops the signal of counting to clock counter 214, in the clock count value that clock counter 214 is sent and the operating frequency that parameters dispensing unit 216 is sent, two preset values that lower limit is corresponding, deliver to comparator 215 together to compare, if count value is in two values, then export the frequency discrimination decision signal Y of high level, Y delivers to enable control gate 217 input as enable signal, control enable storbing gate 217 gating output data DATA OUT and deliver to baseband processor, if count value is not in values, then counter resets, frequency discriminator starts again to adjudicate.The parameters dispensing unit 216 of the embodiment of the present invention according to error precision, the operating rate of working frequency range scope, frequency discrimination, by state machine to frequency discrimination parameter: error precision configuration words ER, lower-frequency limit configuration words DUP, upper frequency limit configuration words DDN and rising edge count limit configuration words P are configured.
For ease of the description to the embodiment course of work, suppose that frequency discrimination parameter configuration is as follows: the reference clock of input is 20KHz and is configured to 80KHz through 4 frequencys multiplication; The bandpass characteristics of the logical frequency discriminator of band is between 8 ~ 22KHz, adjustable by working frequency range scope; Operating rate is adjustable between the rising edge of 4 ~ 15 input data, and error precision configuration words is adjustable between 3 ~ 8 reference clock numbers.State machine 22 pairs of frequency discrimination parameter configuration arrange according to the performance requirement of receiver, and provide error precision configuration words ER by tabling look-up, upper frequency limit configuration words DUP, upper frequency limit configuration words DDN and rising edge counter configuration words P.
Table 1 is speed and the bandpass characteristics allocation list of frequency discrimination.As shown in table 1, the left side first row band passband rate F of table, represent the band passband rate of frequency discrimination, and top the first row C represents rising edge count number set value.Provide the reference clock count number set value under different frequency discrimination band pass frequency value and different rising edge count number set value in table 1, clock count settings are corresponding with frequency discrimination speed, therefrom visible.Frequency range is led to for 13 ~ 15kHz for the band of frequency discriminator, if select rising edge count number set value P to be 6, then the reference clock count number set value of the reference clock 80kHz that the lower frequency limit 13kHz of frequency discriminator is corresponding is 31, and reference clock count number set value corresponding to upper limiting frequency 15kHz is 27, when rising edge counter 212 reaches 6 to input data rising edge count value, clock counter 214 stops counting, if deliver to the reference clock count value of comparator 215 in 27 ~ 31 scopes, then comparator 215 exports high level, the logical frequency discriminator of band exports and wakes control signal Y up, open the transmission circuit on receiver, enable storbing gate 217 is opened simultaneously, input data export, otherwise, comparator output low level, enable storbing gate 217 is closed, input data do not export, the data of the outer interference of filtering band and in-band noise from input data, the logical frequency discriminator of band does not export and wakes control signal up simultaneously, close the transmission circuit on receiver, realize energy-conservation low-power consumption.
The continuity judgment condition allocation list that table 2 resets.As shown in table 2, the first row Fmin is expressed as the lower limit frequency value of the logical frequency discriminator configuration of band, and the 2nd row Cs is expressed as the reference clock numerical value that in the clock cycle, error allows, it is determined by error precision configuration words, the reference clock maximum number value of permissible error when namely one group of continuous data inputs in the clock cycle.Reset unit 213 is mainly added up the continuity and duty ratio that input data and is adjudicated, and the continuity of the rising edge number that reset unit 213 pairs of falling edge detectors 211 export is adjudicated.According to table 1 and table 2, frequency discrimination parameter configuration value and judgement relation are described.Within a clock cycle (with institute's configuration frequency lower limit for the clock cycle), when clock counter 214 count down to the longest counting number 31 corresponding to operating frequency lower limit, when falling edge detectors does not also detect rising edge, show that the data inputted are discontinuous, just send reset signal.
The high level of the input data that reset unit 212 pairs of falling edge detectors 211 are sent and low level number are added up and judge, if within a clock cycle, and the number difference of high and low level exceedes limit value, then the duty ratio of clock cycle interior input data does not meet the demands for this reason, and reset unit 212 exports reset signal.As shown in Table 2, the reference clock maximum number value of the permissible error that lower frequency limit 13kHz is corresponding is 6, if the continuity of the rising edge number that reset unit 213 pairs of falling edge detectors 211 export is adjudicated, if the number difference of high and low level exceeds 6, then export reset signal.
Within a clock cycle, rising edge counter does not reach rising edge count number set value, resets current rising edge count value to reset.
Table 1
Table 2
The band of the present invention the 2nd embodiment leads to frequency discriminator and forms block diagram as shown in Figure 2 b, leads to compared with frequency discriminator forms, omit reset unit, omit and configure count value P to rising edge counter with the band of the first embodiment.It is substantially identical that the course of work that the band of two embodiments leads to frequency discriminator and the band of the first embodiment lead to frequency discriminator, difference is: detection output is sent state machine 22 and rising edge counter 212 by falling edge detectors 211 output, rising edge counter 212 exports rising edge count value and gives state machine 22, rising edge count value is done whether identical judgement with configuration count value P by state machine 22, if judgement is "Yes", state machine 22 exports " stopping counting " signal to rising edge counter 212 and clock counter 214, otherwise continues counting.State machine 22 start counting, stop counting and reset signal, deliver to rising edge counter 212 and clock counter 214 respectively.
Fig. 2 b is the 2nd embodiment that low-power consumption band leads to frequency discriminator, falling edge detectors 211 exports and reset from baseband processor is all directly be connected to state machine, realize warm reset process, rising edge counter is except detecting upper body edge, simultaneously also to the high level part-pulse duration of input data, the time of low level part is added up respectively, when the time that high and low level portions counts exceedes preset value, then to resets, remaining realization is substantially identical with the 1st embodiment, no longer describes in detail.
As shown in Figure 3, state machine has three kinds of states to the state machine state transition diagram of the embodiment of the present invention: idle (IDLE) state 31, counting (COUNTER) state 32 and end (Finish) state 33.
State machine beginning is in IDLE state 31, when falling edge detectors detects first rising edge of input data, state machine receives falling edge detectors and exports beginning detection signal, then proceed to counting COUNTER state 32, if state machine is according to the output signal of reset unit, judgement does not meet reset requirement, and when having input data, remains on COUNTER state 32.
When reset unit meets reset requirement and the rising edge of next input data detected, then restart counting, when counting reaches preset value, then state machine enters Finish state 33.
If the request reset QRES signal that state machine exports according to reset unit, judgement meets reset requirement, and when not inputting data, state machine initiatively proceeds to IDLE state 31 from COUNTER state 32.
When state machine receives digital base band processor chip reset signal RES, also proceed to IDLE state 31 by Finish state 33.
Frequency discrimination method implements band leads to frequency discriminator to adopt the band of the present invention a kind of super low-power consumption to lead to, and its course of work is as shown in Fig. 4 flow process, and composition graphs 2, is described below the workflow of embodiment frequency discriminator:
(1) S401 is when chip powers on or has a RSE reset signal from digital baseband processor, and the state machine being in IDLE state enters (2);
(2) S402 state machine is to band logical frequency discriminator configuration frequency discrimination parameter: according to the requirement of operation of receiver band limits, operating rate, frequency discrimination error precision, operating frequency upper and lower limit settings DUP and DDN is comprised by configuration parameter of tabling look-up, rising edge count number set value P, reference clock count number set value T and error precision settings ER;
(3) S403 detects the rising edge of input data, if input data rising edge detected, turns (4); If input data rising edge do not detected, then continue the rising edge detecting input data;
(4) S404 is when input data first rising edge being detected, and state machine proceeds to COUNTER state 32 from IDLE state 31, and control rising edge counter and clock counter start counting separately, carry out (5) simultaneously;
(5) S405 detects the continuity of square-wave signal or the duty ratio of square wave of input data, if the duty ratio of the continuity of square-wave signal or square wave is undesirable, then turns (6); If the duty ratio of the continuity of square-wave signal or square wave meets the requirements, then turn (7);
(6) S406 reset unit exports reseting request signal to state machine, skips to S403;
(7) if the inspection of S407 reset unit is normal, then rising edge counter adds 1, and enters (8);
(8) S408 judges whether rising edge counter counting reaches preset value, if reach preset value to complete calculating signal to state machine one, enters (9); If rising edge counter does not reach preset value, then skip to (13) S413;
(9) S409 state machine controls clock counter stopping counting, and count value is delivered to comparator, enters (10);
(10) clock counter count value compares with the frequency band upper limit value and lower limit value preset by S410 comparator, if in frequency band upper limit value and lower limit value, turns (12); Otherwise maintain low level output index signal, turn (11);
(11) S411 is by counter resets, and skips to S403;
(12) instruction of S412 frequency discrimination exports high level;
(13) the enable output data of S413, when enable output data are to digital baseband processor, a data transfer is complete, and digital baseband processor exports RES reset signal to the logical frequency discriminator of band, and jump to (1), the band starting newly once to input data leads to frequency discrimination process;
(14) S414 frequency discrimination exports the wake-up signal Y that high level exports as the logical frequency discriminator of band.
Fig. 5 a and Fig. 5 b provides the simulation waveform figure of embodiment of the present invention input data 13KHz and the simulation waveform figure of embodiment of the present invention input data 8KHz.The frequency discrimination scope that the embodiment of the present invention arranges the logical frequency discriminator of band is 10 ~ 20KHz, and the settings P of statistics rising edge number is 7, and clock signal is 20KHz, through 4 frequencys multiplication to the reference clock of 80KHz as clock counter.Input data to 13KHz and 8KHz delivering to the logical frequency discriminator of band and carried out frequency discrimination emulation, its simulation result as shown in figure 5 a and 5b.In figs. 5 a and 5b, the reference clock of the signal indication 80KHz gone up most, Fin represents the signal of input data, and inputting data in Fig. 5 a is that to input data in 13KHz, Fig. 5 b be 8KHz.Y represents the frequency discrimination court verdict of frequency discriminator, and court verdict is high level, and input data are strobed output, export wake-up signal simultaneously, wake receiver chip up.Court verdict is low level is input data not gatings, does not export wake-up signal, continues judgement.RST represents the reset signal from base band.Known by Fig. 5 a, it is 10 ~ 20kHz that the band due to frequency discriminator leads to frequency-selecting scope, therefore wakes output enable signal-Y up, after the rising edge of statistics 7 input data, export high level; After circuit receives reset signal, circuit reset Y also becomes low level, and when condition meets again, after 7 input data rising edges, Y is output enable signal again.In figure 5b, because the data of input are not within the scope of the logical frequency-selecting of band, therefore Y is low level always.
Protection scope of the present invention, is not limited to embodiments described herein.As long as various change to limit and in the spirit and scope of the present invention determined, these changes are apparent, and all examples utilizing the present invention to conceive are all at the row of protection in claims.
Claims (10)
1. the band of super low-power consumption leads to a frequency discriminator, it is characterized in that, the band of the super low-power consumption of modular structure leads to the logical frequency discriminator of frequency discriminator abbreviation band and comprises numerical frequency comparator and state machine; Wherein
Described numerical frequency comparator comprises falling edge detectors, rising edge counter, reset unit, clock counter, comparator, parameters dispensing unit, enable storbing gate; Wherein, an output connect state machine of falling edge detectors, another output of falling edge detectors connects the input of rising edge counter, the input of numerical frequency comparator connects previous stage radio-frequency (RF) front-end circuit output, the output of numerical frequency comparator connects the input of rear stage digital baseband processor, exports the input data from previous stage radio-frequency (RF) front-end circuit output for gating;
Described state machine is be integrated in the microprocessor in the logical frequency discriminator sheet of band, state machine connects enable signal EN from the outer digital baseband processor of sheet and reset signal RES, connects the output signal from the falling edge detectors of numerical frequency comparator, rising edge counter, reset unit simultaneously; The operating state of state machine comprises idle IDLE state, counting COUNTER state, terminates FINISH state, and state machine realizes the conversion of three kinds of operating states according to frequency discrimination work requirements; Enable control end and the reseting controling end of state machine are connected enable control line and the reset control line of rear stage digital baseband processor respectively, the counting of state machine and the counting of reset control line linking number word frequency comparator and reseting controling end, the frequency discrimination parameter configuration end of the frequency discrimination parameter configuration line linking number word frequency comparator of state machine; The logical frequency discriminator output of band, for waking control end up, wakes control signal Y up for exporting one.
2. the logical frequency discriminator of band as claimed in claim 1, is characterized in that,
An output connect state machine of described falling edge detectors, this rising edge detects output and is used for making state machine enter count status, and open corresponding rising edge counter and clock counter counting, the digital control configuration words P of the configuration end connect state machine of falling edge detectors, falling edge detectors also has an output to connect the input of reset unit, the reset terminal of the output connect state machine of reset unit, the input end of clock of clock counter connects reference clock signal, the starting end of clock counter, stop end and reset terminal connect state machine start count, the control signal end stopping counting and reset, the configuration words end connect state machine configuration words ER of parameters dispensing unit, DUP, DDN, parameters configuration for completing the logical frequency discriminator of band controls, an output of parameters dispensing unit connects clock counter, for arranging clock counter counting preset value, another output of parameters dispensing unit connects an input of comparator, for arranging the preset value of comparator, output and the parameters dispensing unit parameter configuration end of clock counter are connected two inputs of comparator respectively, deliver to comparator for the count value of clock counter and the preset value of setting to compare, comparator exports and connects enable storbing gate input, input data are also connected to another input of enable storbing gate, the output high potential of comparator is as enable signal, for controlling enable storbing gate, data strobe will be inputted and export, the output of comparator is also as frequency discrimination index signal simultaneously, for exporting wake-up signal.
3. the logical frequency discriminator of band as claimed in claim 1, is characterized in that: described clock counter comprises the frequency divider, the frequency multiplier sum counter that are sequentially connected in series; Reference clock access frequency divider, frequency division is connected with frequency parameter control end parameters dispensing unit ER configuration end, counter controls end connect state machine start counting, stop counting and reset terminal, counter output connection comparator; Frequency division and the frequency parameter of clock counter arrange end and are connected parameters dispensing unit, the frequency division of clock counter and frequency parameter are configured by parameters dispensing unit ER configuration words, determine that reference clock carries out frequency dividing ratio and times frequency ratio of frequency division, for determining frequency discrimination error precision.
4. the band as described in one of claim 1-3 leads to frequency discriminator, it is characterized in that: described state machine exports the rising edge counter of control signal wire linking number word frequency comparator and the control end of clock counter that start to count, stop counting and reset.
5. the band of super low-power consumption leads to a frequency discrimination method, comprises the following steps:
(1) frequency discrimination parameter is configured by the state machine of the logical frequency discriminator of band;
Be numerical frequency comparator arrangement frequency discrimination parameter by the state machine of the logical frequency discriminator of band, in the memory of state machine, have frequency discrimination parameter configuration table, state machine according to radio-frequency transmitter frequency discrimination requirement, by output one group of frequency discrimination parameter configuration word of tabling look-up; Power on when chip or receive reset signal, one group of frequency discrimination parameter configuration word is configured to numerical frequency comparator;
(2) rising edge of input data is detected;
Detecting the rising edge from the input data of radio-frequency (RF) front-end circuit, when the first rising edge being detected, starting a rising edge counting number, detect each rising edge of input data, count value adds 1; Start to count reference clock signal simultaneously;
(3) detect each rising edge of input data and do to judge to input data;
Detect each rising edge of input data and do to judge to input data, if the rising edge number that falling edge detectors exports is discontinuous, detection determines the discontinuous or duty cycle square wave of square-wave signal not to then sending a count signal again, state machine is done filtering and is resetted, and goes to step (2) and again detects input data rising edge; Then go to step if not (4);
If detect, initial square-wave signal is discontinuous or duty cycle square wave is not right, state machine makes filtering reset processing, make the input signal that square-wave signal is discontinuous or square wave is not right, can not export from the logical phase discriminator of band, realize the bandpass filtering to the noise signal in the interference signal outside band and band;
(4) judge whether rising edge count value reaches settings;
Rising edge count value adds 1, and judges whether rising edge count value reaches settings; If so, state machine exports and stops counting controling signal, and reference clock counter stops counting; Otherwise go to step (2);
(5) reference clock count value is judged whether within working frequency range upper and lower limit respective value scope;
Reference clock count value send comparator, and making comparisons with corresponding frequency discrimination parameter configuration value judges; If within the clock cycle of setting, reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator exports high level; Otherwise output low level, returns step (2);
Within the clock cycle of setting, rising edge count value does not meet parameter setting values, then output low level, wakes receiver up and does not possess wake-up condition;
(6) export high level do the control of enable gating and realize arousal function;
By enable unit, enable control treatment is carried out to comparator output level and input data, when comparator exports high level, selected input data, and export wake-up signal, realize arousal function; Otherwise block input data not export, realize the outer interference of band and in-band noise filtering function;
The logical frequency discriminator of band can make a good job of as wake module and wake controlling functions up, perform not arousal function time, other power consumption module of receiver is in resting state, for obtaining super low-power consumption.
6. the logical frequency discrimination method of band as claimed in claim 5, is characterized in that, step (1) described state machine configuration frequency discrimination parameter comprises following content:
1) working frequency range scope configuration; Modulating data operating frequency is waken up, the operating frequency upper limit value and lower limit value of configuration frequency discriminator according to concrete;
2) the input data length of frequency discrimination is configured; According to the data frame format waking modulating data up of input digital modulation data, configure band leads to the input data length that frequency discriminator receives digital modulation signals;
3) the reference clock number ER of the limits of error is configured; Under the prerequisite not affecting receiving sensitivity, do the configuration of frequency discrimination error precision according to the bit error rate requirement of system;
4) rising edge count number set value P is configured; Under guarantee wakes the prerequisite of the receiver error rate up, namely input data decision length received to operating rate and is configured;
5) scope of configurable clock generator count number set value; According to 1) working frequency range scope configurable clock generator count number set value.
7. the logical frequency discrimination method of band as claimed in claim 5, is characterized in that, the first rising edge and each rising edge of step (2) and (3) described detection input data comprise following control content:
1) falling edge detectors does not detect the rising edge of first input data, and state machine is in idle IDLE state; Counting COUNTER state, end FINISH state;
2) falling edge detectors detects the rising edge of first input data, exports and starts count signal;
3) falling edge detectors detects the rising edge of each input data;
A. falling edge detectors exports and send rising edge counter to a rising edge counting number:
B. reference clock send clock counter to a clock counting number:
4) if falling edge detectors detects that initial square-wave signal is discontinuous or square wave is not right,
A. falling edge detectors exports a signal to reset unit:
B. reset unit exports reseting request signal to state machine;
C. state machine exports reset signal, controls rising edge counter and clock counter clearing, and falling edge detectors restarts to detect input data.
8. the logical frequency discrimination method of band as claimed in claim 5, it is characterized in that, step (4) is described judges whether rising edge counter count value reaches settings and comprise following control content:
1) state machine does not receive rising edge counter and exports count completion signal, judge rising edge counter count value < settings, state machine continues to wait for that rising edge counter exports count completion signal, and rising edge counter continues counting, and clock counter continues counting;
2) state machine receives rising edge counter and exports count completion signal, judges rising edge counter count value >=settings;
3) state machine exports and stops count signal, and rising edge counter stops counting, and clock counter stops counting;
4) clock counter count value is delivered to the comparator reference clock number settings corresponding with the working frequency range upper and lower limit of setting and is made comparisons and judge, if count value is within the scope of working frequency range, then exports high level index signal, and enable output data; Otherwise maintain low level output index signal, and by counter resets, restart falling edge detectors, if rising edge counter does not reach preset value, then go to step (2) and continue counting.
9. method band as claimed in claim 5 leads to frequency discrimination method, and it is characterized in that, step (5) is described judges whether reference clock count value comprises following content within working frequency range upper and lower limit respective value scope:
1) comparator is made comparisons to reference clock count value and corresponding frequency discrimination parameter configuration value and is judged;
2) if within the clock cycle of setting, reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator exports as high level;
3) within the clock cycle of setting, rising edge count value does not meet parameter setting values, and reference clock count value is not within working frequency range upper and lower limit respective value scope, and comparator exports as low level, then do not possess wake-up condition.
10. the band as described in one of claim 5-9 leads to frequency discrimination method, it is characterized in that, step (6) described output high level is made enable gating and controlled and realize arousal function to comprise following content:
1) when comparator exports as high level, control enable storbing gate as enable gating signal and realize being with logical frequency discriminator gated data to export, gated data is transferred to the digital baseband processor of next stage, and gated data once transfers;
2) simultaneously, comparator exports as high level, possesses wake-up condition, and export wake-up signal to receiver, arousal function is used for realizing low-power consumption;
3) next stage digital baseband processor receives the gated data that the logical frequency discriminator of band once transmits, and feedback sends reset signal to frequency discriminator, starts the new frequency discrimination once inputting data and judgement.
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