CN103094470B - Method for forming magnetoresistive element structure - Google Patents
Method for forming magnetoresistive element structure Download PDFInfo
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- CN103094470B CN103094470B CN201210431518.1A CN201210431518A CN103094470B CN 103094470 B CN103094470 B CN 103094470B CN 201210431518 A CN201210431518 A CN 201210431518A CN 103094470 B CN103094470 B CN 103094470B
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- Prior art keywords
- dielectric layer
- magnetoresistive element
- formation method
- groove
- magnetoresistive
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 58
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 210000004027 cell Anatomy 0.000 claims 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 10
- 238000013461 design Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for forming a magnetoresistive element structure, which comprises the following steps: providing a substrate; and forming a metal mosaic structure above the substrate, and forming a patterned magnetic resistance unit above the metal mosaic structure to be electrically connected with the metal mosaic structure. The method for forming the structure of the magneto-resistive element not only can integrate the integrated circuit and the magneto-resistive material to achieve the minimum volume, but also can skillfully combine the aligned mark and the manufacturing process to save the layer number of the photomask.
Description
Technical field
The present invention relates to a kind of magnetoresistive element Structure formation method, particularly a kind of magnetoresistive element Structure formation method that can be applicable in integrated circuit manufacture process.
Background technology
The major function of magnetoresistive element can change its resistance value in response to the change in magnetic field in space, therefore can be widely used on many electronic products, as magnetic-resistance random access memory (MRAM) and magnetic measuring sensor (magnetometer).But magnetoresistive element needs to coordinate peripheral circuit that its function just can be made to give a full play of, and therefore how it to be successfully integrated in integrated circuit manufacture process, and then can to complete in the lump on substrate with peripheral circuit, be always manufacturer target for reaching.But current technological means still has many problems, and how to improve the disappearance of existing means, it is development main purpose of the present invention.
Summary of the invention
The present invention mainly proposes a kind of magnetoresistive element Structure formation method, and graphical magnetoresistive cell and integrated circuit can be combined dexterously through the method, it comprises the following steps: to provide substrate; Form integrated circuit structure layer in this surface, this integrated circuit structure layer can include the component structure of metal connection, logic circuit component, memory element, electrostatic protection element (ESD) and other prior art; Dielectric layer structure is formed above this circuit structure layer; In this dielectric layer structure; This dielectric layer of planarization; At least one groove is formed in this dielectric layer structure; This at least one groove is utilized to form metal damascene structure or as an alignment mark; Magnetoresistance material layer is formed above this dielectric layer structure with this at least one groove; And utilize this alignment mark carry out pattern definition to this magnetoresistance material layer and form magnetoresistive cell.
According to above-mentioned conception, the magnetoresistive element Structure formation method described in this case, not only can combine integrated circuit and magnetoresistive cell, reach volume minimization, and by the mark of aligning and the ingenious combination of processing procedure, can save the number of plies of light shield.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other objects of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 D is the schematic flow sheet of the magnetoresistive element Structure formation method in the embodiment of the present invention.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of magnetoresistive element Structure formation method proposed according to the present invention, method, step, structure, feature and effect, be described in detail as follows.
Refer to Figure 1A to Fig. 1 D, it is the schematic flow sheet of the magnetoresistive element Structure formation method in the embodiment of the present invention, first, there is provided substrate 1 and complete integrated circuit structure 10 in upper, this integrated circuit structure 10 can include the component structure (failing in figure to illustrate) of at least one metal interconnect structure, logic circuit component, memory element, electrostatic protection element (ESD) and other prior art; Wherein this metal interconnect structure can complete setting/replacement (set/reset) and compensate circuit arrangements (failing in figure to illustrate) such as (offset), certainly also metal connection pad 100 can be included in this metal interconnect structure, then above this integrated circuit structure 10, cover a dielectric layer, and this dielectric layer surface is carried out planarization and forms a planarized dielectric layer 101.Further above this planarized dielectric layer 101, be formed with another dielectric layer structure 11, the dielectric layer structure 11 that the three-decker such as formed with silica 110, silicon nitride 111 and silica 112 completes.And metal damascene structure 113 can be formed with in dielectric layer structure 11.It is worth mentioning that, the structure of the dielectric layer structure 11 shown in figure is only an embodiment, and those skilled in the art all can comply with actual Demand Design, and it is single or multiple lift dielectric layer structure.Metal damascene structure 113 mainly provides the follow-up magnetoresistance material completed interstructural electric connection, its formation method is the damascene pattern groove first forming groove-like on dielectric layer structure 11 surface, again metal level be covered in dielectric layer structure 11 surface and fill up this groove, finally utilizing cmp processing procedure that the metal level on dielectric layer structure 11 surface is removed the metal level only stayed in pattern groove.This metal level is preferably tungsten or copper.Owing to all planarization process can be carried out when completing metal damascene structure 113, therefore complete the dielectric layer structure after planarization process 11 all quite smooth with the end face of metal damascene structure 113.But excessively smooth surface by puzzlement when causing follow-up magnetoresistance material layer to carry out graphical processing procedure, and is to improve this problem, in the present embodiment, carries out the following step.
See Figure 1B, on the ad-hoc location mainly in dielectric layer structure 11, light shield micro-photographing process is utilized first to define groove 114a, 114b.One of main purpose of groove structure be can be used to define follow-up micro-photographing process must alignment patterns, therefore can be arranged on the region not affecting element characteristic, such as, groove 114a can be located on Cutting Road region.In addition, groove 114b also can be located at the top of metal connection pad 100, its depth of groove can be set in and only etches away dielectric layer structure partly or etch away the whole dielectric layer of more than metal connection pad, etch downwards again after even etching away the whole dielectric layer of more than metal connection pad, make this depth of groove be greater than the thickness of this dielectric layer structure 11.
Moreover groove structure also can be arranged at (figure does not indicate) in magnetoresistive cell array area, utilizes groove structure to define the magnetoresistive element of particular design.
Again see Figure 1B, then a magnetoresistance material layer 115 can be formed on the surface again in the dielectric layer structure 11 completing fluted 114a, 114b, this magnetoresistance material layer can be single or multiple lift structure, but because of the usual neither printing opacity of magnetoresistance material layer, therefore, originally, after being covered by magnetoresistance material layer with the alignment mark of patterned fashion definition, effectively function cannot be played.But this case groove 114a just can improve this problem, because groove 114a is after inserting magnetoresistance material layer, by the phenomenon causing magnetoresistance material layer surface still to have high low head, the angle of light reflection is changed.Therefore, the shadow lines that exposure bench still can utilize high low head to produce to carry out the aligning of light shield, and then define smoothly magnetoresistive cell 115 ' shape.
As Fig. 1 C shown in, the sidewall of groove 114, when defining magnetoresistive element shape, may leave not the magnetoresistance material clearance wall 115 of etching completely because of the adjustment of process parameter ".And this magnetoresistive cell 115 ' can complete electric connection with metal damascene structure 113.Again this magnetoresistive cell 115 ' shape and position can define with existing photoresistance exposure developing manufacture process, also metal or dielectric layer can be adopted as hard shielding (hard mask), and adopt existing etching technique to remove not by the region that photoresistance or hard shielding cover, form the magnetoresistive cell 115 ' of pattern picture.This magnetoresistive cell 115 ' partly or entirely can be covered in the upper surface of dielectric layer structure 11, need determine according to the Functional Design of this magnetoresistive element.
And then form a protective layer 116 in this magnetoresistive cell 115 ' surface, suffer extraneous pollution or destruction in order to prevent magnetoresistive cell 115 '.And the sandwich construction that this protective layer 116 can utilize low heat budget (low thermal budget) processing procedure to be formed or single-layer silicon nitride silicon have come, such as, with the three-decker that silicon nitride 1160, silica 1161 and silicon nitride 1162 are formed in Fig. 1 D.The groove 114b being now positioned at the top of metal connection pad 100 then can play another effect; namely when metal connection pad 100 will be opened by successive process completely; only need to remove part above metal connection pad 100 and the dielectric layer structure 11 of reduced down in thickness and protective layer 116; just can complete routing opening 117 and expose metal connection pad 100, so can reduce time of etch process and the harmful effect reduced element.In like manner be only an embodiment in the structure of this protective layer 116, those skilled in the art all can according to reality Demand Design its be single or multiple lift protective layer structure.
Can be silicon substrate as the substrate 1 mentioned in above-described embodiment, or be coated with the silicon substrate of the material such as dielectric material or germanium silicide, GaAs, carborundum, and this substrate 1 can complete application-specific IC (ASIC), analog integrated circuit, logical integrated circuit and mixed integrated circuit etc.Can be incorgruous magnetic resistance (Anisotropic Magnetoresistance as magnetoresistive cell 115, AMR), giant magnetoresistance (GiantMagnetoresistance, GMR), tunneling magnetic resistance (Tunneling Magnetoresistance, and the magnetic-resistance random access memory (MRAM) that completes of the magnetic resistance such as huge magneto-resistor (CMR, Colossal Magnetoresistance) mechanism or magnetic measuring sensor (magnetometer) etc. TMR).
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a magnetoresistive element Structure formation method, is characterized in that, comprises the following steps:
Substrate is provided;
Form integrated circuit structure in this surface, comprising:
Form at least one metal interconnect structure in this integrated circuit structure, this metal interconnect structure comprises at least one metal connection pad;
At least one deck planarized dielectric layer is formed above this integrated circuit structure;
Metal damascene structure is formed above this at least one deck planarized dielectric layer;
Above this metal damascene structure, form graphical magnetoresistive cell again, complete electric connection with this metal damascene structure;
Protective layer is formed in this graphical magnetoresistive cell surface; And
This protective layer of remove portion exposes this metal connection pad to form routing opening.
2. magnetoresistive element Structure formation method according to claim 1, is characterized in that, the step forming this graphical magnetoresistive cell above this metal damascene structure is further comprising the steps:
Dielectric layer structure is formed above this at least one deck planarized dielectric layer;
At least one groove is formed in this dielectric layer structure;
Forming magnetoresistance material layer in this dielectric layer structure surface covers this at least one groove; And
Pattern definition is carried out to form magnetoresistive cell to this magnetoresistance material layer.
3. magnetoresistive element Structure formation method according to claim 2, is characterized in that, utilizes this at least one groove to carry out pattern definition as alignment mark to this magnetoresistance material layer.
4. magnetoresistive element Structure formation method according to claim 2, is characterized in that, the step that should form this dielectric layer structure above this at least one deck planarized dielectric layer comprises the following steps:
Form silicon oxide layer;
Silicon nitride layer is formed in this silicon oxide layer surface; And
Another silicon oxide layer is formed again in this silicon nitride layer surface.
5. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprising: form this at least one groove one of in this substrate on Cutting Road region.
6. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprising: form this at least one groove on this metal connection pad.
7. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprising: form this at least one groove one of in this substrate in magnetoresistive element array area.
8. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprising: the upper surface of part in this dielectric layer structure forming this magnetoresistive cell.
9. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprising: form the whole in the upper surface of this dielectric layer structure of this magnetoresistive cell.
10. magnetoresistive element Structure formation method according to claim 2, is characterized in that, comprise further: leave this magnetoresistance material layer in the sidewall of this at least one groove.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100140601A TWI445225B (en) | 2011-11-07 | 2011-11-07 | Method for forming structure of magnetoresistance device |
| TW100140601 | 2011-11-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103094470A CN103094470A (en) | 2013-05-08 |
| CN103094470B true CN103094470B (en) | 2015-04-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201210431518.1A Active CN103094470B (en) | 2011-11-07 | 2012-11-01 | Method for forming magnetoresistive element structure |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US8871529B2 (en) |
| JP (1) | JP2013102161A (en) |
| CN (1) | CN103094470B (en) |
| TW (1) | TWI445225B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104037163B (en) * | 2014-06-05 | 2017-02-15 | 中国电子科技集团公司第十三研究所 | Method for utilizing composite medium conductive film to achieve SiC substrate projection photoetching marking |
| CN105140217B (en) * | 2015-07-27 | 2018-03-02 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of three-dimensional integrated device |
| US10516101B2 (en) * | 2015-07-30 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Physical cleaning with in-situ dielectric encapsulation layer for spintronic device application |
| CN112133822A (en) * | 2019-06-25 | 2020-12-25 | 中电海康集团有限公司 | Self-aligned MRAM bottom electrode preparation method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653549A (en) * | 2002-05-16 | 2005-08-10 | 因芬尼昂技术股份公司 | Method of manufacturing MRAM offset cells in a damascene structure |
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| JPS61248427A (en) * | 1985-04-25 | 1986-11-05 | Nec Corp | Formation of multilayer interconnection |
| JPS6331115A (en) * | 1986-07-24 | 1988-02-09 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6313025B1 (en) * | 1999-08-30 | 2001-11-06 | Agere Systems Guardian Corp. | Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit |
| JP3677455B2 (en) * | 2001-02-13 | 2005-08-03 | Ｎｅｃエレクトロニクス株式会社 | Nonvolatile magnetic storage device and method of manufacturing the same |
| US6682943B2 (en) * | 2001-04-27 | 2004-01-27 | Micron Technology, Inc. | Method for forming minimally spaced MRAM structures |
| US6403461B1 (en) * | 2001-07-25 | 2002-06-11 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce capacitance between metal lines |
| US7723827B2 (en) * | 2002-05-13 | 2010-05-25 | Nec Corporation | Semiconductor storage device and production method therefor |
| US6979526B2 (en) * | 2002-06-03 | 2005-12-27 | Infineon Technologies Ag | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs |
| US6858441B2 (en) * | 2002-09-04 | 2005-02-22 | Infineon Technologies Ag | MRAM MTJ stack to conductive line alignment method |
| KR100923298B1 (en) * | 2003-01-18 | 2009-10-23 | 삼성전자주식회사 | Magnetic RAM comprising unit cell having one transistor and two Magnetic Tunneling Junctions and method for manufacturing the same |
| JP2005142252A (en) * | 2003-11-05 | 2005-06-02 | Sony Corp | Forming method of alignment mark, semiconductor device, and manufacturing method thereof |
| US7223612B2 (en) * | 2004-07-26 | 2007-05-29 | Infineon Technologies Ag | Alignment of MTJ stack to conductive lines in the absence of topography |
| US20060276034A1 (en) | 2005-06-06 | 2006-12-07 | Philippe Blanchard | Forming via contacts in MRAM cells |
| JP2007049066A (en) * | 2005-08-12 | 2007-02-22 | Seiko Epson Corp | Semiconductor wafer as well as semiconductor chip, and method of manufacturing same |
| JP5072012B2 (en) * | 2005-11-14 | 2012-11-14 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP4240044B2 (en) * | 2006-03-22 | 2009-03-18 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| JP5080102B2 (en) * | 2007-02-27 | 2012-11-21 | ルネサスエレクトロニクス株式会社 | Magnetic storage device manufacturing method and magnetic storage device |
| CN102054757B (en) * | 2009-11-10 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of integrated circuit copper interconnection structure |
| JP5483281B2 (en) * | 2010-03-31 | 2014-05-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor device assembly |
-
2011
- 2011-11-07 TW TW100140601A patent/TWI445225B/en active
-
2012
- 2012-03-22 US US13/427,875 patent/US8871529B2/en active Active
- 2012-11-01 CN CN201210431518.1A patent/CN103094470B/en active Active
- 2012-11-06 JP JP2012244695A patent/JP2013102161A/en active Pending
-
2014
- 2014-07-07 US US14/324,617 patent/US20140322828A1/en not_active Abandoned
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1653549A (en) * | 2002-05-16 | 2005-08-10 | 因芬尼昂技术股份公司 | Method of manufacturing MRAM offset cells in a damascene structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI445225B (en) | 2014-07-11 |
| TW201320422A (en) | 2013-05-16 |
| US20130115719A1 (en) | 2013-05-09 |
| US20140322828A1 (en) | 2014-10-30 |
| US8871529B2 (en) | 2014-10-28 |
| JP2013102161A (en) | 2013-05-23 |
| CN103094470A (en) | 2013-05-08 |
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Effective date of registration: 20170718 Address after: 2/ F, Caribbean Plaza, North Tower, 878 West Bay Road, Cayman Islands, Cayman Islands Patentee after: Woo woo Electronics (Cayman) Polytron Technologies Inc Address before: Taiwan Hsinchu County China jhubei City, Taiwan yuan street, six floor of Patentee before: Voltafield Technology Corp. |