CN103078610A

CN103078610A - Delay unit for digital delay chain

Info

Publication number: CN103078610A
Application number: CN2012105800146A
Authority: CN
Inventors: 程旭; 王逵
Original assignee: CHANGZHOU PKUNITY NETWORK COMPUTER Co Ltd; BEIDA ZHONGZHI MICROSYSTEM SCIENCE AND TECHNOLOGY Co Ltd BEIJING
Current assignee: CHANGZHOU PKUNITY NETWORK COMPUTER Co Ltd; BEIDA ZHONGZHI MICROSYSTEM SCIENCE AND TECHNOLOGY Co Ltd BEIJING
Priority date: 2012-12-27
Filing date: 2012-12-27
Publication date: 2013-05-01

Abstract

The invention relates to a delay unit for a digital delay chain. Each delay unit comprises a propagation path and a return path, wherein the propagation path is an inverter, the return path consists of AND-NOT gate, a plurality of delay units are connected in a front-to-back way to form the delay chain, the control signal of the next delay unit in the delay chain can be generated by the control signal of the previous delay unit, the previous delay unit in the delay chain is in a loop-back state, the next delay unit is in a return state, and the signal returns back from the previous delay unit. The delay unit has the advantages that the main delay components of the traditional delay unit, such as the inverter and the multiple choice device, are changed into the inverter and the AND-NOT gates; and since the AND-NOT gates have the advantages of simple structure and small delay in comparison with a multiple-selection device, the delay unit consisting of the inverter and the AND-NOT gates has smaller granularity.

Description

A kind of delay cell for the digital delay chain

Technical field

The present invention relates to integrated circuit, especially a kind of delay cell for the digital delay chain.

Background technology

The digital delay chain generally comprises the delay cell of a plurality of series connection, and the structure of traditional delay cell as shown in Figure 1, is to adopt single control signal to come conducting and the winding of control lag unit.Fig. 2 is a kind of common mutation design of Fig. 1, adopts inverter and multi-selection device to consist of delay cell.But because the complicated structure of multi-selection device, the granularity of the delay of the delay cell that therefore is made of such parts is larger.

Summary of the invention

The technical problem to be solved in the present invention is: propose a kind of less delay cell of granularity that postpones.

The technical solution adopted in the present invention is: a kind of delay cell for the digital delay chain, and described delay cell comprises propagation path and return path, described propagation path and return path are made of inverter and NAND gate.

Specifically, propagation path of the present invention is an inverter; Described return path is made of 3 NAND gate.

Join before and after a plurality of delay cell of the present invention and can consist of delay chain.And the control signal of the delay cell of one-level can be generated by the control signal of previous stage delay cell after in the described delay chain.When previous delay cell in the described delay chain was in loopback status and a rear delay cell and is in return state, signal was turned back at previous delay cell place.

The invention has the beneficial effects as follows: the present invention by inverter and multi-selection device, changes into inverter and NAND gate with the main delay unit of traditional delay cell; Because NAND gate is more simple in structure than the multi-selection device, postpone littlely, so the delay cell granularity that is made of inverter and NAND gate is less.

Description of drawings

The present invention is further described below in conjunction with drawings and Examples.

Fig. 1 is the common structure of delay cell in the prior art;

Fig. 2 is a kind of common mutation of Fig. 1;

Fig. 3 is the structural representation of delay cell of the present invention;

Fig. 4 is the adjustment of a kind of structure of Fig. 3.

Embodiment

The present invention is further detailed explanation with preferred embodiment by reference to the accompanying drawings now.These accompanying drawings are the schematic diagram of simplification, basic structure of the present invention only is described in a schematic way, so it only show the formation relevant with the present invention.

As shown in Figure 3, a kind of delay cell for the digital delay chain, delay cell comprises propagation path and return path, propagation path is an inverter; Return path is made of 3 NAND gate.

When ctrl2 was 0, delay cell was in " conducting " state; When ctrl2 is 1 and ctrl1 when being 0, delay cell is in the state of " returning 1 "; When ctrl2 is 1 and ctrl1 when being 1, delay cell is in " winding " state.When i unit in the delay cell was in " winding " and i+1 unit and is in the state of " returning 1 ", signal was turned back at place, i unit.

Delay cell structure shown in Figure 3 is adjusted, formed a kind of structure as shown in Figure 4, the ctrl2 signal is generated by the ctrl1 signal of previous stage delay cell.And consist of a digital delay chain with joining before and after such delay cell, this delay chain is that 1 delay cell place settling signal is turned back at first ctrl1.

Just the specific embodiment of the present invention of describing in the above specification, various not illustrating is construed as limiting flesh and blood of the present invention, the person of an ordinary skill in the technical field after having read specification can to before described embodiment make an amendment or be out of shape, and do not deviate from essence of an invention and scope.

Claims

1. delay cell that is used for the digital delay chain, it is characterized in that: described delay cell comprises propagation path and return path, described propagation path and return path are made of inverter and NAND gate.

2. a kind of delay cell for the digital delay chain as claimed in claim 1, it is characterized in that: described propagation path is an inverter; Described return path is made of 3 NAND gate.

3. a kind of delay cell for the digital delay chain as claimed in claim 1 is characterized in that: the formation delay chain joins before and after described a plurality of delay cells.

4. a kind of delay cell for the digital delay chain as claimed in claim 3 is characterized in that: the control signal of the delay cell of one-level is generated by the control signal of previous stage delay cell after in the described delay chain.

5. a kind of delay cell for the digital delay chain as claimed in claim 4, it is characterized in that: when previous delay cell was in loopback status and a rear delay cell and is in return state in the described delay chain, signal was turned back at previous delay cell place.