CN103066900B - Based on the pipeline compressor synchronous machine numerical control system of IGCT five Level Technology - Google Patents
Based on the pipeline compressor synchronous machine numerical control system of IGCT five Level Technology Download PDFInfo
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- CN103066900B CN103066900B CN201310002292.8A CN201310002292A CN103066900B CN 103066900 B CN103066900 B CN 103066900B CN 201310002292 A CN201310002292 A CN 201310002292A CN 103066900 B CN103066900 B CN 103066900B
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Abstract
The invention discloses a kind of pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, it comprises master control borad, fibre optic plate, VME bus cabinet and several bottom floor units, wherein said master control borad and described fibre optic plate are inserted on the backboard of described VME bus cabinet, therebetween communication is realized by VME bus, described fibre optic plate and master control borad carry out exchanges data, and data transaction are become the data that described each bottom floor units needs; Described fibre optic plate and described bottom floor units pass through Fiber connection, described fibre optic plate has fiber optic receiver, to receive the data that described bottom floor units sends, described fibre optic plate is defined as described each bottom floor units by the data that the data and described bottom floor units analyzing the transmission of described master control borad send and distributes corresponding data.Instant invention overcomes existing technology extensibility poor, be difficult to reach at a high speed and the defect of high-precision requirement for complex calculation, its control performance meets the requirement of reactive-load compensation equipment.
Description
Technical field
The present invention relates to a kind of driven by power numerical control system, especially, relate to a kind of pipeline compressor synchronous machine numerical control system based on integrated gate commutated thyristor (Intergrated Gate Commutated Thyristors, IGCT) five Level Technology.
Background technology
The basic thought of many level is by multiple level step to synthesize staircase waveform, to approach sine output voltage.Level number is more, and the ladder level step obtained is more, thus more approaches sine wave, and harmonic components is fewer.Theoretically, multi-level converter by the infinite multiple level step of synthesis, can finally realize the output of zero harmonic wave.But in actual applications, owing to being subject to the restriction of hardware condition and control complexity, usually under the prerequisite meeting performance index, do not pursue too high level number.
From current development trend, in oil and gas industry, the full driven by power of pipeline compressor will substitute combustion gas turbine and drive.The high-power compressor of tens of MW needs Large Copacity, high speed alternator driven motor-driven.Five-electrical level inverter (frequency converter) based on IGCT can realize the target of high speed, Large Copacity, efficient, high reliability, smooth output voltage waveform in pipeline compressor electric motor transmission application.Control signal and the feedback signal of traditional inverter control system adopt analog signal transmission usually, and it exists the shortcomings such as the complicated and anti-interference of hardware circuit complexity, debug difficulties, programming is poor.For the five-electrical level inverter control system based on IGCT technology, traditional control system all cannot meet the demands in control precision or response speed.
Summary of the invention
Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, it overcomes the deficiency of existing control system, complex calculation is difficult to reach at a high speed and the defect of high-precision requirement, provides a kind of convenience of programming, respond the numerical control system fast, antijamming capability is strong and precision is high.
For achieving the above object, the invention provides a kind of pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, it comprises master control borad, fibre optic plate, VME bus cabinet and several bottom floor units, wherein said master control borad and described fibre optic plate are inserted on the backboard of described VME bus cabinet, therebetween communication is realized by VME bus, described fibre optic plate and master control borad carry out exchanges data, and data transaction are become the data that described each bottom floor units needs; Described fibre optic plate and described bottom floor units pass through Fiber connection, described fibre optic plate has fiber optic receiver, to receive the data that described bottom floor units sends, described fibre optic plate is defined as described each bottom floor units by the data that the data and described bottom floor units analyzing the transmission of described master control borad send and distributes corresponding data.
According to the above-mentioned pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, wherein, data are sent to described bottom floor units by optical fiber head by described fibre optic plate.
According to the above-mentioned pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, wherein, described master control borad comprises DSP and FPGA, carries out communication by VME bus and other board.
According to the above-mentioned pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, wherein, described fibre optic plate and described bottom floor units swap data adopt two Optical Fiber Transmission, wherein, the transmission of an optical fiber control data, the reception of another root optical fiber control data.
According to the above-mentioned pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, wherein, described bottom floor units forms by from controller, IGCT and DC bus capacitor.
Further, according to the above-mentioned pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, wherein, described from controller by FPGA, fibre optical transmission and receiving circuit, voltage and current testing circuit, A/D convertor circuit, temperature sensing circuit, IGCT drives and fault return circuit and IO drive circuit form, wherein, described voltage and current testing circuit, described A/D convertor circuit, described FPGA drives with described IGCT and is connected successively with fault return circuit, described fibre optical transmission and receiving circuit, described temperature sensing circuit and described IO drive circuit are all connected on described FPGA.
Therefore, pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology of the present invention provides a kind of novel modularized reactive compensation control system based on FPGA, master control borad adopts the framework of DSP+FPGA, carries out communication by VME bus and fibre optic plate.Fibre optic plate and bottom floor units pass through Fiber connection, by optical fiber head, data are sent to bottom floor units, this control system adopts modularization idea, can expand according to actual needs, overcome existing technical deficiency, be difficult to reach at a high speed and the defect of high-precision requirement for complex calculation, control performance meets the requirement of five-electrical level inverter equipment.
Accompanying drawing explanation
Fig. 1 is the structural representation of the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology of the present invention;
Fig. 2 is the structural representation from controller of bottom floor units in the present invention.
Embodiment
Be described further below with reference to the technique effect of accompanying drawing to design of the present invention, concrete structure and generation, to understand object of the present invention, characteristic sum effect fully.
As shown in Figure 1, according to the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology of the present invention, it comprises master control borad 1, fibre optic plate 2, VME bus cabinet 3 and several bottom floor units 4.Wherein master control borad 1 and fibre optic plate 2 are inserted on VME bus cabinet 3 backboard, and the two realizes communication by VME bus.Fibre optic plate 2 and master control borad 1 carry out exchanges data, and data transaction are become the data that each bottom floor units 4 needs; Data by Fiber connection, and are sent to bottom floor units by optical fiber head by fibre optic plate 2 and bottom floor units 4, and fibre optic plate 2 adopts the fiber optic receiver with optical fiber receiving function simultaneously, to receive the data that bottom floor units 4 sends.Fibre optic plate 2 is defined as each bottom floor units by the data that the data and bottom floor units 4 analyzing master control borad 1 transmission send and distributes corresponding data.
Master control borad 1 adopts the framework of DSP+FPGA, carries out communication by VME bus and other board.The algorithm of the DSP completion system in master control borad 1, with FPGA exchanges data, with the function such as upper machine communication; FPGA mainly complete pulse distribution, with the function such as the protection of DSP exchanges data and system.In master control borad 1, place memory, it as the buffer of exchanges data, can also deposit significant data when data volume is larger.DSP and FPGA works in coordination, and master control borad 1 completes the functions such as top layer algorithm, the protection of system, the control of submodule and protection.Master control borad 1 is after receiving the voltage of line voltage, electric current and each bottom floor units, current signal, the set-point of computing system, by the fibre optic plate 2 in control system, signal is sent in bottom floor units 4, after bottom floor units 4 receives signal, bottom floor units 4 balanced voltage from controller and export corresponding response current.The fpga chip that master control borad 1 adopts calculation function stronger, embeds several soft core in fpga chip, can computing complicated algorithm and with bottom floor units swap data.Master control borad 1 after completing algorithm, by the data calculated by fibre optic plate pass in bottom floor units 4 from controller.Fibre optic plate 2 and bottom floor units 4 swap data adopt two Optical Fiber Transmission, the transmission of an optical fiber control data, the reception of an optical fiber control data.
The mode that fibre optic plate 2 adopts FPGA to control, by VME bus and other board communication.FPGA in fibre optic plate 2 mainly completes the exchanges data between master control borad 1, and data transaction is become the data that each bottom floor units needs, by optical fiber head, data are sent to bottom floor units 4, fibre optic plate 2 has optical fiber reception facilities simultaneously, can receive the data that bottom floor units 4 sends, the data sent by the data and bottom floor units 4 analyzing master control borad 1 transmission are defined as each bottom floor units and distribute corresponding data.
VME bus cabinet 3 adopts VME bus protocol, and in VME communications protocol, the transmission means of data adopts parallel transmission, effectively ensure that the speed of transmission, adopts multiple control line to guarantee real-time and the accuracy of transmission data in VME communications protocol.The realization of VME bus protocol adopts the connected mode of backboard.
Bottom floor units 4 forms by from controller, IGCT and DC bus capacitor.Bottom floor units 4 mainly completes the control command that master control borad 1 sends.Wherein adopt FPGA and master control borad 1 swap data from controller 5, thus reach the object accurately controlling reactive power compensator.Bottom floor units 4 is the minimum step exporting sinusoidal voltage waveform, must contain protective circuit simultaneously, automatically can excise bottom floor units when capacitance short-circuit or the open circuit of bottom floor units 4 in bottom floor units 4, the normal operation of protection whole system.
As shown in Figure 2, being made up of FPGA6, fibre optical transmission and receiving circuit 7, voltage and current testing circuit 8, A/D convertor circuit 9, temperature sensing circuit 10, IGCT driving and fault return circuit 11 and IO drive circuit 12 from controller 5 in bottom floor units 4.Wherein, voltage and current testing circuit 8, A/D convertor circuit 9, FPGA6 with IGCT drive and are connected successively with fault return circuit 11, and fibre optical transmission and receiving circuit 7, temperature sensing circuit 10 and IO drive circuit are all connected on FPGA6.Fibre optical transmission and receiving circuit 7 are for receiving the data of master control borad 1 transmission and sending from the data after controller 5 collection and computing.A/D convertor circuit 9 gathers the direct voltage of DC bus capacitor in each bottom floor units 4.Temperature sensing circuit 10 gathers the temperature of IGCT, for the excision drive singal when IGCT excess temperature.IGCT drive and fault return circuit 11 for driving the turn-on and turn-off of IGCT and receiving the fault-signal of IGCT.IO drive circuit 12 controls the thyristor of bottom module.Bottom floor units 4 from controller 5 mainly complete the control of bottom IGCT module switch, submodule protection, detect and magnitude of voltage control capacitance, complete the interface with fibre optic plate 2 simultaneously.Need control IGCT conducting, the adhesive of control by-pass switch from controller 5, control thyristor, Detection capacitance voltage, detect IGCT temperature, IGCT overcurrent, overvoltage protection, complete and master control borad 1 communication simultaneously.
Novel modularized reactive compensation control system based on FPGA of the present invention, master control borad 1 adopts the framework of DSP+FPGA, carries out communication by VME bus and fibre optic plate 2.Fibre optic plate 2 and bottom floor units 4 pass through Fiber connection, by optical fiber head, data are sent to bottom floor units 4, this control system adopts modularization idea, can expand according to actual needs, overcome existing technology extensibility poor, be difficult to reach at a high speed and the defect of high-precision requirement for complex calculation, control performance meets the requirement of five-electrical level inverter equipment.
More than describe preferred embodiment of the present invention in detail.Should be appreciated that the ordinary skill of this area just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all technical staff in the art, all should by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (4)
1. the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology, it is characterized in that, comprise master control borad, fibre optic plate, VME bus cabinet and several bottom floor units, wherein said master control borad and described fibre optic plate are inserted on the backboard of described VME bus cabinet, therebetween communication is realized by VME bus, FPGA in described fibre optic plate and master control borad carry out exchanges data, and data data transaction being become each bottom floor units to need, by optical fiber head, data are sent to described bottom floor units; Described fibre optic plate and described bottom floor units pass through Fiber connection, described fibre optic plate has fiber optic receiver, to receive the data that described bottom floor units sends, described fibre optic plate is defined as each bottom floor units by the data that the data and described bottom floor units analyzing the transmission of described master control borad send and distributes corresponding data;
Described bottom floor units forms by from controller, IGCT and DC bus capacitor; Described from controller by FPGA, fibre optical transmission and receiving circuit, voltage and current testing circuit, A/D convertor circuit, temperature sensing circuit, IGCT drives and fault return circuit and IO drive circuit form.
2. the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology according to claim 1, it is characterized in that, described master control borad comprises DSP and FPGA, carries out communication by VME bus and other board.
3. the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology according to claim 1, it is characterized in that, described fibre optic plate and described bottom floor units swap data adopt two Optical Fiber Transmission, wherein, the transmission of an optical fiber control data, the reception of another root optical fiber control data.
4. the pipeline compressor synchronous machine numerical control system based on IGCT five Level Technology according to claim 1, it is characterized in that, described from controller, described voltage and current testing circuit, described A/D convertor circuit, described FPGA and described IGCT drive and are connected successively with fault return circuit, and described fibre optical transmission and receiving circuit, described temperature sensing circuit and described IO drive circuit are all connected on described FPGA.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0566297A1 (en) * | 1992-04-13 | 1993-10-20 | SMITH & NEPHEW DYONICS INC | Brushless motor control system |
CN101620428A (en) * | 2009-07-28 | 2010-01-06 | 中国科学院电工研究所 | VME bus motor controller based on FPGA chip |
CN102270842A (en) * | 2010-06-01 | 2011-12-07 | 上海电气集团股份有限公司 | Active power filter control system based on digital signal processing (DSP) chip and field programmable gate array (FPGA) chip |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0566297A1 (en) * | 1992-04-13 | 1993-10-20 | SMITH & NEPHEW DYONICS INC | Brushless motor control system |
CN101620428A (en) * | 2009-07-28 | 2010-01-06 | 中国科学院电工研究所 | VME bus motor controller based on FPGA chip |
CN102270842A (en) * | 2010-06-01 | 2011-12-07 | 上海电气集团股份有限公司 | Active power filter control system based on digital signal processing (DSP) chip and field programmable gate array (FPGA) chip |
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