CN206595719U - A kind of photovoltaic parallel in system based on FPGA - Google Patents
A kind of photovoltaic parallel in system based on FPGA Download PDFInfo
- Publication number
- CN206595719U CN206595719U CN201621012771.3U CN201621012771U CN206595719U CN 206595719 U CN206595719 U CN 206595719U CN 201621012771 U CN201621012771 U CN 201621012771U CN 206595719 U CN206595719 U CN 206595719U
- Authority
- CN
- China
- Prior art keywords
- voltage
- core
- fpga
- photovoltaic
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02A—TECHNOLOGIES FOR ADAPTATION TO CLIMATE CHANGE
- Y02A30/00—Adapting or protecting infrastructure or their operation
- Y02A30/60—Planning or developing urban green infrastructure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
Abstract
The utility model discloses a kind of photovoltaic parallel in system based on FPGA, system includes following device：Photovoltaic cell PV, electric capacity of voltage regulation, DC/DC translation circuits, dc bus, DC/AC full-bridge inverters, core controller FPGA, AC network and power supply unit.Wherein, core controller FPGA uses heterogeneous dual-core pattern, and core 1 produces prime DC/DC translation circuits, the PWM drive signal of rear class DC/AC full-bridge inverters and MPPT maximum power point tracking MPPT control signals；Core 0 carries linux system and carrys out the functions such as operational network service, database and remote monitoring.Heterogeneous dual-core FPGA parallel processable tasks, realize the flexible combination of difference in functionality；Dinuclear Systems are easy to expand, and powerful process performance can be incorporated in compact profile, and the heat low in energy consumption, calculating power consumption generation used in this profile is few.The SPWM controls of inverter are main to use voltage and current double closed-loop active control, and this method strong robustness, control speed is fast, and inverter output voltage and power network reference voltage are basically identical.
Description
Technical field
The utility model is related to field of new energy technologies, more particularly to a kind of photovoltaic parallel in system based on FPGA.
Background technology
With the quick consumption of the global reserves energy, the supply of the traditional energy such as coal, oil, natural gas is more tight
, in order to alleviate energy and environment crisis, the exploitation of a regenerative resource such as wind energy, solar energy are paid high attention to.
Nearly ten years, solar photovoltaic industry is developed rapidly, and photovoltaic installation total amount is in explosive increase trend in the world.
Only in 2015, photovoltaic generation installation total capacity reaches 21,000,000 kilowatts, and annual electricity generating capacity is up to 25,000,000,000 kilowatt hours.Photovoltaic industry is
Into new developing period, by the important component as later power source.
A series of simultaneously adjoint grid-connected problems are also shown especially further, if photovoltaic parallel in system is to the power network quality of power supply
The problems such as influence problem, the control problem of inverter, low voltage crossing.Photovoltaic power generation grid-connecting system due to its generate electricity it is discontinuous
Property and randomness, system output is unstable, and input line voltage produces fluctuation, so as to produce a series of quality of power supply sides to power network
The influence in face.Power electronic equipment in grid-connected system, such as DC/DC translation circuits, inverter are realizing voltage x current processing
While, harmonic current can be produced, voltage waveform is produced distortion.The control problem of inverter be ensure output voltage with
While the same frequency of line voltage is with phase, effectively control output current simultaneously reduces influence of the harmonic wave to power network.When line voltage occurs
During bust, the stability of power distribution network will be had a strong impact on, so as to influence the normal operation of power network.In order to improve solar energy to greatest extent
Utilization rate, realizes the safe and effective grid-connected of photovoltaic generation, and the photovoltaic parallel in system for studying real-time high-efficiency is imperative.
For current photovoltaic parallel in system, the domestic function control to photovoltaic parallel in system mostly using single-chip microcomputer,
The serial structure controller such as digital signal processor DSP or integrated circuit ASIC, its speed of service and scalability need to be carried
It is high.Programmable logic array FPGA based on parallel organization computing is capable of the unit module of self-defined difference in functionality, with integrated
The features such as degree height, flexible resource allocation and strong autgmentability, good hardware foundation is provided for photovoltaic parallel in system.
Utility model content
The purpose of this utility model is to overcome photovoltaic parallel in system the deficiencies in the prior art to be based on FPGA there is provided one kind
Photovoltaic parallel in system, using heterogeneous dual-core FPGA as core controller, can be achieved difference in functionality flexible combination, improve system
Control performance, is mainly adopted the following technical scheme that：
A kind of photovoltaic parallel in system based on FPGA, including following device：Photovoltaic cell PV, electric capacity of voltage regulation, DC/DC become
Change circuit, dc bus, DC/AC full-bridge inverters, core controller FPGA, AC network and power supply unit etc..Photovoltaic electric
Pond output is in parallel with electric capacity of voltage regulation, and electric capacity output series filtering inductance L1 is in parallel with DC/DC translation circuits again, DC/DC conversion electricity
Road output is in parallel with electric capacity of voltage regulation through single-phase diode, then connects DC/AC full-bridge inverters, inverter output string through dc bus
Connection filter inductance L2 is connected in parallel to AC network through electric capacity of voltage regulation again.Core controller FPGA then gathers the output electricity of photovoltaic cell
Pressure and current information, the output voltage information of DC/DC translation circuits and system output voltage, current information, by self-defined
Driving and control module produce required signal to grid-connected system.
PV parts in the photovoltaic generation use MPPT maximum power point tracking control strategy, pass through core controller FPGA
The customized MPPT functional modules of core 1, follow the internal resistance of cell to adjust the load resistance in photovoltaic cell equivalent model so that
Realize that maximum power of photovoltaic cell is exported.The photovoltaic cell equivalent model is by equivalent current source Iph, forward diode Id, electric capacity
Cj, PN junction by-pass shunt resistance Rsh, series resistance RsWith load RLDeng composition.Battery model is simple in construction, and internal resistance is that circuit is defeated
Go out impedance.
The DC/DC translation circuits use boost boost conversion circuits, and the electric energy that photovoltaic inversion is produced is carried out at boosting
Reason, so as to reduce energy consumption when it is transmitted on dc bus.
The DC/AC full-bridge inverters select the single-phase full bridge inverter circuit of H bridge topological structures, and wherein power switch pipe is
Voltage driven type MOSFET is managed, model IRF3710, maximum voltage 500V, maximum current 57A.According to SPWM sinusoidal pulse width modulations
Its drive circuit of Technology design, and add light-coupled isolation in the design.Isolation circuit uses binary channels HCPL-2630 chips
Realize that voltage is isolated, driving chip uses special chip IR2410, it has binary channels, driving force is strong, and high pressure can be driven high
The voltage driven type switching tube of speed.
The core controller FPGA selects the Zynq-7000 models of heterogeneous dual-core.In FPGA, systemic-function realizes master
To include three layers：Hardware layer, system layer and application layer.In FPGA, core 1 realizes the relevant control of photovoltaic parallel in system, main complete
Into MPPT, SPWM, CAP and ADC scheduling algorithm programming, the transplanting linux system of core 0 realizes that photovoltaic is monitored, while dinuclear also may be used
To carry out real time data interaction.Wherein the realization of hardware is mainly set including FPGA ZedBorad development boards, FPGA SD card circuits
Meter, the design of FPGA UART circuitries, full bridge inverter design, drive circuit design, sample circuit design, Zero-cross comparator circuit
Design, auxiliary power circuit design, the design of grid-connected on-off circuit, protecting circuit designed etc..
The software of the core controller FPGA centers 1 realizes overall architecture：Including realizing to SPWM modules, CAP captures
The design of module and MPPT modules etc., and to journeys such as frequency-tracking, Phase Tracking, ADC samplings, isolated island detection and MPPT algorithms
Sequence is designed.Wherein, customed multiple FPGA IP kernel, such as under Matlab, with reference to DDS and sliding mode technology, generation
Only the frequency and reference phase of SPWM modules need to be changed in the IP kernel of SPWM modules, program, you can flexibly realize SPWM ripples
Real-time update.SPWM controls are main to use voltage and current double closed-loop sliding mode control strategy, and this method can make inverter output voltage
Quick tracking power network given voltage.The capture logic of CAP signals has been write simultaneously, generates the IP kernel of CAP trapping modules, customization
The register such as mains frequency, phase and the reverse frequency of CAP modules, phase.The frequency and Phase Tracking are real by phaselocked loop
It is existing.Phaselocked loop is a closed-loop control system, and it is carried out from motion tracking by detecting the frequency and phase of line voltage in real time,
Make the frequency and phase and line voltage of inverter output current basically identical, its control accuracy directly affect photovoltaic system and
Net performance.
The utility model has the advantage of：
1st, heterogeneous dual-core FPGA parallel processable tasks, realize the flexible combination of difference in functionality.
2nd, Dinuclear Systems are easy to expand, and can incorporate powerful process performance in compact profile, used in this profile
Heat that is low in energy consumption, calculating power consumption generation is few.
3rd, the SPWM controls of inverter are main uses voltage and current double closed-loop active control, should compared with conventional PI control
Method strong robustness, control speed is fast, and inverter output voltage and power network reference voltage are basically identical.
The technique effect of design of the present utility model, concrete structure and generation is made furtherly below with reference to accompanying drawing
It is bright, to be fully understood from the purpose of this utility model, feature and effect.
Brief description of the drawings
Fig. 1 is photovoltaic parallel in system structure chart of the present utility model；
Fig. 2 is the equivalent model of photovoltaic cell of the present utility model；
Fig. 3 is double-core FPGA system functional block diagram of the present utility model；
Fig. 4 is inverter circuit figure of the present utility model；
Fig. 5 is the main program flow chart of core 1 of the present utility model；
Fig. 6 is inverter SPWM control structure figures of the present utility model；
Fig. 7 is phase-locked loop structures figure of the present utility model；
Fig. 8 is prime sample circuit of the present utility model；
Fig. 9 is the grid-connected on-off circuit of relay of the present utility model；
Figure 10 is the main program functional block diagram of core 1 of the present utility model；
Figure 11 is SPWM module frame charts of the present utility model；
Figure 12 is that CAP of the present utility model captures flow chart；
Figure 13 is MPPT program flow diagrams of the present utility model；
Figure 14 is AD of the present utility model sampling flow charts；
Figure 15 is isolated island program flow diagram of the present utility model；
Figure 16 is double-core Principle of Communication block diagram of the present utility model.
Embodiment
The utility model is described in further detail with specific embodiment below in conjunction with the accompanying drawings.
A kind of photovoltaic parallel in system based on FPGA, it ties as shown in Figure 1.System mainly includes following device：Photovoltaic electric
Pond PV, electric capacity of voltage regulation, DC/DC translation circuits, dc bus, DC/AC full-bridge inverters, core controller FPGA, AC network
And power supply unit etc..Photovoltaic cell output is in parallel with electric capacity of voltage regulation, and electric capacity output series filtering inductance L1 becomes with DC/DC again
Circuit in parallel is changed, the output of DC/DC translation circuits is in parallel with electric capacity of voltage regulation through single-phase diode, then connects DC/AC through dc bus
Full-bridge inverter, inverter output series filtering inductance L2 is connected in parallel to AC network through electric capacity of voltage regulation again.Core controller FPGA
Then the output voltage and current information of collection photovoltaic cell, the output voltage information of DC/DC translation circuits and system output are electric
Pressure, current information, the signal needed for being produced by self-defined driving and control module is to grid-connected system.
PV parts in photovoltaic generation use MPPT maximum power point tracking control strategy, pass through core controller FPGA core 1
Customized MPPT functional modules, follow the internal resistance of cell, so as to realize to adjust the load resistance in photovoltaic cell equivalent model
Maximum power of photovoltaic cell is exported.Photovoltaic cell equivalent model is by equivalent current source Iph, forward diode Id, electric capacity Cj, PN junction
By-pass shunt resistance Rsh, series resistance RsWith load RLDeng composition, its circuit structure is as shown in Figure 2.Battery model is simple in construction,
Internal resistance is circuit output impedance.
Core controller FPGA selects the Zynq-7000 models of heterogeneous dual-core.In FPGA, systemic-function realizes main bag
Include three layers：Hardware layer, system layer and application layer, its functional block diagram are as shown in Figure 3.In FPGA, core 1 realizes photovoltaic parallel in system
Relevant control, mainly completes MPPT, SPWM, CAP and ADC scheduling algorithm programming, and the transplanting linux system of core 0 realizes photovoltaic
Monitoring, while dinuclear can also carry out real time data interaction.Wherein the realization of hardware mainly includes FPGA ZedBorad exploitations
Plate, FPGA SD cards circuit design, the design of FPGA UART circuitries, full bridge inverter design, drive circuit design, sample circuit
Design, the design of Zero-cross comparator circuit design, auxiliary power circuit, the design of grid-connected on-off circuit, protecting circuit designed etc..
DC/DC translation circuits use boost boost conversion circuits, and boosting processing is carried out to the electric energy that photovoltaic inversion is produced,
So as to reduce energy consumption when it is transmitted on dc bus.The single-phase full bridge of DC/AC full-bridge inverters selection H bridge topological structures is inverse
Become circuit, its circuit structure is as shown in Figure 4.Wherein power switch pipe is managed for voltage driven type MOSFET, model IRF3710, most
Big voltage 500V, maximum current 57A, IRF3710 driving design is simple, break-make switching is fast, conducting resistance is small, switching loss
It is low, so as to improve overall inversion efficiency.
Inverter driving circuit is the key component of whole inverter circuit, and its structure is based on SPWM SPWM Techniques
Design, and light-coupled isolation is added in the design.Its operation principle is：When four road SPWM ripples outputs are after two panels light-coupled isolation,
Two panels special driving chip is input to, output sends into inverter bridge device for power switching with the strong SPWM ripples of driving force.Using double
Passage HCPL-2630 chips realize that voltage is isolated, and driving chip uses high performance special chip IR2410, its band binary channels,
Driving force is strong, can drive the voltage driven type switching tube of high-voltage high-speed.
The Software for Design of FPGA centers 1 mainly includes realizing setting to SPWM modules, CAP trapping modules and MPPT modules etc.
Meter, and the programs such as frequency-tracking, Phase Tracking, ADC samplings and MPPT algorithm are designed.Wherein, it is customed multiple
FPGA IP kernel, such as under Matlab, with reference to DDS and sliding mode technology, generating only needs change in the IP kernel of SPWM modules, program
The frequency and reference phase of SPWM modules, you can flexibly realize the real-time update of SPWM ripples.SPWM controls mainly use voltage
Current double closed-loop sliding mode control strategy, this method can make inverter output voltage quickly track power network given voltage.Write simultaneously
The capture logic of CAP signals, generates the IP cores of CAP trapping modules, has customized mains frequency, phase and the inversion of CAP modules
The registers such as frequency, phase, the main program flow of core 1 is as shown in Figure 5.The frequency and Phase Tracking are realized by phaselocked loop.Lock
Phase ring is a closed-loop control system, and it carries out from motion tracking by detecting the frequency and phase of line voltage in real time, make inversion
The frequency and phase and line voltage of device output current are basically identical, and its control accuracy directly affects the grid-connected property of photovoltaic system
Energy.
The SPWM controls of wherein inverter are main to use voltage and current double closed-loop active control, its control structure such as Fig. 6 institutes
Show.Accurate grid-connected voltage is obtained, accurate inverter switching device signal is needed.In order to improve grid-connected performance, the utility model is adopted
Active sliding-mode control is used, control is tracked by power network reference value to inverter output voltage electric current.Controller is used and opened
Close the form that switching function and feedback are combined, it is assumed that line voltage, current reference value and actual output voltage, current deviation eu
=uref-uo, ei=iref(uu)-io.Define sliding surface su=eu, si=ei, then voltage x current two-stage sliding mode controller is using this
Form uu=-ρusgn(eu)-kueu, ui=-ρisgn(ei)-kiei, wherein ρu, ku, ρi, kiIt is the constant more than zero.With tradition
PI controls compare, this method strong robustness, control speed is fast, and inverter output voltage and power network reference voltage are basically identical.
Fig. 7 is phase-locked loop structures figure of the present utility model.As seen from the figure, phaselocked loop is mainly by digital phase discriminator PD, loop
The part such as wave filter LF and digital vco DCO constitutes degeneration factor, and digital phase discriminator detects input signal and anti-
The phase difference of feedback signal, the phase of output signal is adjusted with this so that output signal accurately tracks the frequency and phase of input signal
Position.Sample mains frequency, be compared through frequency multiplication with feedback frequency, digital phase discriminator frequency and phase discrimination obtains deviation voltage first,
Mains frequency and tracking lock mains frequency are obtained by digital vco DCO again, the frequency is used as inverter modulating wave
Frequency, modulating wave and triangle wave obtain switching tube trigger pulse, so that the conducting of controlling switch pipe so that inversion is exported
Voltage it is consistent with the frequency and phase of line voltage.
Zedboard includes double-core Cortex-A9 processors, and each processor is complete ARM subsystems, and each
Processor subsystem Memory Controller Hub and a large amount of peripheral hardwares all in Embedded, such ARM cores can work independently, can also combine
Programmable logic cells PL is same in FPGA develops design.There is a USB to turn UART serial ports on Zedboard development boards, install
After Cypress USB-UART driving, it is that USB can be achieved to turn UART serial communications to access corresponding port numbers.Using
The CY7C64225 controllers of Cypress companies turn UART serial ports schemes, chip integration there is provided a very simple and effective USB
Controlled into various functions such as USB2.0 controllers, UART transceivers, crystal oscillator and EEPROM, and using the Uart of USB interface
Device processed is easy to use, and plug and play is without USB adapters.
Sample circuit is designed to multi-functional sampling configuration, changeable survey electric current or the pattern for surveying voltage, connects corresponding pipe
Pin short circuit cap can switch mode.Sample circuit needs voltage or electric current, the voltage or electric current of dc bus to photovoltaic cell
Sampled respectively with output voltage and electric current etc..Wherein voltage or current signal by front stage circuits handle, then by every
High voltage or high current are converted into weak voltage signal from sample circuit, voltage signal is transferred to by linear optical coupling isolation
The XADC ends of fpga chip, prime sample circuit is as shown in Figure 8.Linear optical coupling circuit prevents overcurrent from burning mainly for isolation
Ruin XADC sampling end.
When inverter current tracks line voltage, i.e., when the same frequency of inverter current and line voltage is with phase, FPGA hairs
Go out control signal to grid-connected on-off circuit, now relay adhesive, inverter output access public network.Model is included in this circuit
TLP521.2 isolation optocoupler, relay model HK3FF-DC5V-SH.The grid-connected on-off circuit of relay is as shown in Fig. 9.
The programming of whole system mainly includes main program and interruption subroutine.Main program mainly has：System frequency with
The programming such as display in real time of track, Phase Tracking programming, SPWM programmings, double intercore communications and liquid crystal.Interrupt service
Subprogram mainly has：Timer interruption MPPT programs, ADC interrupt routines, CAP capture interrupt routines and protection interrupt routine etc..
The main program functional block diagram of FPGA core 1 is as shown in Figure 10.
SPWM ripples module uses the System Generator instruments in Xilinx Design Tools, in Matlab
Complete design and emulation, generate the IP kernel of SPWM modules, and add in Vivado engineerings.In generation SPWM wave processes, with reference to
Advanced direct digital synthesizer DDS technology, is aided with corresponding hardware and software platform, can generate as triangular wave, sine wave and
The multiple waveforms such as square wave.According to SPWM generation principle, SPWM circuits mainly have：Sine wave module, carrier module, comparison module
With dead band module etc., its structure is as shown in figure 11.
Add IP kernel in Vivado engineering design source files, system automatically generate it is general, example, be not added with user
Three files of logic, and be all the source file write with Verilog HDL, it is design top document cap_ip_ respectively
V1_0, bus signals logical file cap_ip_v1_0_S00_AXI_inst and bus signals interrupt file cap_ip_v1_
0_S00_AXI_INTR_inst.In view of the portability of CAP_IP cores, when Verilog hdl files are write here, if
Put the functions such as interruption enable, number of interrupts, data bit, address width and triggering interrupt mechanism.When CAP trapping module Document Editings
After the completion of, then IP kernel is encapsulated into by all steps of IP Packaging Steps.After IP kernel is generated, in engineering
The IP kernel path specified is added into the storehouse of engineering, you can CAP modules are added in Vivado engineerings.
In the CAP of generation IP kernel increase newly 5 registers, be respectively trapped state register, capture mains frequency and
The register of the register of phase, capture inverter frequency and phase.When capture signal changes, CAP is to corresponding letter
Number judged, and whether compare power network that CAP captures obtain and inverter frequency, phase into corresponding interrupt handling routine
Unanimously, if inconsistent, the frequency word and phase word of SPWM modules is adjusted, is then compared again, so circulation.Using first frequency with
The mode of track Phase Tracking again, until output current and line voltage are completely with the same phase of frequency, CAP capture flow chart such as Figure 12 institutes
Show.
The system realizes that maximum power of photovoltaic cell point is tracked in timer interruption, using variable step conductance increment method,
Photovoltaic cell reference voltage and virtual voltage sampled value deviation are obtained in timer interrupt program, is changed by MPPT algorithm
The dutycycle of PWM ripples, so as to realize the control of photovoltaic array MPPT algorithm in closed-loop control Boost circuit.MPPT
Program flow diagram is as shown in figure 13.
In closed-loop system, A/D module plays feedback effect, and the output result to system is corrected in real time.In FPGA
Double 12 1Msps digital analog converters are put, at most receive 17 pairs of difference analogue inputs.A/D samplings are main to complete voltage and current thing
Reason amount is sampled：It is defeated including line voltage and electric current, contravarianter voltage and electric current, DC bus-bar voltage and electric current and photovoltaic cell
Voltage and current gone out etc..AD sampling flow charts are as shown in figure 14.FPGA obtains to numeral being believed by analog signal by AD samplings
Number data, due to there is the inaccurate of interference and reference source, removed and disturbed using digital filtering algorithm, make result closer to true
Real value.
The utility model also provides isolated island detection module simultaneously.Conventional isolated island detection mode has active and passive type,
It is active often to have frequency deviation method, phase shift method and impedance measurement etc..Passive type often has voltage detecting method, mains by harmonics to survey
The method such as amount and Phase jump detection.The system using actively by the way of being passively combined, selected frequency deflection method and voltage
The method that detection method is combined, such a method can carry out effective detection to island effect.
When island effect occurs for system, voltage and frequency can all change, therefore using active frequency disturbance plus real-time
The method of voltage detecting, is more than positive and negative 5% to the frequency error detected, and rated voltage exceeds between -10% to+7%,
I.e. system can assert occurred island effect.Isolated island protection flow chart is as shown in figure 15.
The system includes multiple peripheral modules, except existing module in storehouse, also comprising self-defined peripheral module.Wherein,
Processing_system7_0 is that Zynq core processors, xadc_wiz_0 are ADC sampling modules, rst_processing_
Sysytem7_0_100M is that system clock module, guangfu_system_0 are that self-defined SPWM ripples module, cap_ip_0 are
Self-defined trapping module, pwm_ip be self-defined pwm generation modules, axi_gpio_0~axi_gpio_4 be general GPIO with
And processing_system7_0_axi_periph is the bus connecting bridge between processor and peripheral hardware.When putting up FPGA
, it is necessary to be integrated, realized and generated BitStream files after hardware bottom layer resource, it imported into be programmed in SDK and sets
Meter.
The system runs linux system using core 0, and core 1 runs grid-connected asymmetric heterogeneous multi-processor mechanism.Core
0, which is responsible for operation linux system, realizes the function that photovoltaic system is remotely monitored, while waking up and monitoring core 1, is carried out in real time with core 1
Communication.In FPGA, core 0 and core 1 have a publicly-owned resource (such as Global Timer) and private privileges (such as privately owned interruption), and core 0 and
The publicly-owned resource OCM that core 1 communicates then by them.OCM distributes resource in one piece of continuous internal memory, and it is in one piece shared
Deposit, it is necessary to which address after being mapped using internal memory is accessed.There is/dev/shm device files under facility inventory, pass through open
Function and mmap functions can obtain the starting mapping address of shared drive.
Do not conflict to allow communicate between core 0 and core 1, here using question and answer mechanism, i.e., when core 1 to core 0 send data, core
1 puts 1 by mark is sent, while sending data.The circulation of core 0, which is read, sends mark, if sending mark puts 1, that is, reads data and clear
Indicate except sending.Similarly, when core 1 receives the data that core 0 is sent, core 0 puts 1 by mark is received, while sending data.Core 1 is circulated
Read and receive mark, if receiving mark puts 1, that is, read data and remove clear flag.Double-core Principle of Communication block diagram such as Figure 16 institutes
Show.
Preferred embodiment of the present utility model described in detail above.It should be appreciated that the ordinary skill of this area without
Need creative work just can make many modifications and variations according to design of the present utility model.Therefore, it is all in the art
Technical staff on the basis of existing technology can by logical analysis, reasoning, or a limited experiment according to design of the present utility model
, all should be in the protection domain being defined in the patent claims with obtained technical scheme.
Claims (3)
1. a kind of photovoltaic parallel in system based on FPGA, it is characterised in that including photovoltaic cell PV, electric capacity of voltage regulation, DC/DC conversion
Circuit, dc bus, DC/AC full-bridge inverters, core controller FPGA, AC network and power supply unit；The photovoltaic electric
Pond PV output is in parallel with electric capacity of voltage regulation, and electric capacity output series filtering inductance L1 is in parallel with DC/DC translation circuits again, and DC/DC becomes
Change circuit output in parallel with electric capacity of voltage regulation through single-phase diode, then DC/AC full-bridge inverters are connected through dc bus, inverter is defeated
Go out series filtering inductance L2 and be connected in parallel to AC network through electric capacity of voltage regulation again；Core controller FPGA is configured as gathering photovoltaic cell
Output voltage and current information, the output voltage information of DC/DC translation circuits and system output voltage, current information, lead to
Cross self-defined driving and control module produces required signal to grid-connected system.
2. photovoltaic parallel in system according to claim 1, it is characterised in that the DC/DC translation circuits are configured as adopting
Boost boost conversion circuits are used, boosting processing is carried out to the electric energy that photovoltaic inversion is produced.
3. photovoltaic parallel in system according to claim 1, it is characterised in that the DC/AC full-bridge inverters are configured as H
The single-phase full bridge inverter circuit of bridge topological structure, wherein power switch pipe are managed for voltage driven type MOSFET, model IRF3710,
Maximum voltage 500V, maximum current 57A；The drive circuit of the power switch pipe is configured as SPWM sinusoidal pulse width modulations and light
Coupling is isolated, and isolation circuit realizes that voltage is isolated using binary channels HCPL-2630 chips, and driving chip uses special chip
IR2410。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621012771.3U CN206595719U (en) | 2016-08-30 | 2016-08-30 | A kind of photovoltaic parallel in system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621012771.3U CN206595719U (en) | 2016-08-30 | 2016-08-30 | A kind of photovoltaic parallel in system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206595719U true CN206595719U (en) | 2017-10-27 |
Family
ID=60129780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621012771.3U Active CN206595719U (en) | 2016-08-30 | 2016-08-30 | A kind of photovoltaic parallel in system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206595719U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106329567A (en) * | 2016-08-30 | 2017-01-11 | 上海新华控制技术集团科技有限公司 | Photovoltaic grid-connected system based on FPGA and realization method thereof |
| CN108448648A (en) * | 2018-03-19 | 2018-08-24 | 郑州琼佩电子技术有限公司 | A kind of intelligent optimization method of regenerative resource |
| CN108448697A (en) * | 2018-03-19 | 2018-08-24 | 山西能源学院 | A kind of intelligent optimization device of clean energy resource |
| CN108664076A (en) * | 2018-05-15 | 2018-10-16 | 陈林 | A kind of variable step MPPT control systems and method |
-
2016
- 2016-08-30 CN CN201621012771.3U patent/CN206595719U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106329567A (en) * | 2016-08-30 | 2017-01-11 | 上海新华控制技术集团科技有限公司 | Photovoltaic grid-connected system based on FPGA and realization method thereof |
| CN106329567B (en) * | 2016-08-30 | 2018-12-21 | 上海新华控制技术集团科技有限公司 | A kind of photovoltaic parallel in system and its implementation based on FPGA |
| CN108448648A (en) * | 2018-03-19 | 2018-08-24 | 郑州琼佩电子技术有限公司 | A kind of intelligent optimization method of regenerative resource |
| CN108448697A (en) * | 2018-03-19 | 2018-08-24 | 山西能源学院 | A kind of intelligent optimization device of clean energy resource |
| CN108664076A (en) * | 2018-05-15 | 2018-10-16 | 陈林 | A kind of variable step MPPT control systems and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206595719U (en) | A kind of photovoltaic parallel in system based on FPGA | |
| CN106329567B (en) | A kind of photovoltaic parallel in system and its implementation based on FPGA | |
| CN205212446U (en) | Single -phase photovoltaic grid -connected inverter controlling means | |
| CN102412598B (en) | Minitype intelligent bidirectional self-adaptation grid-connected photovoltaic power generation system and control method thereof | |
| CN102156416B (en) | Current transformer control device | |
| CN201956908U (en) | Control device of converter | |
| CN110286606B (en) | Comprehensive energy microgrid control experiment system based on semi-physical simulation | |
| CN102842917B (en) | A kind of general parallel net type photovoltaic generating system machine-electricity transient model | |
| CN201837674U (en) | Grid-connected photovoltaic power generation monitoring and analysis system | |
| CN103219733A (en) | Scattered power generation reactive compensation device and method with harmonic suppression function | |
| CN105680473A (en) | Physical fusion modeling method for general electromechanical transient information of photovoltaic power generation system | |
| CN108803406A (en) | Task hierarchy system and method for electrokinetic cell and analog meter | |
| CN101777776A (en) | Method for controlling intelligent PV grid-connected inverter based on synchro generator model | |
| CN204205923U (en) | Wind-powered electricity generation Variable flow control system | |
| CN105652950A (en) | Photovoltaic maximum power point tracing control and simulation method based on RR-LAB | |
| CN103558478A (en) | Platform for testing microgrid converter hardware on return circuit system | |
| CN103532167B (en) | Grid-connected photovoltaic system small signal stability based on FPGA judges system and method | |
| Cao et al. | Modeling and analysis of grid-connected inverter for PV generation | |
| CN203218889U (en) | Universal grid-connected photoelectric power generation system dynamo-electric transient model | |
| CN204258325U (en) | A kind of novel hybrid energy-storing control device of converter | |
| CN103427437A (en) | Central controller device | |
| CN105529946A (en) | Quasi-Z-source cascaded multi-level photovoltaic grid-connected inverter control system and method thereof | |
| Tengfei et al. | Bus voltage stability control of the distributed photovoltaic and energy storage DC microgrid based on ADRC | |
| CN203326608U (en) | Scattered power generation reactive compensation device with harmonic suppression function | |
| CN103401269B (en) | Three-phase current type multi-level converter photovoltaic power generation grid-connection device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |