CN203103968U - Motor electric drive digital control system of pipeline compressor - Google Patents
Motor electric drive digital control system of pipeline compressor Download PDFInfo
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- CN203103968U CN203103968U CN 201320004967 CN201320004967U CN203103968U CN 203103968 U CN203103968 U CN 203103968U CN 201320004967 CN201320004967 CN 201320004967 CN 201320004967 U CN201320004967 U CN 201320004967U CN 203103968 U CN203103968 U CN 203103968U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/30—Reactive power compensation
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Abstract
Disclosed in the utility model is a motor electric drive digital control system of a pipeline compressor. The digital control system comprises a main control board, a fiber plate, a VME bus cabinet, and a plurality of bottom units; the main control board and the fiber plate are inserted at the back plate of the VME bus cabinet and carry out communication with each other by a VME bus; the fiber plate and the bottom units are connected by fibers; and the bottom units are composed of controllers, integrated gate commutated thyristors (IGCT), and direct-current side capacitors. With utilization of the system, defects that the expandability is poor and the requirements of high speed and high precision of complex operations can not be met in the prior art can be overcome; and the control property of the system can meet the requirement of the reactive compensating equipment.
Description
Technical field
The utility model relates to a kind of driven by power numerical control system, especially, relate to a kind of based on integrated gate commutated thyristor (Intergrated Gate Commutated Thyristors, IGCT) the motor driven by power numerical control system of the pipeline compressor of five Level Technology.
Background technology
The basic thought of many level is to synthesize staircase waveform by a plurality of level steps, to approach sinusoidal output voltage.Level number is many more, and resulting ladder level step is many more, thereby approaches sine wave more, and harmonic components is few more.Theoretically, multi-level converter can be by synthetic infinite a plurality of level steps, the final output that realizes zero harmonic wave.But in actual applications,,, do not pursue too high level number usually satisfying under the prerequisite of performance index owing to be subjected to the restriction of hardware condition and control complexity.
From present development trend, in oil and gas industry, the full driven by power of pipeline compressor will substitute combustion gas turbine and drive.The high-power compressor of tens of MW needs big capacity, the transmission of high speed alternating current machine.Based on the five-electrical level inverter (frequency converter) of IGCT in pipeline compressor electric motor transmission application, can realize at a high speed, the target of big capacity, efficient, high reliability, smooth output voltage waveform.The control signal of traditional inverter control system and feedback signal adopt analog signal transmission usually, and there are shortcomings such as hardware circuit complexity, debug difficulties, programming complexity and anti-interference difference in it.At the five-electrical level inverter control system based on the IGCT technology, traditional control system all can't meet the demands on control precision still is response speed.
The utility model content
Because the above-mentioned defective of prior art, technical problem to be solved in the utility model provides a kind of motor driven by power numerical control system of pipeline compressor, it overcomes the deficiency of existing control system, be difficult to reach at a high speed and the defective of high-precision requirement for complex calculation, provide a kind of and programmed conveniently, respond the numerical control system fast, that antijamming capability is strong and precision is high.
For achieving the above object, the utility model provides a kind of motor driven by power numerical control system of pipeline compressor, it comprises master control borad, fibre optic plate, VME bus cabinet and several bottom floor units, wherein said master control borad and described fibre optic plate are inserted on the backboard of described VME bus cabinet, realize communication by the VME bus between the two; Described fibre optic plate is connected by optical fiber with described bottom floor units; Described bottom floor units is made up of slave controller, IGCT and dc bus capacitor.
According to the motor driven by power numerical control system of above-mentioned pipeline compressor, wherein, described fibre optic plate sends to described bottom floor units by optical fiber head with data.
According to the motor driven by power numerical control system of above-mentioned pipeline compressor, wherein, described master control borad comprises DSP and FPGA.
According to the motor driven by power numerical control system of above-mentioned pipeline compressor, wherein, described fibre optic plate and described bottom floor units are provided with two Optical Fiber Transmission, are used for swap data.
Motor driven by power numerical control system according to above-mentioned pipeline compressor, wherein, described slave controller transmits and receives by FPGA, optical fiber that circuit, voltage and current testing circuit, A/D convertor circuit, temperature sensing circuit, IGCT drive and fault return circuit and IO drive circuit are formed.
Further, motor driven by power numerical control system according to above-mentioned pipeline compressor, wherein, described voltage and current testing circuit, described A/D convertor circuit, described FPGA drive with described IGCT and are connected successively with the fault return circuit, and described optical fiber transmits and receives circuit, described temperature sensing circuit and described IO drive circuit and all is connected on the described FPGA.
Therefore, the motor driven by power numerical control system of pipeline compressor of the present utility model provides a kind of novel modularized reactive compensation control system based on FPGA, and master control borad adopts the framework of DSP+FPGA, carries out communication by VME bus and fibre optic plate.Fibre optic plate is connected by optical fiber with bottom floor units, by optical fiber head data are sent to bottom floor units, this control system adopts modularization idea, can expand according to actual needs, overcome existing technical deficiency, be difficult to reach at a high speed and the defective of high-precision requirement for complex calculation, control performance meets the requirement of five-electrical level inverter equipment.
Description of drawings
Fig. 1 is the structural representation of the motor driven by power numerical control system of pipeline compressor of the present utility model;
Fig. 2 is the structural representation of the slave controller of bottom floor units in the utility model.
Embodiment
Be described further below with reference to the technique effect of accompanying drawing, to understand the purpose of this utility model, feature and effect fully design of the present utility model, concrete structure and generation.
As shown in Figure 1, according to the motor driven by power numerical control system of pipeline compressor of the present utility model, it comprises master control borad 1, fibre optic plate 2, VME bus cabinet 3 and several bottom floor units 4.Wherein master control borad 1 and fibre optic plate 2 are inserted on VME bus cabinet 3 backboards, and the two realizes communication by the VME bus.Fibre optic plate 2 carries out exchanges data with master control borad 1, and data transaction is become the data of each bottom floor units 4 needs; Fibre optic plate 2 and bottom floor units 4 are connected by optical fiber, and by optical fiber head data are sent to bottom floor units, and fibre optic plate 2 adopts the fiber optic receiver with optical fiber receiving function simultaneously, to receive the data that bottom floor units 4 sends.The data that fibre optic plate 2 sends by the data analyzing master control borad 1 and send and bottom floor units 4 are defined as each bottom floor units and distribute corresponding data.
Master control borad 1 adopts the framework of DSP+FPGA, carries out communication by VME bus and other integrated circuit board.DSP in the master control borad 1 finish system algorithm, with the FPGA exchanges data, with function such as upper machine communication; FPGA mainly finish pulse distribution, with the functions such as protection of DSP exchanges data and system.Place memory in master control borad 1, it can be used as the buffer of exchanges data, can also deposit significant data when data volume is bigger.DSP and FPGA work in coordination, and master control borad 1 is finished functions such as the control of protection, submodule of top layer algorithm, system and protection.Master control borad 1 is behind the voltage that receives line voltage, electric current and each bottom floor units, current signal, the set-point of computing system, by the fibre optic plate in the control system 2 signal is sent in the bottom floor units 4, after bottom floor units 4 receives signal, balanced voltage and export corresponding response current in the slave controller of bottom floor units 4.Master control borad 1 adopts the stronger fpga chip of calculation function, embeds several soft nuclears in fpga chip, can the computing complicated algorithm and with the bottom floor units swap data.Master control borad 1 passes to slave controller in the bottom floor units 4 with the data that calculate by fibre optic plate after finishing algorithm.Fibre optic plate 2 adopts two Optical Fiber Transmission, the transmission of an optical fiber control data, the reception of an optical fiber control data with bottom floor units 4 swap datas.
Fibre optic plate 2 adopts the mode of FPGA control, by VME bus and other integrated circuit board communication.FPGA in the fibre optic plate 2 mainly finish and master control borad 1 between exchanges data, and the data that become each bottom floor units to need data transaction, by optical fiber head data are sent to bottom floor units 4, fibre optic plate 2 has the optical fiber reception facilities simultaneously, can receive the data that bottom floor units 4 sends, be defined as each bottom floor units and distribute corresponding data by analyzing data that data that master control borad 1 sends and bottom floor units 4 send.
VME bus cabinet 3 adopts VME bus communication agreement, and the transmission means of data adopts parallel transmission in the VME communications protocol, has effectively guaranteed transmitting speed, adopts a plurality of control lines to guarantee to transmit the real-time and the accuracy of data in the VME communications protocol.The connected mode of backboard is adopted in the realization of VME bus protocol.
Bottom floor units 4 is made up of slave controller, IGCT and dc bus capacitor.Bottom floor units 4 is mainly finished the control command that master control borad 1 sends.Wherein slave controller 5 adopts FPGA and master control borad 1 swap data, thereby reaches the purpose of accurate control reactive power compensator.Bottom floor units 4 is minimum step of output sinusoidal voltage waveform, must contain protective circuit in the bottom floor units 4 simultaneously, can excise bottom floor units automatically, the normal operation of protection whole system at the capacitance short-circuit of bottom floor units 4 or when opening circuit.
As shown in Figure 2, the slave controller 5 in the bottom floor units 4 transmits and receives by FPGA6, optical fiber that circuit 7, voltage and current testing circuit 8, A/D convertor circuit 9, temperature sensing circuit 10, IGCT drive and fault return circuit 11 and IO drive circuit 12 are formed.Wherein, voltage and current testing circuit 8, A/D convertor circuit 9, FPGA6 and IGCT drive and are connected successively with fault return circuit 11, and optical fiber transmits and receives circuit 7, temperature sensing circuit 10 and IO drive circuit and all is connected on the FPGA6.Optical fiber transmits and receives the data after circuit 7 is used to receive the data of master control borad 1 transmission and sends slave controller 5 collections and computing.A/D convertor circuit 9 is gathered the direct voltage of dc bus capacitor in each bottom floor units 4.The temperature that temperature sensing circuit 10 is gathered IGCT is used for excision drive signal when the IGCT excess temperature.The fault-signal that IGCT drives and fault return circuit 11 is used to drive the turn-on and turn-off of IGCT and receives IGCT.The thyristor of IO drive circuit 12 control bottom modules.The slave controller 5 of bottom floor units 4 mainly finish control, the submodule of bottom IGCT module switch protection, detect and control capacitance on magnitude of voltage, finish interface simultaneously with fibre optic plate 2.Slave controller 5 needs control IGCT conducting, the adhesive of control by-pass switch, control thyristor, detects capacitance voltage, detects IGCT temperature, IGCT overcurrent, overvoltage protection, finishes simultaneously and master control borad 1 communication.
Novel modularized reactive compensation control system based on FPGA of the present utility model, master control borad 1 adopts the framework of DSP+FPGA, carries out communication by VME bus and fibre optic plate 2.Fibre optic plate 2 and bottom floor units 4 are connected by optical fiber, by optical fiber head data are sent to bottom floor units 4, this control system adopts modularization idea, can expand according to actual needs, it is relatively poor to have overcome existing technology extensibility, be difficult to reach at a high speed and the defective of high-precision requirement for complex calculation, control performance meets the requirement of five-electrical level inverter equipment.
More than describe preferred embodiment of the present utility model in detail.The ordinary skill that should be appreciated that this area need not creative work and just can make many modifications and variations according to design of the present utility model.Therefore, all technical staff in the art comply with design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be in the determined protection range by claims.
Claims (6)
1. the motor driven by power numerical control system of a pipeline compressor, it is characterized in that, comprise master control borad, fibre optic plate, VME bus cabinet and several bottom floor units, wherein said master control borad and described fibre optic plate are inserted on the backboard of described VME bus cabinet, realize communication by the VME bus between the two; Described fibre optic plate is connected by optical fiber with described bottom floor units; Described bottom floor units is made up of slave controller, IGCT and dc bus capacitor.
2. the motor driven by power numerical control system of pipeline compressor according to claim 1 is characterized in that described fibre optic plate sends to described bottom floor units by optical fiber head with data.
3. the motor driven by power numerical control system of pipeline compressor according to claim 1 is characterized in that described master control borad comprises DSP and FPGA.
4. the motor driven by power numerical control system of pipeline compressor according to claim 1 is characterized in that described fibre optic plate and described bottom floor units are provided with two Optical Fiber Transmission, are used for swap data.
5. the motor driven by power numerical control system of pipeline compressor according to claim 1, it is characterized in that described slave controller transmits and receives circuit, voltage and current testing circuit, A/D convertor circuit, temperature sensing circuit, IGCT driving and fault return circuit by FPGA, optical fiber and the IO drive circuit is formed.
6. the motor driven by power numerical control system of pipeline compressor according to claim 5, it is characterized in that, described voltage and current testing circuit, described A/D convertor circuit, described FPGA drive with described IGCT and are connected successively with the fault return circuit, and described optical fiber transmits and receives circuit, described temperature sensing circuit and described IO drive circuit and all is connected on the described FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320004967 CN203103968U (en) | 2013-01-05 | 2013-01-05 | Motor electric drive digital control system of pipeline compressor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320004967 CN203103968U (en) | 2013-01-05 | 2013-01-05 | Motor electric drive digital control system of pipeline compressor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203103968U true CN203103968U (en) | 2013-07-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320004967 Expired - Fee Related CN203103968U (en) | 2013-01-05 | 2013-01-05 | Motor electric drive digital control system of pipeline compressor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203103968U (en) |
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2013
- 2013-01-05 CN CN 201320004967 patent/CN203103968U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130731 Termination date: 20170105 |