CN103065593B - Shift register unit and driving method, gate drive circuit and display device thereof - Google Patents
Shift register unit and driving method, gate drive circuit and display device thereof Download PDFInfo
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- CN103065593B CN103065593B CN201210540912.9A CN201210540912A CN103065593B CN 103065593 B CN103065593 B CN 103065593B CN 201210540912 A CN201210540912 A CN 201210540912A CN 103065593 B CN103065593 B CN 103065593B
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Abstract
The invention discloses a shift register unit and a driving method, a gate drive circuit and a display device of the shift register unit, and relates to the technical field of displaying. The shift register unit and the driving method, the gate drive circuit and the display device of the shift register unit are capable of solving the problem that the threshold voltage of a transistor drifts under direct current bias, and improving displaying quality of a product. The shift register unit comprises a upward pulling module, a pre-charge reset module, a downward pulling module, a downward pulling control module and an electric discharge module. The shift register unit and the driving method, the gate drive circuit and the displaying device of the shift register are used for achieving gate driving scanning from top to bottom or from bottom to top.
Description
Technical field
The present invention relates to display technique field, relate in particular to a kind of shift register cell and driving method thereof, gate driver circuit and display device.
Background technology
For TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor (TFT) liquid crystal display), the ultimate principle that realizes a frame picture disply is to drive signal required every one-row pixels successively output from top to bottom by source (source), then is driven successively and from top to bottom the square wave of each pixel column input certain width is carried out to gating by gate (grid).At present, the display device of manufacturing a kind of like this structure normally passes through COG (Chip On Glass by gate driving circuit and source driving circuit, chip is directly fixed on glass) technique coheres on face glass, but for undersized TFT-LCD, in the time that resolution is higher, the output that gate drives and source drives is all more, and the length of driving circuit also will increase, and this will be unfavorable for bonding (binding) technique of module driving circuit.
In order to overcome above problem, the manufacture of existing display device often adopts GOA (GateDriver on Array, array base palte is capable to be driven) design of circuit, on the basis that does not increase existing processing procedure, gate driving circuit can be integrated on face glass by Array technique, the integrated cost of not only can saving of gate driving circuit, for small size TFT-LCD, reduce the difficulty of bonding technique, also increased the reliability of panel simultaneously.
The structure of the shift register cell circuit that in prior art, basic GOA circuit comprises can be as shown in Figure 1, comprises for the transistor T 1 of precharge, for the transistor T 2 that resets, for the transistor T 3 that above draws and for drop-down transistor T 4.Wherein, the grid of transistor T 1 is connected higher level's output signal Input (n-1) with drain electrode; The grid of transistor T 1 and T4 is all connected with the output signal Reset (n+1) of subordinate, and drain electrode is all connected with low level end Voff; The grid of transistor T 3 is connected with clock signal clk 1 by capacitor C 1, and drain electrode is connected with clock signal clk 2; Node P is connected with clock signal clk 1 by capacitor C 1 equally, connects output signal Row at the corresponding levels (n) by capacitor C 2.In the time that Input (n-1) is high level, T1 is to node P precharge, and CLK2 controls T3 and will on output signal Row (n), draw as high level; In the time that Reset (n+1) is high level, T2 resets to node P, and T4 drags down output signal Row at the corresponding levels (n).A kind of like this weak point of shift register cell is, the threshold voltage of pull-down transistor can produce drift under direct current (DC) bias, and this will cause the brightness disproportionation of display device, affects the quality of product.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell and driving method, gate driver circuit and display device, can improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias, improve the display quality of product.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention, provides a kind of shift register cell, comprising: upper drawing-die piece, preliminary filling reseting module, drop-down module, drop-down control module and discharge module;
Described upper drawing-die piece, connects preliminary filling reseting module, the first clock signal and signal output part at the corresponding levels, for drawing as high level on the signal of signal output part output at the corresponding levels under the control in described preliminary filling reseting module and described the first clock signal;
Described preliminary filling reseting module, also connects first signal input end and secondary signal input end, for described upper drawing-die piece being carried out to preliminary filling or reset according to the signal of the signal of described first signal input end input and the input of described secondary signal input end;
Described drop-down module, connect described preliminary filling reseting module, the first voltage end, described drop-down control module and described signal output part at the corresponding levels, under the control at described drop-down control module and described preliminary filling reseting module by drop-down the signal of signal output part at the corresponding levels output be low level;
Described drop-down control module, also connects described the first clock signal and second clock signal, for according to drop-down module described in described the first clock signal and described second clock unblanking;
Described discharge module, connect described the first clock signal, described second clock signal, described drop-down module, described drop-down control module and described the first voltage end, for carrying out drop-down to described drop-down module and described drop-down control module respectively under the control at described the first clock signal and described second clock signal.
The embodiment of the present invention on the other hand, provides a kind of shift register driving method, is applied to as above arbitrary described shift register cell, comprising:
Preliminary filling reseting module carries out preliminary filling according to the signal of the signal of first signal input end input and the input of secondary signal input end to upper drawing-die piece;
On described upper drawing-die piece, draw shift register cell at the corresponding levels, making the signal of signal output part output at the corresponding levels is high level;
Described preliminary filling reseting module resets to described upper drawing-die piece according to the signal of the signal of described first signal input end input and the input of described secondary signal input end, and making the signal of described signal output part output at the corresponding levels is low level;
Drop-down module under the control of drop-down control module and described preliminary filling reseting module by drop-down output signal at the corresponding levels be low level; Discharge module carries out drop-down to described drop-down control module and described drop-down module respectively under the control of described the first clock signal and described second clock signal.
The embodiment of the present invention on the other hand, provides a kind of gate driver circuit, comprises multistage as above arbitrary described shift register cell;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end of the upper level shift register cell being adjacent;
Except afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end of the next stage shift register cell being adjacent.
The another aspect of the embodiment of the present invention, provides a kind of display device, comprises gate driver circuit as above.
The shift register cell that the embodiment of the present invention provides and driving method thereof, gate driver circuit and display device, can improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias, improved the display quality of product.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the electrical block diagram of existing a kind of shift register that is applied to gate driver circuit;
The structural representation of a kind of shift register cell that Fig. 2 provides for the embodiment of the present invention;
The electrical block diagram of a kind of shift register cell that Fig. 3 provides for the embodiment of the present invention;
The timing waveform of each signal when Fig. 4 is the shift register cell work shown in Fig. 3;
The electrical block diagram of a kind of gate driver circuit that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 is the timing waveform of each signal of the gate driver circuit shown in Fig. 5 while scanning from top to bottom;
Fig. 7 is the timing waveform of each signal of the gate driver circuit shown in Fig. 5 while scanning from bottom to up.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The transistor adopting in all embodiment of the present invention all can be for thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the transistorized source electrode adopting here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called source electrode, and another utmost point is called drain electrode.In addition; distinguish and transistor can be divided into N-type and P type according to transistorized characteristic; following examples all describe as inner taking N transistor; what can expect is that those skilled in the art can expect easily not making under creative work prerequisite in the time adopting P transistor npn npn to realize, therefore also in embodiments of the invention protection domain.
The shift register cell that the embodiment of the present invention provides, as shown in Figure 2, comprising: upper drawing-die piece 21, preliminary filling reseting module 22, drop-down module 23, drop-down control module 24 and discharge module 25.
Wherein, upper drawing-die piece 21 connects preliminary filling reseting module 22, the first clock signal clk and signal output part OUTPUT at the corresponding levels, for drawing as high level on the signal of signal output part OUTPUT output at the corresponding levels under the control at preliminary filling reseting module 22 and the first clock signal clk.
Preliminary filling reseting module 22 also connects first signal input end INPUT1 and secondary signal input end INPUT2, for upper drawing-die piece 21 being carried out to preliminary filling or reset according to the signal of the signal of first signal input end INPUT1 input and secondary signal input end INPUT2 input.
Drop-down module 23 connects preliminary filling reseting module 22, the first voltage end V1, drop-down control module 24 and signal output part OUTPUT at the corresponding levels, under the control at drop-down control module 24 and preliminary filling reseting module 22 by drop-down the signal of signal output part OUTPUT at the corresponding levels output be low level.
Drop-down control module 24 also connects the first clock signal clk and second clock signal CLKB, for opening drop-down module 23 according to this first clock signal clk and second clock signal CLKB.
Discharge module 25 connects respectively the first clock signal clk, second clock signal CLKB, drop-down module 23, drop-down control module 24 and the first voltage end V1, for carrying out drop-down to drop-down module 23 and drop-down control module 24 respectively under the control at this first clock signal clk and second clock signal CLKB.
The shift register cell that the embodiment of the present invention provides, can improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias, has improved the display quality of product.
Wherein, the first voltage end V1 is earth terminal, or the first voltage end V1 input low level VSS.
Further, as shown in Figure 3, in the shift register providing in the embodiment of the present invention, upper drawing-die piece 21 can comprise:
The first transistor T1, its source electrode connects signal output part OUTPUT at the corresponding levels, and grid connects preliminary filling reseting module 22, and drain electrode is connected with the first clock signal clk.
Capacitor C, it is parallel between the source electrode and grid of the first transistor T1.
In embodiments of the present invention, the effect of upper drawing-die piece 21 is after carrying out preliminary filling, and in the first clock signal clk half clock period that is high level, the high level signal that signal output part OUTPUT output grid at the corresponding levels is driven.
On the other hand, preliminary filling reseting module 22 can comprise:
Transistor seconds T2, its source electrode connects the grid of the first transistor T1, and grid connects first signal input end INPUT1, and drain electrode is connected with second voltage end V2.
The 3rd transistor T 3, its source electrode connects the grid of the first transistor T1, and grid connects secondary signal input end INPUT2, and drain electrode is connected with tertiary voltage end V3.
The effect of preliminary filling reseting module 22 is different according to the low and high level of second voltage end V2 and tertiary voltage end V3, the first clock signal clk and second clock signal CLKB, realizes the bilateral scanning of gate driver circuit.
Concrete, first signal input end INPUT1 can input the signal N-1OUT of higher level's shift register cell output, and secondary signal input end INPUT2 can input the signal N+1OUT of subordinate's shift register cell output.
In the time of second voltage end V2 input high level VGH, tertiary voltage end V3 input low level VGL, the high level of higher level's shift register cell output carries out preliminary filling by preliminary filling reseting module 22 to upper drawing-die piece 21, and the high level of subordinate's shift register cell output resets to upper drawing-die piece 21 by preliminary filling reseting module 22.
In the time of second voltage end V2 input low level VGL, tertiary voltage end V3 input high level VGH, the high level of subordinate's shift register cell output carries out preliminary filling by preliminary filling reseting module 22 to upper drawing-die piece 21, and the high level of higher level's shift register cell output resets to upper drawing-die piece 21 by preliminary filling reseting module 22.
So, in the time that gate driver circuit scans from top to bottom, transistor seconds T2 is preliminary filling part, and the 3rd transistor T 3 is reset part; In the time that gate driver circuit scans from bottom to up, the 3rd transistor T 3 is preliminary filling part, and transistor seconds T2 is reset part.Wherein, in half clock period that it is high level that preliminary filling part refers at second clock signal CLKB, the part circuit structure that the grid of the first transistor T1 is carried out to precharge; The part that resets refers at shift register output grid at the corresponding levels and drives after square wave, controls to above drawing the part circuit structure that node PU point current potential resets.Wherein, above draw control node PU to be connected with the grid of the first transistor T1, for controlling the opening and closing of the first transistor T1.
Further, drop-down module 23 can comprise:
The 4th transistor T 4, its source electrode connects the first voltage end V1, and grid connects the source electrode of the 9th transistor T 9, and drain electrode connects the grid of the first transistor T1.
The 5th transistor T 5, its source electrode connects the first voltage end V1, and grid connects the source electrode of the 7th transistor T 7, and drain electrode connects signal output part OUTPUT at the corresponding levels.
Drop-down control module 24 can comprise:
The 6th transistor T 6, its source electrode connects the first voltage end V1, and grid connects the grid of the first transistor T1, and drain electrode is connected with the grid of the 9th transistor T 9 with the source electrode of the 8th transistor T 8 respectively.
The 7th transistor T 7, its grid is connected with second clock signal CLKB with drain electrode.
The 8th transistor T 8, its source electrode connects the grid of the 9th transistor T 9, and grid is connected with the first clock signal clk with drain electrode.
The 9th transistor T 9, its drain electrode is connected with the first clock signal clk.
In embodiments of the present invention, the effect of drop-down module 23 is specifically under the control of drop-down control module 24 output signals, when on while drawing that to control node PU point current potential be low, and be that high level, second clock signal CLKB are in low level half clock period at the first clock signal clk, in the time that the first drop-down control node PD1 is noble potential by the 4th transistor T 4 on draw and control node PU current potential and carry out drop-down; In the first clock signal clk is low level, second clock signal CLKB half clock period that is high level, in the time that the second drop-down control node PD2 is noble potential, carry out drop-down by the 5th transistor T 5 to signal output part OUTPUT current potential at the corresponding levels.Wherein, the current potential of the first drop-down control node PD1 by the first clock signal clk, on draw and control node PU and second clock signal CLKB and control, the current potential of the second drop-down control node PD2 is controlled by the first clock signal clk and second clock signal CLKB.The effect of drop-down control module 24 be the first clock signal clk, on draw under the control of controlling node PU and second clock signal CLKB, control the current potential of the first drop-down control node PD1; Under the control of the first clock signal clk and second clock signal CLKB, control the current potential of the second drop-down control node PD2.
Wherein, the first drop-down control node PD1 is connected with the grid of the 4th transistor T 4, for controlling the opening and closing of the 4th transistor T 4; The second drop-down control node PD2 is connected with the grid of the 5th transistor T 5, for controlling the opening and closing of the 5th transistor T 5.
Further, discharge module 25 can comprise:
The tenth transistor T 10, its source electrode connects the first voltage end V1, and grid connects second clock signal CLKB, and drain electrode connects the grid of the 4th transistor T 4.
The 11 transistor T 11, its source electrode connects the first voltage end V1, and grid connects the first clock signal clk, and drain electrode connects the grid of the 5th transistor T 5.
The tenth two-transistor T12, its source electrode connects the first voltage end V1, and grid connects second clock signal CLKB, and drain electrode connects the grid of the 9th transistor T 9.
In embodiments of the present invention, as shown in Figure 3, the effect of discharge module 25 is in the time that the first clock signal clk is high level, carries out drop-down by the 11 transistor T 11 to the second drop-down control node PD2; In the time that second clock signal CLKB is high level, by the tenth transistor T 10, the first drop-down control node PD1 is carried out drop-downly, simultaneously carry out drop-down by the tenth two-transistor T12 to controlling node M.Wherein, control node M and be positioned at the source electrode of the 8th transistor T 8, and be connected with the grid of the 9th transistor T 9, for controlling the opening and closing of the 9th transistor T 9.
It should be noted that, in embodiments of the present invention, discharge module 25 at least comprises the tenth transistor T 10, at least one in the 11 transistor T 11 or the tenth two-transistor T12, so, can by the tenth transistor T 10 control the 4th transistor T 4 on draw and control node PU and carry out drop-down, or controlling the 5th transistor T 5 by the tenth transistor T 11 carries out drop-down to signal output part OUTPUT at the corresponding levels, or control the unlatching of the 9th transistor T 9 or close by the tenth two-transistor T 12, or respectively by the tenth transistor T 10, the 11 transistor T 11 or the tenth two-transistor T 12 realize drop-down module and control the alternately drop-down of node PU and signal output part OUTPUT at the corresponding levels to above drawing.
The embodiment of the present invention also provides a kind of shift register driving method, can be applied to shift register cell described above, comprising:
Preliminary filling reseting module carries out preliminary filling according to the signal of the signal of first signal input end input and the input of secondary signal input end to upper drawing-die piece.
On upper drawing-die piece, draw shift register cell at the corresponding levels, making the signal of signal output part output at the corresponding levels is high level.
Preliminary filling reseting module resets to upper drawing-die piece according to the signal of the signal of first signal input end input and the input of secondary signal input end, and making the signal of signal output part output at the corresponding levels is low level.
Drop-down module under the control of drop-down control module and preliminary filling reseting module by drop-down output signal at the corresponding levels be low level; Discharge module carries out drop-down to drop-down control module and drop-down module respectively under the control of the first clock signal and second clock signal.
The shift register cell driving method that the embodiment of the present invention provides, can improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias, has improved the display quality of product.
Adopt a kind of like this shift register cell of structure, can realize the bilateral scanning of gate driver circuit by changing the height of control signal level.For example, in shift register cell as shown in Figure 3, first signal input end INPUT1 can input the signal N-1OUT of higher level's shift register cell output, and secondary signal input end INPUT2 can input the signal N+1OUT of subordinate's shift register cell output.
In the time of second voltage end V2 input high level VGH, tertiary voltage end V3 input low level VGL, the high level of higher level's shift register cell output carries out preliminary filling by preliminary filling reseting module 22 to upper drawing-die piece 21, and the high level of subordinate's shift register cell output resets to upper drawing-die piece 21 by preliminary filling reseting module 22.
In the time of second voltage end V2 input low level VGL, tertiary voltage end V3 input high level VGH, the high level of subordinate's shift register cell output carries out preliminary filling by preliminary filling reseting module 22 to upper drawing-die piece 21, and the high level of higher level's shift register cell output resets to upper drawing-die piece 21 by preliminary filling reseting module 22.
Concrete, can, in conjunction with the time-state method shown in Fig. 4, driving method and the duty of the shift register cell shown in embodiment of the present invention Fig. 3 be described in detail.
The preliminary filling stage: under this stage the sequential of control signal can as in Fig. 4 1. as shown in, wherein, clock signal clk is that low level, CLKB are high level, signal input part INPUT 1 inputs the signal N-1OUT of higher level's shift register cell output, the signal N+1OUT of signal input part INPUT2 input subordinate shift register cell output, N-1OUT is high level, N+1OUT is low level, second voltage end V2 input high level VGH, tertiary voltage end V3 input low level VGL.Now, transistor T 3, T8, T9, T11 close, and transistor T 2, T7, T10, T12 open, and the first drop-down control node PD1 and control node M are electronegative potential, and transistor T 4 is closed.N-1OUT carries out precharge to the grid of transistor T 1, above draws and controls the rising of node PU point voltage, and the grid of transistor T 1 keeps precharging state; Clock signal clk B, by drawing the second drop-down control node PD2 on transistor T 7, makes the current potential of the second drop-down control node PD2 for high, and transistor T 5 is opened, thereby makes OUTPUT end be set to low level.
On draw the stage: under this stage the sequential of control signal can as in Fig. 4 2. as shown in, wherein, after the preliminary filling stage, clock signal clk is that high level, CLKB are that low level, N-1OUT are that low level, N+1OUT are low level.Now, transistor T 6, T8, T11 open, and transistor T 2, T3, T7, T10 close.On draw and control node PU point potential rise, transistor T 1 is opened, thereby makes to draw on the signal of OUTPUT end output, exports high level signal.It should be noted that in the design of side circuit, the current potential that the channel width-over-length ratio of transistor T 6, T8, T9 should meet the first drop-down control node PD1 in the time that above to draw the current potential of controlling node PU be high is low and transistor T 4 is closed; When clock signal clk is while being high, transistor T 11 is drop-down to the second drop-down control node PD2, and transistor T 5 is closed.
Reseting stage: under this stage the sequential of control signal can as in Fig. 4 3. as shown in, wherein, clock signal clk is that low level, CLKB are high level, N-1OUT is low level, N+1OUT is high level.Now, transistor T 1, T2, T6, T8, T11 close, transistor T 3, T7, T10, T12 open, on draw that to control node PU node be electronegative potential, the first drop-down control module PD1 is electronegative potential, the second drop-down control module PD2 is noble potential, and transistor T 5 is opened, thereby makes OUTPUT end be set to low level.
The first drop-down stage: under this stage the sequential of control signal can as in Fig. 4 4. as shown in, wherein, clock signal clk is that high level, CLKB are low level, N-1OUT is that low level, N+1OUT are low level.Now, transistor T 1, T2, T3, T6, T7, T10 close, and transistor T 8, T9, T11 open, the first drop-down control node PD1 is high level, the second drop-down control node PD2 is low level, and transistor T 4 is opened, and above draws control node PU to be pulled down to low level.In this stage, clock signal clk is also controlled transistor T 11 and is carried out drop-down to the second drop-down control node PD2
The second drop-down stage: under this stage the sequential of control signal can as in Fig. 4 5. as shown in, wherein, clock signal clk is that low level, CLKB are that high level, N-1OUT are that low level, N+1OUT are low level.Now, transistor T 1, T2, T3, T6, T8, T11 close, and transistor T 7, T10, T12 open, and the first drop-down control node PD1 is low level.The second drop-down control node PD2 is high level, and transistor T 5 is opened, thereby makes OUTPUT end be pulled down to low level.In this stage, clock signal clk B also control transistor T 10 the first drop-down control node PD 1 is carried out drop-down, clock signal clk B also control T12 to control node M carry out drop-down.
So realize the displacement from N-1OUT to OUTPUT, under the control of doubleclocking signal, realized the capable driving scanning of top-down grid output.It should be noted that, in embodiments of the present invention, can change the mode of preliminary filling and reset by changing the high electronegative potential of signal N-1OUT, N+1OUT, VGH and VGL, realize gate driver circuit bilateral scanning from top to bottom or from bottom to up.
Shift register cell of the present invention is by the drop-down control node of clock signal clk control first PD1, and then control above drawing control node PU to carry out drop-down transistor T 4, in half clock period that is simultaneously high level by clock signal clk control transistor T 11 at CLK, the second drop-down control node PD2 is discharged, transistor T 5 is closed; Control the second drop-down control node PD2 by clock signal clk B, and then control OUTPUT end is carried out to drop-down transistor T 5, control in half clock period that transistor T 12 is high level at CLKB and discharge to controlling node M by clock signal clk B simultaneously, transistor T 9 is closed; Control in half clock period that transistor T 10 is high level at CLKB the first drop-down control node PD1 is discharged by clock signal clk B, transistor T 4 is closed.The shift register cell of structure can effectively reduce the dutycycle that pull-down transistor and discharge transistor are opened like this, has prevented that the output that clock modulation brings is unsettled; In realizing gate driver circuit bilateral scanning, significantly improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias.
The gate driver circuit that the embodiment of the present invention provides, as shown in Figure 5, comprises multistage shift register cell as above.Wherein, the output terminal OUTPUT of every one-level shift register cell SR exports line scan signals G at the corresponding levels; Each shift register cell has a first clock signal clk input and a second clock signal CLKB input; Second clock signal CLKB and the first clock signal clk have the phase differential of 180 degree, and the first clock signal clk and all half the time output high level within the work period separately of second clock signal CLKB, second half time output low level; In addition the first clock signal clk of two adjacent shift register cells has 180 degree phase differential, and the second clock signal CLKB of two adjacent shift register cells has 180 degree phase differential.
Except first order shift register cell SR0, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end N+1OUT of the upper level shift register cell being adjacent.
Except afterbody shift register cell SRn, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end N-1OUT of the next stage shift register cell being adjacent.
In embodiments of the present invention, the first signal input end N-1OUT of first order shift register cell SR0 can incoming frame start signal STV; The secondary signal input end N+1OUT of afterbody shift register cell SRn can input reset signal RST.
The gate driver circuit that the embodiment of the present invention provides can be in realizing gate driver circuit bilateral scanning, significantly improves the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias.
Concrete, in the time that gate driver circuit adopts scan mode from top to bottom, the timing waveform of the horizontal-drive signal of its control signal and output is as shown in Figure 6.Wherein, clock signal clk, CLKB, the sequential of voltage VGH, VHL, VSS can be with reference to shown in Fig. 4, and frame start signal STV provides a square wave in the incipient stage, and reset signal RST provides a square wave in ending phase.Can be clear that, horizontal-drive signal, by G0 to Gn, is exported from top to bottom successively.
In the time that gate driver circuit adopts scan mode from bottom to up, the timing waveform of the horizontal-drive signal of its control signal and output as shown in Figure 7.Wherein, clock signal clk, CLKB, the sequential of voltage VGH, VHL has been carried out the conversion of high electronegative potential compared with the waveform shown in Fig. 6, voltage VSS current potential height is constant, the RST of reset signal shown in Fig. 7 is identical with the frame start signal STV shown in Fig. 6, and the STV of frame start signal shown in Fig. 7 is the reset signal RST shown in Fig. 6.Can be clear that, horizontal-drive signal, by GLn+1 to G0, is exported from bottom to up successively.
The embodiment of the present invention also provides a kind of display device, comprises gate driver circuit as above.
The display device that the embodiment of the present invention provides, comprises gate driver circuit, can improve the problem that the threshold voltage of pull-down transistor drifts about under direct current (DC) bias, has improved the display quality of product.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (11)
1. a shift register cell, is characterized in that, comprising: upper drawing-die piece, preliminary filling reseting module, drop-down module, drop-down control module and discharge module;
Described upper drawing-die piece, connects preliminary filling reseting module, the first clock signal and signal output part at the corresponding levels, for drawing as high level on the signal of signal output part output at the corresponding levels under the control in described preliminary filling reseting module and described the first clock signal;
Described preliminary filling reseting module, also connects first signal input end and secondary signal input end, for described upper drawing-die piece being carried out to preliminary filling or reset according to the signal of the signal of described first signal input end input and the input of described secondary signal input end;
Described drop-down module, connect described preliminary filling reseting module, the first voltage end, described drop-down control module and described signal output part at the corresponding levels, under the control at described drop-down control module and described preliminary filling reseting module by drop-down the signal of signal output part at the corresponding levels output be low level;
Described drop-down control module, also connects described the first clock signal and second clock signal, for according to drop-down module described in described the first clock signal and described second clock unblanking;
Described discharge module, connect described the first clock signal, described second clock signal, described drop-down module, described drop-down control module and described the first voltage end, for carrying out drop-down to described drop-down module and described drop-down control module respectively under the control at described the first clock signal and described second clock signal.
2. shift register cell according to claim 1, is characterized in that, described upper drawing-die piece comprises:
The first transistor, its source electrode connects described signal output part at the corresponding levels, and grid connects described preliminary filling reseting module, and drain electrode is connected with described the first clock signal;
Electric capacity, it is parallel between the source electrode and grid of described the first transistor.
3. shift register cell according to claim 2, is characterized in that, described preliminary filling reseting module comprises:
Transistor seconds, its source electrode connects the grid of described the first transistor, and grid connects described first signal input end, and drain electrode is connected with second voltage end;
The 3rd transistor, its source electrode connects the grid of described the first transistor, and grid connects described secondary signal input end, and drain electrode is connected with tertiary voltage end.
4. shift register cell according to claim 3, is characterized in that, the signal of described first signal input end input higher level shift register cell output, and described secondary signal input end is inputted the signal of subordinate's shift register cell output;
In the time of described second voltage end input high level, described tertiary voltage end input low level, the high level of higher level's shift register cell output carries out preliminary filling by described preliminary filling reseting module to described upper drawing-die piece, and the high level of subordinate's shift register cell output resets to described upper drawing-die piece by described preliminary filling reseting module;
In the time of described second voltage end input low level, described tertiary voltage end input high level, the high level of subordinate's shift register cell output carries out preliminary filling by described preliminary filling reseting module to described upper drawing-die piece, and the high level of higher level's shift register cell output resets to described upper drawing-die piece by described preliminary filling reseting module.
5. shift register cell according to claim 2, is characterized in that, described drop-down module comprises:
The 4th transistor, its source electrode connects described the first voltage end, and grid connects the 9th transistorized source electrode, and drain electrode connects the grid of described the first transistor;
The 5th transistor, its source electrode connects described the first voltage end, and grid connects the 7th transistorized source electrode, and drain electrode connects described signal output part at the corresponding levels;
Described drop-down control module comprises:
The 6th transistor, its source electrode connects described the first voltage end, and grid connects the grid of described the first transistor, and drain electrode is connected with the 9th transistorized grid with the 8th transistorized source electrode respectively;
The 7th transistor, its grid is connected with described second clock signal with drain electrode;
The 8th transistor, its source electrode connects described the 9th transistorized grid, and grid is connected with described the first clock signal with drain electrode;
The 9th transistor, its drain electrode is connected with described the first clock signal.
6. shift register cell according to claim 5, is characterized in that, described discharge module comprises:
The tenth transistor, its source electrode connects described the first voltage end, and grid connects described second clock signal, and drain electrode connects described the 4th transistorized grid;
The 11 transistor, its source electrode connects described the first voltage end, and grid connects described the first clock signal, and drain electrode connects described the 5th transistorized grid;
The tenth two-transistor, its source electrode connects described the first voltage end, and grid connects described second clock signal, and drain electrode connects described the 9th transistorized grid.
7. a shift register driving method, be applied to as arbitrary in claim 1 to 6 as described in shift register cell, it is characterized in that, comprising:
Preliminary filling reseting module carries out preliminary filling according to the signal of the signal of first signal input end input and the input of secondary signal input end to upper drawing-die piece;
On described upper drawing-die piece, draw shift register cell at the corresponding levels, making the signal of signal output part output at the corresponding levels is high level;
Described preliminary filling reseting module resets to described upper drawing-die piece according to the signal of the signal of described first signal input end input and the input of described secondary signal input end, and making the signal of described signal output part output at the corresponding levels is low level;
Drop-down module under the control of drop-down control module and described preliminary filling reseting module by drop-down output signal at the corresponding levels be low level; Discharge module carries out drop-down to described drop-down control module and described drop-down module respectively under the control of described the first clock signal and described second clock signal.
8. method according to claim 7, is characterized in that, the signal of described first signal input end input higher level shift register cell output, and described secondary signal input end is inputted the signal of subordinate's shift register cell output;
In the time of described second voltage end input high level, described tertiary voltage input end input low level, the high level of higher level's shift register cell output carries out preliminary filling by described preliminary filling reseting module to described upper drawing-die piece, and the high level of subordinate's shift register cell output resets to described upper drawing-die piece by described preliminary filling reseting module;
In the time of described second voltage end input low level, described tertiary voltage input end input high level, the high level of subordinate's shift register cell output carries out preliminary filling by described preliminary filling reseting module to described upper drawing-die piece, and the high level of higher level's shift register cell output resets to described upper drawing-die piece by described preliminary filling reseting module.
9. a gate driver circuit, is characterized in that, comprises multistage shift register cell as described in as arbitrary in claim 1 to 6;
Except first order shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the secondary signal input end of the upper level shift register cell being adjacent;
Except afterbody shift register cell, the signal output part at the corresponding levels of all the other each shift register cells connects the first signal input end of the next stage shift register cell being adjacent.
10. gate driver circuit according to claim 9, is characterized in that, the first signal input end incoming frame start signal STV of described first order shift register cell; The secondary signal input end input reset signal RST of described afterbody shift register cell.
11. 1 kinds of display devices, is characterized in that, comprise the gate driver circuit as described in claim 9 or 10.
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| CN103761952B (en) * | 2013-12-31 | 2016-01-27 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit of liquid crystal panel, liquid crystal panel and a kind of driving method |
| CN104464666B (en) * | 2014-12-09 | 2017-01-18 | 昆山龙腾光电有限公司 | Grid electrode drive circuit and display device thereof |
| CN104575437B (en) * | 2015-02-06 | 2017-01-25 | 京东方科技集团股份有限公司 | Shifting register, driving method of shifting register, grid driving circuit and display device |
| CN105976775B (en) * | 2016-05-18 | 2019-01-15 | 武汉华星光电技术有限公司 | GOA circuit based on LTPS semiconductor thin-film transistor |
| CN105788553B (en) * | 2016-05-18 | 2017-11-17 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN106205530B (en) * | 2016-07-26 | 2018-10-16 | 武汉华星光电技术有限公司 | GOA circuits |
| CN106448538B (en) | 2016-11-01 | 2019-11-12 | 合肥鑫晟光电科技有限公司 | Drive element of the grid, gate driving circuit and its driving method and display device |
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