CN1030593C - Nonvolatile memory and method of manufacturing thereof - Google Patents
Nonvolatile memory and method of manufacturing thereof Download PDFInfo
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- CN1030593C CN1030593C CN 89108268 CN89108268A CN1030593C CN 1030593 C CN1030593 C CN 1030593C CN 89108268 CN89108268 CN 89108268 CN 89108268 A CN89108268 A CN 89108268A CN 1030593 C CN1030593 C CN 1030593C
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- layer
- insulating barrier
- polysilicon
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- conductive layer
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Abstract
The present invention relates to an interface obtaining a very smooth layer of polycrystalline silicon 1/an insulation layer between layers/ the layer of a polycrystalline silicon 2. Essentially, a layer 18 of the polycrystalline silicon 1 is a depositional layer of LPCVD with an amorphous phase and is used for injection doping, and a proper insulation layer 20 is deposited. Subsequently, the layer 18 of the polycrystalline silicon 1 is recrystallized at the temperature of about 1000 DEG C, and then the interface of the polycrystalline silicon 2 obtained by using the layer of LPCVD deposited polycrystalline silicon 2 and adulterating POCl-[3] in 950 DEG C temperature/the insulation layer between the layers/the polycrystalline silicon 1 is a very smooth interface with an atomic range. Even, other devices are manufactured through a heat cycle, and superior leakage characteristic is caused.
Description
The present invention relates to integrated circuit and their manufacture method.
VLSI nonvolatile memory and other high voltage integrated circuit are used two-layer polysilicon usually, there is a kind of appropriate insulation layer the very requirement of low-leakage current only to be arranged between the two-layer polysilicon when standing high electric field to satisfy, usually, polysilicon layer is the big LPCVD method deposition of using under 620 ℃ of temperature, and insulating barrier can be the hot grown oxide on polysilicon 1, and perhaps it also can be the THIN COMPOSITE rete of oxide/nitride/oxide.
In many kinds of integrated circuit structures, particularly resemble in this nonvolatile memory of EPROM and EEPROM, the smoothness of polysilicon and insulating barrier interface is very crucial in the polysilicon-polysilicon silicon capacitor, this is because usually when oxide growth is on polysilicon, interface between polysilicon and the insulating barrier is very coarse, just as is well known, these uneven electric field strength that will be directed at increase, therefore, in order to prevent to puncture, required thickness when the thickness of insulating barrier must be made to such an extent that be fully level and smooth much larger than the interface, this problem of determining that is situated between was once attempted in the research of prior art, one level and smooth polysilicon one interfacial dielectric layer promptly is provided, but does not obtain significant success as yet.Most important list of references gathers for your guidance following in the prior art according to the knowledge of the applicant:
1.L.Faraone, An Improved Fabrication Process forMulti-level Polysilion Strceture.RCA Laboratories(do not point out the date-obviously this did not publish at internal circulation).
2.Harbek Deng the people, LPCVD Polycrystalline Silceon:Growth and Physical Properties of In-Situ Phosphorus Doped and undoped Films, 44RCA Review 287(June 1983).
3.Chias Deng the people, Developments in Thin Polyoxides for Non Volatile Memories Semiconductor International. April 1985.P156-159.
4.Faraone Deng the people, Characteriyation of Thermally Otidized n-Paly-crystalline Sillcon.32 IEEE Transaction on Electron Devicas-(March 1985).
In the seemingly the most useful discussion in the prior art of one piece of paper of the Faraone of IEEE proceedings electronic device fascicle (IEEE Transactions On Electron Device) publication, this piece paper includes the key recommendations that improves the interface smoothness, the polysilicon layer that is the bottom should be that amorphous aspect is not polysilicon layer, as prior art is known, that is exactly the temperature of deposition, (for example) be reduced to 562 ℃ from 625 ℃, such sedimentary deposit just no longer is polysilicon and in fact be unbodied, specific surface is much level and smooth mutually with the polycrystal layer for this unformed layer, this is that grain boundary and crystal grain orienting difference tend to produce some surperficial roughness because in polysilicon layer.
But very crucial argumentation of the present invention is after amorphous first silicon layer is deposited, and it should oxidation, but should deposit a layer insulating, and this point to be the prior art of having delivered all do not comprise.The reason of doing like this is that oxidizing process reduces surface quality, its reason is not only aspect heat, as if oxidizing process comprise the increase of oxygen along the grain boundary diffusion, and this grain boundary diffusion itself will produce roughness, therefore, the chemical vapor deposition of high-quality insulating barrier will carry out under than the low slightly temperature of low-temperature oxidation step temperature, but the interface smoothness that generates improved greatly, because the effect that oxygen transmits along the grain boundary has been avoided basically.Therefore, the present invention and any art methods specific energy mutually provide a kind of very level and smooth interface,
And, should be noted that in the discussion of prior art smooth interface, not resemble and propose the complete method of making the present invention, as if prior art processes needs point-device temperature to control temperature used in the low-temperature oxidation step, and so accurate control has reduced production capacity.Therefore, the improvement of another advantage of the present invention production capacity.
And the present invention also further proposes silicon layer and should not adopt diffusing, doping (for example, to use POCl
3) and should adopt to inject and mix, inject the further amorphization of silicon layer that doping method makes deposition, therefore, after higher temperature insulating layer deposition step, can also help to make this one deck to keep less crystallite dimension.
Should be noted that, no matter use the oxidation technology of prior art or the method for depositing insulating layer of the present invention, some grain growths always appear during hot stage, wonderful result of the present invention is that the insulating barrier of deposition but keeps a kind of very level and smooth interface, even also is like this when this crystal grain of growth converts this amorphous as deposited layer to polycrystal layer.
In a class embodiment of the present invention, depositing insulating layer is made up of oxide/nitride, and further thermal oxidation forms a kind of oxide/nitride/oxide structure, and this insulating barrier is useful especially to the surface that keeps polysilicon 1 in the thermal cycle cycle in position.
Should point out that also the discussion of unique known correlation that diffusing, doping and ion are injected appears at Fanaone and communicate by letter, the latter 21 is quoted in the Faraone article as a reference, and the applicant has obtained copy, and is existing as annex confession referendary reference.But should point out that this piece article may not delivered as yet, so in the country that several present patent application wish to patent, pressing Patent Law can not be as appropriate term of reference at least.
Therefore, the present invention provides a theatrical improvement result who surpasses art methods and structure aspect interface quality, this causes a kind of capacitor, and (wherein lower floor's pole plate is a polycrystal, mainly be silicon), this capacitor is under given thickness of insulating layer, puncture voltage has been improved (qualitative factor that adopts everybody to accept), and the charge storage amount of capacitor unit are has significantly increased.
Particularly the present invention has special advantage to the EPROM element, coupling is always wished tight as far as possible between the floating grid and the control utmost point, but the insulating barrier between the two-layer polysilicon must be not breakdown under employed voltage, and the leakage current of this insulating barrier must extremely hang down to keep a good storage life.Because rough interface degree between polysilicon and the insulating barrier has been lowered in the present invention, has not only advantageously improved puncture voltage, and has reduced the leakage current when being lower than puncture voltage.
Therefore, EPROM that makes by the present invention or EEPROM unit are compared with any product of prior art aspect the coupling of the control utmost point and floating grid and leakage current and are had outstanding advantage and substantial improvement.
Therefore, except mention in the application some other, the present invention provides following advantage at least:
1. repeated better manufacture method.
2. reduced leakage current by interlaminar capacitor.
3. improved the puncture voltage of interlaminar capacitor.
4. under given puncture voltage, interlaminar capacitor can have higher ratio electric capacity.
5. thereby the floating gate memory transistor that can make certain density makes programming very fast.
The invention provides a kind of integrated-circuit capacitor, it comprises the first polycrystal conductive layer that contains 50%～100% silicon atom, is applied to the device on the said capacitor at the composite insulation layer on this conductive layer, at second conductive layer on the insulating barrier with voltage, if said insulating barrier is a kind of desirable insulating barrier with thickness of said insulating barrier, this voltage is to puncture 1/4th of said insulating barrier required voltage at least.
The present invention also provides Nonvolatile memery unit, it comprises that a transistor channel region, is positioned at top floating grid, this floating grid capacitive is coupled to the control utmost point that said transistor channel region, a capacitive are coupled to said floating grid, the said control utmost point is to be coupled to said floating grid by the insulating barrier capacitive, and this insulating barrier is 80 perpendicular to the maximum partial deviations at said interface
The present invention also provides a kind of Nonvolatile memery unit, it comprises that a transistor channel region, is positioned at top floating grid, and this floating grid capacitive is coupled to that said transistor channel region, a capacitive are coupled to the control utmost point of said floating grid, the said control utmost point is coupled to said floating grid by the insulating barrier capacitive.This insulating barrier is 10% perpendicular to the maximum local thickness deviation at interface.
The present invention also provides a kind of manufacture method of Nonvolatile memery unit, the step of this method comprises: Semiconductor substrate is provided, on the transistorized precalculated position of nonvolatile memory, form the door insulator, deposit first conductive layer, this conductive layer contains 50%～100% amorphous silicon (atom) (not being polycrystal) on the non-volatile memory transistor presumptive area, depositing insulating layer on ground floor, on insulating barrier, deposit second conductive layer and said first and second conductive layers are made figure, so that in said non-volatile memory transistor presumptive area, said first conductive layer forms said second conductive layer of floating grid and forms control gate.
The present invention also provides a kind of method of making capacitor in integrated circuit is made between two conductive layers, this method comprise deposition contain the step of 50%～100% amorphous silicon (not being polycrystal) (atom), depositing insulating layer on the said ground floor and on said insulating barrier a kind of second conductive layer of deposition.
Accompanying drawing below in conjunction with most preferred embodiment is done more detailed narration to the present invention:
Fig. 1～3rd, microphoto, Fig. 3 are the microphotos by the sample structure of the inventive method manufacturing, and Fig. 1 and 2 is the sample structure microphoto of making by other technology.
Fig. 4 A～4C is a ribbon diagram of making sample by the inventive method.
To go through below and make and use most preferred embodiment, should be understood that, the invention provides can extensive use inventive concept.These notions can be used for many occasions.Most preferred embodiment described here only is manufacturing to be described as an example and to use method of the present invention, and scope of the present invention never is subjected to the restriction of these most preferred embodiments.
Fig. 1 is the microphoto of the section bright field transmission electron microscope of batch #2600/#3 sheet.Polysilicon 1 is 620 ℃ of temperature deposit, uses POCl
3Mixing (1000 ℃, 8 minutes) and removed smooth layer (Deglazed) 30 minutes with 10%HF, then is the interlayer insulating film deposition: 330
Oxide (bottom)+85
Nitride (top), this nitride is partial oxidation under 1000 ℃, water vapour and 60 minutes conditions, and deposit spathic silicon is 2 layers again.
Fig. 2 is the microphoto of the section bright field transmission electron microscope of batch #2600/#7 sheet.Polysilicon 1 is 620 ℃ of temperature deposit and injects mix (P31,50Kev, 1.0E16/cm
2Dosage), then be the deposition interlayer insulating film: 330
Oxide (bottom)+85
Nitride (top), this nitride is partial oxidation under 1000 ℃, steam and 60 minutes conditions, and deposit spathic silicon is 2 layers then.
Fig. 3 is the microphoto of the section bright field transmission electron microscope of batch #2600/#19 sheet.Polysilicon 1 is 560 ℃ of temperature deposit and inject mix (P31,50Kev, 1.0E16/cm
2Dosage), then be the deposition interlayer insulating film: 330
Oxide (bottom)+85
Nitride (top), this nitride is partial oxidation under the condition of 1000 ℃, steam and 60 minutes, then, deposit spathic silicon 2.
The present invention has narrated a kind of interface that can obtain very level and smooth polysilicon 2/ interlayer insulating film/polysilicon 1, the usefulness of the VLSI of the insulating barrier that supply and demand will be extremely thin.Polysilicon is the deposition of the amorphous phase under 560 ℃ for 1 layer, the 50-Kev condition following with P31 by about 1.0E16cm
-2Dosage inject to mix, then with LPCVD deposition (under 800 ℃ of conditions) interlayer insulating film: 330
SiO
2(bottom)/85
Si
3N
4(top), next one is (1000 ℃ of oxidizing processs, steam, 60 minutes), the part nitride layer is changed into a kind of oxynitrides so that the insulating barrier of forming by three layers to be provided, in this oxidation step, the polysilicon of bottoming is annealed for 1 layer, so that the amorphous phase recrystallization of deposition, meanwhile still keep level and smooth polysilicon 1/ deposition oxide interface, partly the thermal oxidation of nitride layer also can be adopted the short time (about 30 minutes), condition is in the water vapour and 1000 ℃, perhaps adopts (for example, 850 ℃ of high pressure oxidations, 10 atmospheric water vapours, about 27 minutes), to reduce dopant species excessive laterally moving (as from the arsenic of hiding diffusion) in lower floor's silicon single crystal.
Being right after is at 620 ℃ of deposit second polysilicon layers after the interlayer insulating film manufacturing, and mixes POCl under 950 ℃
3About 20 minutes of-impurity is removed smooth layer (30 seconds) with 10%HF, and then, remaining device fabrication processes is finished according to a conventional method.
Now will be compared as follows with the method that the present invention does the people such as Faraone of the method for embodiment sample and RCA:
Method step the present invention (TI) method RCA method
560 ℃ of the depositions of polysilicon 1,3000
560 ℃, 7500
The doping P31 ion of polysilicon 2 injects the P31 ion and injects
（50Kev， （120Kev，
1E13cm
-2） 1E16cm
-2）
Thermal oxidation-850 ℃, water vapour, 750
800 ℃ of lpcvd oxide depositions, 330A(changes)-
800 ℃ of LPCVD nitride depositions, 85A(changes)-
Anneal 1000 ℃, water vapour-
(30-60 minute)
(perhaps: high steam oxygen
Change 850 ℃ of 10 atmospheric pressure)
620 ℃ of polysilicon 2 depositions, 560 ℃ of 4500A?
Above a critical difference of two kinds of methods be that the present invention adopts the LPCVD method layer insulation to be deposited to the top of unbodied n-polysilicon 1, under 1000 ℃ of temperature, it is annealed then, so that its recrystallization, and RCA is a kind of thermal oxidation insulating barrier of growth on unbodied n-polysilicon 1.The deposition of interlayer insulating film of the present invention provide a kind of than the method that proposes of Faraone article be easier to the method making and repeat because the thin oxide of thermal oxide growth is difficult to control.
Method disclosed by the invention can not only be used for EPROM and EEPROM, also can be used for other a lot of high voltage integrated circuits, comprises controller, simulation part etc.
Can in high resolution cross-sectional transmission electron microscope (TEM), see by polysilicon 2/ interlayer insulating film/polysilicon 2 interfaces that the inventive method is produced, the results are shown in Figure 3.As a comparison, Fig. 1 and Fig. 2 show the result of other method, can clearly be seen that from these figure, be very level and smooth by polysilicon 2/ interlayer insulating film provided by the invention/polysilicon 1 interface, more than art methods provide level and smooth.Shown in these microphotos, the IEEE Electron Dev of Faraone, in the argumentation of article (Fig. 9,10) as if the polysilicon to 620 ℃ have 300～500
Interface roughness (on polysilicon 1/ interfacial dielectric layer), and use in the situation of 560 ℃ of amorphous silicons, interface roughness is 120-220
, the microphoto of Fig. 3 shows by contrast, using interface roughness of the present invention is that a very little deviation is affirmed less than 55
, more like 10
Fig. 4 A～4C shows the step of making EPROM unit sample by the present invention.The epitaxial structure of preferably a kind of P of substrate 10(on P) tool N bit line (bitline) diffusion 12, the latter is topped by 14 in self aligned thick oxide (SATO) district, growth is to provide the gate oxide of famos transistor in the space of one oxide 16 that approaches between conventional (bitline) oxide 14, then deposition forms the silicon of 1 layer 18 of polysilicon, but this layer is not (at this moment waiting) polycrystal, but unbodied.This layer mixed impurity to reach the conductance of hope, make figure and etching with routine techniques then, to obtain structure shown in Figure 4.
Then, the insulating barrier 20 of deposition one deck sandwich construction shown in Fig. 4 B, preferably a kind of sandwich construction of this insulating barrier 20, its the top layer high-temperature oxydation step method of the most handy short time converts composite insulation layer to, and this just will obtain the sandwich structure of oxide/nitride/oxide of mentioning above a kind of.But, also can use much other insulation layer structures (single or multiple lift, compound material or fairly simple component), as long as amorphous silicon layer 18 does not have complete oxidation.Concerning a kind of advanced person's EPROM unit, the spacing between the diffusion region 12 is about 1 micron, and used thickness of insulating layer is (as described above) about 400 preferably
Oxide thickness of equal value also can be used other thickness (preferably less) certainly.
After insulating barrier 20 is in place, this structure is preferably carried out a high annealing to allow silicon layer 18 recrystallizations and to reduce its resistivity.After this step, layer 18 will be polycrystal (though it is unbodied at first), and insulating barrier 20 now preferably peels off and grows from periphery and is used for the gate oxide of peripheral devices.Then carry out the deposition of 2 layer 22 of polysilicon: 2 layers of diffusion method the most handy of polysilicon are mixed; make figure and etching [applying hierarchical etching then; it will be continuously etching polysilicon 2, insulating barrier 20,1 layer of 18(of polysilicon this be to know in the EPROM manufacturing technology)]; then, deposit interlayer insulating film, contact etch, metal etch, the outer deposition of protection etc. with conventional processing step.
Certainly, 2 layers of polysilicons are silicon not necessarily, and it can be a kind of metal or a kind of sandwich construction.Silicide and polysilicon/silicide sandwich structure also can be used.The present invention also is included in the position of using polysilicon in the present processing step, adopts the sandwich structure in the future with similar deposition and electrical characteristic.In addition, 1 layer of mixture that also can comprise some other material of polysilicon is as long as this layer is unbodied when deposition and contains a big silicon percentage.
Therefore, the invention provides very crucial advantage, i.e. layer 18 and 20, the interface between the layer 20 and 22 is very level and smooth, and is much more level and smooth than interface of the prior art, do not increase the complexity of technology simultaneously.
Those skilled in the art knows that the present invention can improve and variation in wide scope, and except that following claims regulation, its scope is not limited.
Claims (3)
1, a kind of Nonvolatile memery unit comprises:
A. a transistor channel region;
B. one be superimposed upon on the described transistor channel region and with the capacitively coupled floating grid of this transistor channel region; It is characterized in that:
When c. the capacitive control utmost point that is coupled to said floating grid was coupled to said floating grid by an insulating barrier capacitive, the maximum partial deviations that this insulating barrier has perpendicular to said interface were 10% of its layer thickness.
2,, it is characterized in that the maximum partial deviations that said insulating barrier has perpendicular to said interface are 80 of its layer thickness according to the memory cell of stating of claim 1
3, a kind of method of making Nonvolatile memery unit comprises following each step:
(a) provide a kind of Semiconductor substrate;
(b) on the non-volatile memory transistor preposition, form gate insulator;
It is characterized in that:
(c) first conductive layer that deposits on the precalculated position of said non-volatile memory transistor contains the silicon atom of 50%～100% non-crystalline (non-polycrystalline);
(d) deposition one layer insulating on said first conductive layer;
(e) deposition second conductive layer on above-mentioned insulating barrier;
(f) on the precalculated position of said non-volatile memory transistor, said first and second conductive layers are made figure, make said first conductive layer form a kind of floating grid, said second conductive layer forms a kind of control utmost point.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US84668386A | 1986-04-01 | 1986-04-01 | |
| US846683 | 1986-04-01 | ||
| US07/102,505 US4806519A (en) | 1986-09-30 | 1987-09-29 | Catalyst for purifying motor vehicle exhaust gases and process for producing the catalyst |
Related Parent Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN87102505A Division CN1007680B (en) | 1986-04-01 | 1987-03-31 | Integrated circuit with smooth interface over polysilicon |
| CN87102505 Division | 1989-10-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1043408A CN1043408A (en) | 1990-06-27 |
| CN1030593C true CN1030593C (en) | 1995-12-27 |
Family
ID=26799443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 89108268 Expired - Fee Related CN1030593C (en) | 1986-04-01 | 1989-10-28 | Nonvolatile memory and method of manufacturing thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1030593C (en) |
-
1989
- 1989-10-28 CN CN 89108268 patent/CN1030593C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1043408A (en) | 1990-06-27 |
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