CN103035733A - High-voltage metal oxide semiconductor (MOS) transistor structure and manufacturing method thereof - Google Patents
High-voltage metal oxide semiconductor (MOS) transistor structure and manufacturing method thereof Download PDFInfo
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Abstract
Disclosed are a high-voltage metal oxide semiconductor (MOS) transistor structure and a manufacturing method of the high-voltage MOS transistor structure. Gate polysilicon is arranged on a position between a first lightly-doped region and a second lightly-doped region, and the gate polysilicon is separated from a middle well region through gate oxides. A first potential connection well region abuts against a first side portion, and a second potential connection well region abuts against a second side portion. A first deep well, a first separating well region and a second separating well region, and the first lightly doped region and the second lightly doped region are provided with a first doping type. A middle well region, a first side portion region, a second side portion region, and the first potential connection well region and the second potential connection well region are provided with a second doping type. The first potential connection well region and the first lightly doped region are separated by a first oxide separating region. The second potential connection well region and the second lightly doped region are separated by the second oxide separating region. The first separating well region abuts against the first potential connection well region, and the second separating well region abuts against the second potential connection well region. A third oxide separating region and a fourth oxide separating region are respectively arranged on the upper portions of the first separating well region and the second separating well region.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to a kind of high pressure MOS transistor structure that is arranged symmetrically with and manufacture method thereof.
Background technology
MOS (Metal-Oxide-Semiconductor, Metal-oxide-semicondutor) field-effect transistor is the abbreviation of metal-oxide semiconductor fieldeffect transistor, and it controls its conductive capability by the electric field strength that changes the applied voltage generation.According to the difference of conduction type, MOS transistor can be divided into N raceway groove and P raceway groove two large classes.
Along with the integrated circuit fabrication process level enters the deep-submicron epoch of integrated circuit live width, the MOS element in the integrated circuit all adopts lightly-doped drain zone structure (Lightly Doped Drain, LDD).Lightly-doped drain zone structure is that MOS transistor is in order to weaken the drain region electric field and then to improve a kind of structure that the hot electron degradation effect is taked.Specifically, lightly-doped drain zone structure near near the drain electrode a low-doped drain region being set, allows also receiving portion component voltage of this low-doped drain region in raceway groove, and this structure can prevent the hot electron degradation effect.
Be integrated in standard CMOS process, the well region that injects (linking bulk potential) and be used to form isolation is leaked in the source of be used for the gate oxide level of the common shared logic device of the MOS transistor that comprises lightly-doped drain zone structure that the high voltage low resistance uses, N trap or P trap being linked current potential.
But, owing to use the very thin gate oxide level of logical device to require simultaneously the high voltage low resistance, stern challenge appears so puncture (Gated diode breakdown), inferior surface leakage (sub-surfaceleak), source drain breakdown (S/D punch) and source leakage tagma puncture problems such as (S/D bulk breakdown) for gated diode, and these problems interact, thereby have brought more complicated consideration for design and the making of high-voltage MOS transistor.
Fig. 1 schematically shows the mos transistor structure (high-voltage MOS transistor) according to prior art.As shown in Figure 1, high pressure MOS transistor structure according to prior art comprises the first deep trap 1 that is arranged in the silicon chip, be arranged in the second well region 2, the first isolation well region 31 in the first deep trap 1 and be connected isolation well region 32, the first current potential connection well region 41 and the current potential connection well region 42 of being connected, be arranged in the first light doping section 51 and the second light doping section 52 in the second well region 2, be arranged in the grid polycrystalline silicon 7 on the silicon chip surface; Described grid polycrystalline silicon 7 is arranged in the position between the first light doping section 51 and the second light doping section 52, and wherein said grid polycrystalline silicon 7 separates by gate oxide 61 and the second well region 2 that is arranged in the silicon chip top layer; The first current potential connects well region 41 and is connected current potential connection well region 42 all in abutting connection with the second well region 2.Wherein, the first current potential connection well region 41 and the first light doping section 51 separate by the first oxide isolation zone 62; The second current potential connects well region 42 and the second light doping section 52 separates by the second oxide isolation zone 63.In addition, the first isolation well region 31 is connected well region 41 adjacency with the first current potential, and the second isolation well region 32 is connected well region 42 adjacency with the second current potential.Trioxide isolated area 64 and tetroxide isolated area 65 have been arranged respectively in the first isolation well region 31 and the second isolation well region 32 tops.
In addition, the first current potential connection well region 41 is connected to the first contact hole C1 by its surperficial heavily doped region; The second current potential connects well region 42 and is connected to the 4th contact hole C4 by its surperficial heavily doped region, thereby the second well region 2 of N trap or P trap can be linked corresponding current potential.The first light doping section 51 is connected to the second contact hole C2 by its surperficial heavily doped region; The second light doping section 52 is connected to the 3rd contact hole C3 by its surperficial heavily doped region; Thus, can apply source voltage and drain voltage to the first light doping section 51 and the second light doping section 52 as the source and drain areas of MOS transistor.Grid polycrystalline silicon 7 is connected to the 5th contact hole C5, thereby can apply grid voltage to the grid of MOS transistor.
But the effect such as the tagma puncture is leaked in gated diode puncture, inferior surface leakage, source drain breakdown and source in the above-mentioned high pressure MOS transistor structure can influence each other.Therefore, hope can provide a kind of interactional technical scheme of eliminating between gated diode puncture, inferior surface leakage, source drain breakdown and the source leakage tagma puncture.
Summary of the invention
Technical problem to be solved by this invention is for having defects in the prior art, a kind of interactional high pressure MOS transistor structure that can eliminate between gated diode puncture, inferior surface leakage, source drain breakdown and the source leakage tagma puncture being provided.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of mos transistor structure (for example high pressure MOS transistor structure), it comprises: be arranged in the first deep trap in the silicon chip; Be arranged in middle part well region, the first sidepiece, the second sidepiece, the first isolation well region in the first deep trap and be connected that isolation well region, the first current potential connect well region and the current potential of being connected connects well region, the first light doping section and the second light doping section; Be arranged in the grid polycrystalline silicon on the silicon chip surface; Described grid polycrystalline silicon is arranged in the position between the first light doping section and the second light doping section, and described grid polycrystalline silicon separates by gate oxide and the middle part well region that is arranged in the silicon chip top layer; Wherein, the first isolation well region and the second isolation well region are arranged symmetrically with respect to described grid polycrystalline silicon; The first current potential connects well region and is connected current potential and connects well region and be arranged symmetrically with respect to described grid polycrystalline silicon; The first lateral zones and the second lateral zones are arranged symmetrically with respect to described grid polycrystalline silicon; The first light doping section and the second light doping section are arranged symmetrically with respect to described grid polycrystalline silicon; Wherein, the first current potential connects well region in abutting connection with the first sidepiece, and the second current potential connects well region in abutting connection with the second sidepiece; Wherein, the first deep trap, the first isolation well region and the second isolation well region and the first light doping section and the second light doping section have the first doping type; Middle part well region, the first lateral zones, the second lateral zones, the first current potential connection well region and the current potential of being connected connect well region and have the second doping type; And the first current potential connects well region and the first light doping section separates by the first oxide isolation zone; The second current potential connects well region and the second light doping section separates by the second oxide isolation zone; The first isolation well region is connected the well region adjacency with the first current potential, and the second isolation well region is connected the well region adjacency with the second current potential; Trioxide isolated area and tetroxide isolated area have been arranged respectively in the first isolation well region and the second isolation well region top.
Preferably, gate oxide, the first oxide isolation zone, the second oxide isolation zone, trioxide isolated area and tetroxide isolated area form integral body.
Preferably, the first doping type is that N-type is mixed, and the second doping type is that the P type mixes.
Preferably, the first current potential connection well region is connected to the first contact hole by its surperficial heavily doped region; The second current potential connects well region and is connected to the 4th contact hole by its surperficial heavily doped region.
Preferably, the first light doping section is connected to the second contact hole by its surperficial heavily doped region; The second light doping section is connected to the 3rd contact hole by its surperficial heavily doped region; Grid polycrystalline silicon is connected to the 5th contact hole.
Preferably, be formed with surperficial heavily doped region by the first isolation well region, the first deep trap and the formed isolated area of the second isolation well region, thereby be connected to corresponding the 6th contact hole and the 7th contact hole by surperficial heavily doped region separately.
Preferably, the middle part well region is the P trap of logic process; The first lateral zones and the second lateral zones are the formed P traps of new mask; And raceway groove mainly is that the middle part well region by logic process is consisted of.
Preferably, carry out one or many by new mask and inject to form the P trap, and new its position of the formed P trap of mask enters the first current potential and connects well region, the first lateral zones, middle part well region, the second lateral zones, the second current potential connection well region, or enters the first current potential connection well region, the first lateral zones, the second lateral zones, the second current potential connection well region.
Preferably, form the first lateral zones and the second lateral zones in the first deep trap by two new masks and be arranged in the first light doping section and the second light doping section in the first deep trap.
In high pressure MOS transistor structure according to the present invention, the first lateral zones 22 and the second lateral zones 23 and the first light doping section and the second light doping section in the first deep trap have been formed by two new masks; The electrical characteristic of the raceway groove of resulting high pressure MOS transistor structure is similar to logical device, and this characteristic can be expected; And, resulting high pressure MOS transistor structure leak influencing each other and can eliminate between the effect of tagma puncturing such as gated diode puncture, inferior surface leakage, source drain breakdown and source, thus can be easier design accordingly and optimize for each problem.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the high pressure MOS transistor structure according to prior art.
Fig. 2 schematically shows the high pressure MOS transistor structure according to the embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
Fig. 2 schematically shows the mos transistor structure (for example high pressure MOS transistor structure) according to the embodiment of the invention.As shown in Figure 2, different from high pressure MOS transistor structure shown in Figure 1 is that the second well region 2 of the high pressure MOS transistor structure of the first embodiment is divided into three parts: middle part well region 21, the first sidepiece 22 and the second sidepiece 23.
Specifically, as shown in Figure 2, comprise according to the high pressure MOS transistor structure of the embodiment of the invention: be arranged in the first deep trap 1 in the silicon chip.
In addition, high pressure MOS transistor structure also comprises: be arranged in middle part well region 21, the first sidepiece 22, the second sidepiece 23, the first isolation well region 31 in the first deep trap 1 and be connected isolation well region 32, the first current potential connection well region 41 and the current potential connection well region 42 of being connected.
In addition, high pressure MOS transistor structure also comprises: be arranged in the first light doping section 51 and the second light doping section 52 in the first deep trap 1.
In addition, high pressure MOS transistor structure also comprises: be arranged in the grid polycrystalline silicon 7 on the silicon chip surface; Described grid polycrystalline silicon 7 is arranged in the position between the first light doping section 51 and the second light doping section 52, and described grid polycrystalline silicon 7 separates with middle part well region 21 by the gate oxide 61 that is arranged in the silicon chip top layer.
And the first isolation well region 31 and the second isolation well region 32 are arranged symmetrically with respect to described grid polycrystalline silicon 7; The first current potential connects well region 41 and is connected current potential and connects well region 42 and be arranged symmetrically with respect to described grid polycrystalline silicon 7; The first lateral zones 22 and the second lateral zones 23 are arranged symmetrically with respect to described grid polycrystalline silicon; The first light doping section 51 and the second light doping section 52 are arranged symmetrically with respect to described grid polycrystalline silicon 7.Wherein, the first current potential connects well region 41 and connects well region 42 in abutting connection with the second sidepiece 23 in abutting connection with the first sidepiece 22, the second current potentials.
Wherein, the first deep trap 1, the first isolation well region 31 and the second isolation well region 32 and the first light doping section 51 and the second light doping section 52 have the first doping type, and for example N-type is mixed.
Middle part well region 21, the first lateral zones 22 and be connected lateral zones 23, the first current potential and connect well region 41 and the current potential of being connected and connect well region 42 and have the second doping type, for example the P type mixes.
And preferably, the first current potential connects well region 41 and the first light doping section 51 separates by the first oxide isolation zone 62; The second current potential connects well region 42 and the second light doping section 52 separates by the second oxide isolation zone 63.
In addition, preferably, the first isolation well region 31 is connected well region 41 adjacency with the first current potential, and the second isolation well region 32 is connected well region 42 adjacency with the second current potential.Trioxide isolated area 64 and tetroxide isolated area 65 have been arranged respectively in the first isolation well region 31 and the second isolation well region 32 tops.
Wherein, preferably, gate oxide 61, the first oxide isolation zone 62, the second oxide isolation zone 63, trioxide isolated area 64 and tetroxide isolated area 65 form whole.
In addition, preferably, the first current potential connects well region 41 and is connected to the first contact hole C1 by its surperficial heavily doped region; The second current potential connects well region 42 and is connected to the 4th contact hole C4 by its surperficial heavily doped region.
In addition, preferably, the first light doping section 51 is connected to the second contact hole C2 by its surperficial heavily doped region; The second light doping section 52 is connected to the 3rd contact hole C3 by its surperficial heavily doped region; Thus, can apply source voltage and drain voltage to the first light doping section 51 and the second light doping section 52 as the source and drain areas of MOS transistor.
In addition, preferably, grid polycrystalline silicon 7 is connected to the 5th contact hole C5, thereby can apply grid voltage to the grid of MOS transistor.
Also can be formed with surperficial heavily doped region N3 and N4 by the first isolation well region 31, the first deep trap 1 and the second isolation well region 32 formed isolated areas, thereby can be connected to corresponding the 6th contact hole C6 and the 7th contact hole C7.
Comparatively speaking, in prior art shown in Figure 1, for logic process, the first deep trap is DNW (dark N trap),, the first isolation well region 31 and the second isolation well region 32 are NW (N traps), the first current potential connects well region 41, and to connect well region 42 are PW (P traps) with being connected current potential; For new mask, the second well region 2 is P traps, and the first light doping section 51 and the second light doping section 52 are light doping sections.And in the embodiment of the invention shown in Figure 2, middle part well region 21 is P traps (namely connect well region 41 and be connected current potential to connect well region 42 identical with the first current potential) of logic process; The first lateral zones 22 is the formed P traps of new mask with the second lateral zones 23. remainder is identical with Fig. 1.
And raceway groove of the prior art shown in Figure 1 is made of the P trap of new mask (the second well region 2); Raceway groove in the embodiment of the invention shown in Figure 2 is made of the P trap of logic process (middle part well region 21).
The new formed P trap of mask in the embodiment of the invention shown in Figure 2, requirement according to actual electrical equipment specification, can carry out one or many by new mask and inject formation, can be to enter the first current potential to connect well region 41, the first lateral zones 22, middle part well region 21, the second lateral zones 23, the second current potential connection well region 42 on the position, or enter the first current potential connection well region 41, the first lateral zones 22, the second lateral zones 23, the second current potential connection well region 42.
High pressure MOS transistor structure according to the embodiment of the invention is particularly suitable for the application of high voltage low resistance, wherein, the first light doping section 51 and the second light doping section 52 that have formed the first lateral zones 22 in the first deep trap 1 and the second lateral zones 23 (can be as requested by carry out once or a plurality of injection realizes) and be arranged in the first deep trap 1 by two new masks; The electrical characteristic of the raceway groove of resulting high pressure MOS transistor structure is similar to logical device, and this characteristic can be expected; And, resulting high pressure MOS transistor structure leak influencing each other and can eliminate between the effect of tagma puncturing such as gated diode puncture, inferior surface leakage, source drain breakdown and source, thus can be easier design accordingly and optimize for each problem.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. high pressure MOS transistor structure is characterized in that comprising:
Be arranged in the first deep trap in the silicon chip;
Be arranged in middle part well region, the first sidepiece, the second sidepiece, the first isolation well region in the first deep trap and be connected that isolation well region, the first current potential connect well region and the current potential of being connected connects well region, the first light doping section and the second light doping section;
Be arranged in the grid polycrystalline silicon on the silicon chip surface; Described grid polycrystalline silicon is arranged in the position between the first light doping section and the second light doping section, and described grid polycrystalline silicon separates by gate oxide and the middle part well region that is arranged in the silicon chip top layer;
Wherein, the first isolation well region and the second isolation well region are arranged symmetrically with respect to described grid polycrystalline silicon; The first current potential connects well region and is connected current potential and connects well region and be arranged symmetrically with respect to described grid polycrystalline silicon; The first lateral zones and the second lateral zones are arranged symmetrically with respect to described grid polycrystalline silicon; The first light doping section and the second light doping section are arranged symmetrically with respect to described grid polycrystalline silicon; Wherein, the first current potential connects well region in abutting connection with the first sidepiece, and the second current potential connects well region in abutting connection with the second sidepiece;
Wherein, the first deep trap, the first isolation well region and the second isolation well region and the first light doping section and the second light doping section have the first doping type; Middle part well region, the first lateral zones, the second lateral zones, the first current potential connection well region and the current potential of being connected connect well region and have the second doping type;
And the first current potential connects well region and the first light doping section separates by the first oxide isolation zone; The second current potential connects well region and the second light doping section separates by the second oxide isolation zone; The first isolation well region is connected the well region adjacency with the first current potential, and the second isolation well region is connected the well region adjacency with the second current potential; Trioxide isolated area and tetroxide isolated area have been arranged respectively in the first isolation well region and the second isolation well region top.
2. high pressure MOS transistor structure according to claim 1 is characterized in that, gate oxide, the first oxide isolation zone, the second oxide isolation zone, trioxide isolated area and tetroxide isolated area form integral body.
3. high pressure MOS transistor structure according to claim 1 and 2 is characterized in that, the first doping type is that N-type is mixed, and the second doping type is that the P type mixes.
4. high pressure MOS transistor structure according to claim 1 and 2 is characterized in that, the first current potential connects well region and is connected to the first contact hole by its surperficial heavily doped region; The second current potential connects well region and is connected to the 4th contact hole by its surperficial heavily doped region.
5. high pressure MOS transistor structure according to claim 1 and 2 is characterized in that, the first light doping section is connected to the second contact hole by its surperficial heavily doped region; The second light doping section is connected to the 3rd contact hole by its surperficial heavily doped region; Grid polycrystalline silicon is connected to the 5th contact hole.
6. high pressure MOS transistor structure according to claim 1 and 2, it is characterized in that, be formed with surperficial heavily doped region by the first isolation well region, the first deep trap and the formed isolated area of the second isolation well region, thereby be connected to corresponding the 6th contact hole and the 7th contact hole by surperficial heavily doped region separately.
7. according to claim 1 to the manufacture method of one of 6 described high pressure MOS transistor structures, it is characterized in that the middle part well region is the P trap of logic process; The first lateral zones and the second lateral zones are the formed P traps of new mask; And raceway groove mainly is that the middle part well region by logic process is consisted of.
8. manufacture method according to claim 7, it is characterized in that, carry out one or many by new mask and inject to form the P trap, and new its position of the formed P trap of mask enters the first current potential and connects well region, the first lateral zones, middle part well region, the second lateral zones, the second current potential connection well region, or enters the first current potential connection well region, the first lateral zones, the second lateral zones, the second current potential connection well region.
9. according to claim 7 or 8 described manufacture methods, it is characterized in that, formed the first lateral zones and the second lateral zones in the first deep trap and be arranged in the first light doping section and the second light doping section in the first deep trap by two new masks.
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| CN106158832A (en) * | 2015-04-01 | 2016-11-23 | 联华电子股份有限公司 | Semiconductor structure |
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