CN103035607B - The method of DIP arrangement in a kind of integrated block package framework and framework - Google Patents
The method of DIP arrangement in a kind of integrated block package framework and framework Download PDFInfo
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- CN103035607B CN103035607B CN201210588304.5A CN201210588304A CN103035607B CN 103035607 B CN103035607 B CN 103035607B CN 201210588304 A CN201210588304 A CN 201210588304A CN 103035607 B CN103035607 B CN 103035607B
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- block package
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Abstract
The present invention relates to integrated block package technical field, the method for particularly DIP arrangement in a kind of integrated block package framework and framework.The method is characterized in that: the pin between two DIP neighbouring arbitrarily in described framework be parallel to each other staggered.The present invention can realize DIP tight arrangement in the frame, promotes chip package efficiency.
Description
Technical field
The present invention relates to integrated block package technical field, the method for particularly DIP arrangement in a kind of integrated block package framework and framework.
Background technology
In integrated block package technique, after forming technique, the arrangement of chip as shown in Figure 1 in the frame, Fig. 1 is the arrangement schematic diagram of DIP chip in framework 4 of a mould, wherein adjacent between two DIP chip 1 be into symmetric relation relative to pin 2 relative to center line 5, this arrangement can cause there is a space 3 between the pin of adjacent chips, so not only cause the waste of frame space, and one the quantity of mould be restricted, cause chip package efficiency cannot promote always, in addition, cut in muscle forming process follow-up, this arrangement mode is easy to the damage causing pin 2, cause the lifting of chip fraction defective.
Summary of the invention
In view of this, the object of this invention is to provide the method for DIP arrangement in a kind of integrated block package framework, DIP tight arrangement in the frame can be realized, promote chip package efficiency.
The present invention adopts following scheme to realize: in a kind of integrated block package framework DIP arrangement method, it is characterized in that: the pin between two DIP neighbouring arbitrarily in described framework be parallel to each other staggered.
In an embodiment of the present invention, the end of described DIP pin has a distance D with the plastic-sealed body side of corresponding DIP.
In an embodiment of the present invention, described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.
In an embodiment of the present invention, described X is 5.
Another object of the present invention is to provide the framework of DIP arrangement in a kind of integrated block package framework.
It adopts following scheme to realize: the framework of DIP arrangement in a kind of integrated block package framework, comprises integrated block package framework, it is characterized in that: described integrated block package framework is laid with a plurality of DIP; Two neighbouring arbitrarily in described DIP, the pin between it be parallel to each other staggered.
In an embodiment of the present invention, the end of described DIP pin has a distance D with the plastic-sealed body side of corresponding DIP.
In an embodiment of the present invention, described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.
In an embodiment of the present invention, described X is 5.
Method of the present invention and framework are by arranging the pin staggered parallel between two between adjacent chips, fully utilize the space of framework, not only avoid the problem of chip pin at the easy clubfoot of following process process, and wait until significant increase compared to mode packaging efficiency in the past.
Accompanying drawing explanation
Fig. 1 is the DIP chip arrangement schematic diagram in the frame of an existing mould.
Fig. 2 is embodiment of the present invention DIP arrangement schematic diagram in the frame.
Fig. 3 is that in the embodiment of the present invention, two neighbouring DIP arrange schematic diagram.
Wherein, 1 is DIP, and 2,21,22 is pin, and 3 is space, and 4 is framework, line centered by 5,
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.
As shown in Figure 2, the present embodiment provides the method for arrangement of DIP in a kind of integrated block package framework, it is characterized in that: the pin between two DIP neighbouring arbitrarily in described framework be parallel to each other staggered.
Refer to Fig. 3, the end of above-mentioned DIP pin has a distance D with the plastic-sealed body side of corresponding DIP.
In an embodiment of the present invention, described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.Continue referring to Fig. 2, in an embodiment of the present invention, described X is 5.The method takes full advantage of the space of framework, not only ensures that a modulus amount can be multiplied compared to technology in the past, improves packaging efficiency, and avoid DIP pin to produce clubfoot in subsequent handling.
In addition, the present embodiment also provides the framework of DIP arrangement in a kind of integrated block package framework, and please continue see in Fig. 2, figure, this framework comprises integrated block package framework 1, it is characterized in that: described integrated block package framework 4 is laid with a plurality of DIP1; Two neighbouring arbitrarily in described DIP1, the pin 2 between it be parallel to each other staggered.
Refer to Fig. 3, in an embodiment of the present invention, the end of described DIP pin has a distance D with the plastic-sealed body side of corresponding DIP, and this distance D can adjust according to actual needs.
Please continue see in Fig. 2, figure, described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.Preferably, this X is 5.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (4)
1. in integrated block package framework DIP arrangement a method, it is characterized in that: the pin between two DIP neighbouring arbitrarily in described framework be parallel to each other staggered; The end of described DIP pin has a distance D with the plastic-sealed body side of corresponding DIP; Described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.
2. the method for DIP arrangement in a kind of integrated block package framework according to claim 1, is characterized in that: described X is 5.
3. a framework for DIP arrangement in integrated block package framework, comprises integrated block package framework, it is characterized in that: described integrated block package framework is laid with a plurality of DIP; Two neighbouring arbitrarily in described DIP, the pin between it be parallel to each other staggered; The end of described DIP pin has a distance D with the plastic-sealed body side of corresponding DIP; Described framework is placed with X and arranges Y row DIP, wherein X be not less than 2 natural number, Y is natural number.
4. the framework of DIP arrangement in integrated block package framework according to claim 3, is characterized in that: described X is 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210588304.5A CN103035607B (en) | 2012-12-29 | 2012-12-29 | The method of DIP arrangement in a kind of integrated block package framework and framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210588304.5A CN103035607B (en) | 2012-12-29 | 2012-12-29 | The method of DIP arrangement in a kind of integrated block package framework and framework |
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| Publication Number | Publication Date |
|---|---|
| CN103035607A CN103035607A (en) | 2013-04-10 |
| CN103035607B true CN103035607B (en) | 2016-04-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210588304.5A Active CN103035607B (en) | 2012-12-29 | 2012-12-29 | The method of DIP arrangement in a kind of integrated block package framework and framework |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI597812B (en) * | 2015-09-15 | 2017-09-01 | Raydium Semiconductor Corp | Driving circuit and pin output order arranging method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201629330U (en) * | 2010-04-16 | 2010-11-10 | 宁波华龙电子股份有限公司 | Densely arranged integrated circuit lead frame piece |
| CN102074540A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
| CN203071057U (en) * | 2012-12-29 | 2013-07-17 | 福建福顺半导体制造有限公司 | Framework for DIP (Double In-line Package) arrangement in integrated block package frame |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6747341B2 (en) * | 2002-06-27 | 2004-06-08 | Semiconductor Components Industries, L.L.C. | Integrated circuit and laminated leadframe package |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201629330U (en) * | 2010-04-16 | 2010-11-10 | 宁波华龙电子股份有限公司 | Densely arranged integrated circuit lead frame piece |
| CN102074540A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Matrix dual in-line package (DIP) lead frame, integrated circuit (IC) packages based on frame and production method of IC packages |
| CN203071057U (en) * | 2012-12-29 | 2013-07-17 | 福建福顺半导体制造有限公司 | Framework for DIP (Double In-line Package) arrangement in integrated block package frame |
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| CN103035607A (en) | 2013-04-10 |
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