CN103035529A

CN103035529A - Method for improving electric leakage in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS)

Info

Publication number: CN103035529A
Application number: CN2012101801192A
Authority: CN
Inventors: 遇寒
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2012-06-04
Filing date: 2012-06-04
Publication date: 2013-04-10

Abstract

The invention discloses a method for improving electric leakage in a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS). The method comprises the steps 1, after a polycrystalline silicon gate is etched to be formed, a first oxide layer is deposited around the surface of a sacrifice oxide layer and the polycrystalline silicon gate; 2, the deposited first oxide layer is etched with a dry method to form a polycrystalline silicon grid lateral wall; 3, the sacrifice oxide layer on two side of the grid is removed in a wet method; and 4, a source drain injection and lateral wall process is carried out to finish the polycrystalline silicon grid lateral wall. The method is simple to achieve, damage on plasma polymers caused by dry method etching is reduced, and electric leakage is reduced. After an etched grid is recovered with the method, electric leakage can be reduced at least one magnitude order on the original base, and other parameters are not affected.

Description

Method for improving electric leakage in RF LDMOS

Technical Field

The present invention relates to a method for improving leakage in the field of semiconductor integrated circuits, and more particularly, to a method for improving leakage in an RF LDMOS (radio frequency laterally diffused metal oxide semiconductor).

Background

The P-type RF LDMOS is mainly applied to switches and has high requirements on resistance and electric leakage. In a complex process, ionic polymer damage caused by etching cannot be avoided, and the electric leakage caused by the ionic polymer damage cannot be ignored. As is known, a uniform plasma polymer on a silicon wafer surface does not generate surface charges, but for complex image etching, such as gate etching, sidewall etching and the like, forward charges are generated in a small local range of etching, conversely, reverse charges are formed in a relatively large etching space region, and if the plasma polymer is uniformly distributed, a current cannot be generated due to a forward electric field and a reverse electric field in general, but actually, the plasma polymer is not uniformly distributed, and charges are trapped in a gate oxide layer on the silicon wafer surface, and charges flow (as shown in fig. 1), so that a leakage current between a gate and a drain or a source is generated (as shown in fig. 2).

In order to reduce the leakage of the device, the plasma polymer and the damage caused by the plasma polymer are reduced and removed as much as possible. However, the existing RF LDMOS product process does not have a step of repairing the damage caused by etching to reduce the leakage.

Disclosure of Invention

The invention aims to provide a method for improving electric leakage in an RF LDMOS. By the method, the damaged sacrificial oxide layer can be removed, interface state charges, dangling bonds and the like can be reduced, and electric leakage is reduced.

To solve the above technical problem, the method for improving leakage in an RF LDMOS of the present invention includes the steps of:

(1) after the polysilicon gate is etched and formed, depositing a first oxide layer on the surface of a sacrificial oxide layer (a second oxide layer) and the periphery of the polysilicon gate (comprising two side surfaces of the polysilicon gate and the surface of the polysilicon gate);

(2) etching the deposited first oxide layer by a dry method to form a polysilicon gate side wall;

(3) removing the sacrificial oxide layer (the second oxide layer) on two sides of the grid electrode by a wet method;

(4) and performing source-drain injection and a side wall process to finish the manufacture of the RF LDMOS.

In the step (1), the deposition method includes: low-pressure chemical vapor deposition; a first oxide layer comprising: a silicon oxide layer; the thickness of the first oxide layer is 200-500 angstroms.

In the step (2), the thickness range of the side wall is 150-400 angstroms.

In order to reduce electric leakage as much as possible, the damage brought by plasma polymers brought by dry etching needs to be reduced, so that the method has the advantages of simple process realization, reduction of the damage brought by the plasma polymers brought by the dry etching and electric leakage reduction. Through the process repair after the gate etching, the electric leakage can be reduced by at least one order of magnitude on the original basis, and no influence is generated on other parameters, namely, other performances of the device are not influenced.

Drawings

The invention will be described in further detail with reference to the following detailed description and accompanying drawings:

FIG. 1 is a schematic charge flow diagram of a silicon wafer surface;

FIG. 2 is a schematic structural diagram of a conventional polysilicon gate etch; wherein,

the icon represents the location of the electrical leakage;

FIG. 3 is a schematic diagram of a structure after the method of the present invention has been employed;

FIG. 4 is a schematic diagram of the structure after polysilicon gate etching;

FIG. 5 is a schematic diagram of the structure after etching the polysilicon gate and depositing silicon oxide by low pressure chemical vapor deposition;

FIG. 6 is a schematic structural view of a small sidewall formed after dry etching away deposited silicon oxide;

fig. 7 is a graph comparing breakdown voltages of RF LDMOS single-transistor devices fabricated using a conventional process and the present invention.

The reference numerals in the figures are illustrated as follows:

the structure comprises an N-type silicon substrate 1, an N-type epitaxial layer 2, a P-type polycrystalline silicon deep groove 3, a low-voltage P-type trap 4, an N-type doped channel region 5, a gate oxide layer 6, a polycrystalline silicon gate 7, a gate metal silicide 8, a polycrystalline silicon gate side wall 9, a sacrificial oxide layer 10 and low-voltage chemical vapor deposition silicon oxide 11.

Detailed Description

The method for improving the leakage in the RF LDMOS comprises the following steps:

(1) depositing a silicon oxide layer, a polysilicon gate layer and a gate metal silicide layer in sequence on the N-type epitaxy 2, etching to form a polysilicon gate (as shown in figure 3), and depositing a silicon oxide layer 11 (as shown in figure 4) on the surface of the sacrificial oxide layer 10, the two side surfaces of the polysilicon gate and the surface of the polysilicon gate by using a low-pressure chemical vapor deposition method, wherein the thickness of the silicon oxide layer is 200-500 angstroms;

wherein, the sacrificial oxide layer is made of silicon oxide;

(2) dry etching the silicon oxide layer 11 deposited on the surface of the sacrificial oxide layer 10 and the surface of the polysilicon gate to form a polysilicon gate side wall 9 (as shown in fig. 5), wherein the thickness of the polysilicon gate side wall 9 is 150-400 angstroms;

(3) removing the sacrificial oxide layer 10 (shown in fig. 6) on both sides (active region) of the gate by a conventional wet method;

(4) and performing source-drain injection and side wall processes according to a conventional process to finish the manufacture of the RF LDMOS.

According to the invention, after the gate etching, the process step of improving the damage brought by the plasma polymer is added, namely, the steps are added after the polysilicon etching, so that the small silicon oxide layer side wall is formed, and the gate oxide layer can be protected. Meanwhile, after the remaining sacrificial oxide layer is removed by a wet method, the operation can still be carried out according to the normal process steps to prepare the RF LDMOS.

After the RF LDMOS product is manufactured by adopting a conventional process (before optimization) and the method (after optimization) of the invention, the breakdown voltage of the product is detected, as shown in FIG. 7, by adopting the method of the invention, namely, by adding a 3-step process, the damage caused by gate etching is reduced, and the electric leakage of a product device can be reduced by at least one order of magnitude, and simultaneously, other performances of the product are not influenced, therefore, the invention can effectively reduce the damage caused by etching, reduce the electric leakage of the product, and can not influence other performances of the device.

Claims

1. A method for improving leakage in an RF LDMOS, comprising the steps of:

(1) after the polycrystalline silicon grid electrode is formed by etching, depositing a first oxidation layer on the surface of the sacrifice oxidation layer and around the polycrystalline silicon grid electrode;

(3) removing the sacrificial oxide layers on the two sides of the grid electrode by a wet method;

2. The method of claim 1, wherein: in the step (1), the periphery of the polysilicon gate includes: two side surfaces of the polysilicon gate and the surface of the polysilicon gate;

a method of deposition comprising: low pressure chemical vapor deposition.

3. The method of claim 1, wherein: in the step (1), the first oxide layer includes: a silicon oxide layer.

4. The method of claim 3, wherein: in the step (1), the thickness of the first oxide layer is 200-500 angstroms.

5. The method of claim 1, wherein: in the step (2), the thickness of the side wall is 150-400 angstroms.