CN104952723A - Manufacturing method of gate sidewall layer and manufacturing method of MOS device - Google Patents

Abstract

The present application provides a method for manufacturing a gate sidewall layer and a method for manufacturing a MOS device. The gate sidewall layer fabrication method comprises the following steps: depositing a dielectric layer on a substrate with a gate; performing dry etching to remove the top dielectric layer of the gate, and thinning the gate sidewall and the dielectric layer on the surface of the substrate ; Deposit photoresist on the top of the gate; perform wet etching to further thin the dielectric layer on the sidewall of the gate and the surface of the substrate; remove the photoresist. The manufacturing method of the MOS device includes: providing a semiconductor substrate, preparing a source electrode, a drain electrode, and a gate on the substrate; Prepared; P or N regions are formed under the source and drain electrodes by deep ion implantation. The manufacturing method provided in the present application avoids damage to the silicon substrate during the dry etching process of the sidewall layer of the gate, and reduces the generation of leakage current.

Description

Fabrication method of gate sidewall layer and fabrication method of MOS device

technical field

The present application relates to an etching process of a semiconductor integrated circuit, in particular to a method for manufacturing a gate sidewall layer and a method for manufacturing a MOS device.

Background technique

With the rapid development of semiconductor integrated circuit technology, semiconductor chips are developing towards higher component density and higher integration, enabling semiconductor devices to achieve faster computing speeds and greater data storage capacity. At present, the manufacturing technology of semiconductor devices has entered the process of 32nm or even 18nm, the minimum feature size of the gate width has reached 45nm or even smaller, and the length of the channel below it is also continuously decreasing.

A MOS transistor consists of a source, a drain, a metal silicide barrier layer (SAB), a gate, and gate sidewall layers. However, in the manufacturing process of MOS transistors, when the sidewall layer of the gate is dry-etched, it is easy to damage the source-drain structure in the silicon substrate, resulting in leakage current, which limits the MOS Applications of transistors in semiconductor devices.

In order to reduce the leakage current caused by the etching of the sidewall layer, the following methods are mainly used at present: one, reducing the time of dry etching, so that the SAB has a larger thickness, so as to reduce damage to the silicon substrate. However, too thick SAB will affect the subsequent process window; another method is to perform light doping under the source and drain to form a lightly doped region (LDD) with high resistivity, thereby reducing the generation of leakage current; The third is to add a heat treatment process after dry etching the gate sidewall layer, so that the damage caused by the dry etching process to the silicon substrate can be recovered, but the heat treatment process will cause the position between the devices to change , affecting the stability of the device.

Specifically, a method for NMOS devices with low GIDL current is disclosed in Chinese patent application publication number CN102867755A. _In this method, the threshold voltage is adjusted through the BF2 ion implantation process after the formation of the P well, BF2 is implanted into the channel region under the _SiO2 /Si interface, F is used to suppress the diffusion of B _ions , and the channel region and the drain electrode are reduced. The lateral electric field can reduce the GIDL current without affecting the device performance. The process steps of the method are: performing well implantation on the wafer to form a P well, and performing BF2 implantation _on the P well to adjust the threshold voltage; sequentially depositing a gate insulating layer and a gate polysilicon layer on the surface of the wafer, and etching to remove excess polysilicon layer to form the gate; prepare the first sidewall layer around the gate, and lightly dope the device after forming the first sidewall layer to form a lightly doped source-drain structure; prepare the second sidewall around the first sidewall layer layer, after forming the second sidewall layer, performing source and drain implantation to form source and drain electrodes. Although this method can reduce the lateral electric field between the channel region and the drain to a certain extent and reduce the generation of leakage current, this method cannot reduce the leakage current caused by the etching of the sidewall layer of the gate, and cannot completely solve the problem. Gate leakage current damages MOS devices.

A Chinese patent application with publication number CN101459140 discloses an embedded EEPROM process method using SAB to increase the width of the sidewall layer. The process steps of the method are: after the polysilicon gate is formed and the LDD is implanted, deposit an oxide film and a nitride film, etch the nitride film at the bottom of the gate to form a sidewall layer; deposit an oxide film as the first layer of silicide barrier layer; performing source and drain implantation; depositing a layer of silicon nitride as the second layer of silicide barrier layer, etching and removing the second layer of silicide barrier layer and the first layer of silicide barrier layer, and finally forming silicide. Although this method can reduce the leakage of the device to a certain extent, it cannot reduce the lateral electric field between the channel region and the drain, and cannot completely solve the damage to the MOS device caused by the gate leakage current.

Contents of the invention

In order to solve the problem of gate leakage current in existing semiconductor devices, the present application provides, on the one hand, a method for fabricating a gate sidewall layer. The manufacturing method avoids damage to the substrate caused by dry etching of the gate side wall layer, thereby reducing the generation of leakage current and improving the stability of the device.

One aspect of the present application provides a method for fabricating a gate sidewall layer, the fabrication method comprising the following steps: depositing a dielectric layer on a substrate with a gate; performing dry etching to remove the top dielectric layer of the gate, and Thin the dielectric layer on the gate sidewall and substrate surface; deposit photoresist on top of the gate; perform wet etching to further thin the dielectric layer on the gate sidewall and substrate surface; then remove the photoresist glue.

Further, in the above manufacturing method, the dielectric layer includes one or more silicon oxide layers and/or silicon nitride layers.

Further, in the above manufacturing method, after the dry etching is completed, the thickness of the dielectric layer on the substrate surface is greater than

Further, in the above manufacturing method, the sputtering power for dry etching is 100-300 watts, and the time for dry etching is 50-70 seconds.

Further, in the above manufacturing method, the etchant used in the wet etching process is HF etchant.

Further, in the above manufacturing method, the concentration of the HF etching solution is 0.1%-3%.

Further, in the above manufacturing method, after wet etching is completed, the thickness of the dielectric layer on the surface of the substrate is

Further, in the above manufacturing method, after the dry etching is completed, a rapid annealing process is further performed.

Another aspect of the present application is to provide a method for manufacturing a MOS device, the method comprising: providing a semiconductor substrate, preparing a source, a drain, and a gate on the substrate; forming a sidewall on the gate layer, wherein the sidewall layer is prepared by the method for fabricating the gate sidewall layer described above in the present application; a P well or N well is formed under the source and drain by deep ion implantation.

Further, the above manufacturing method includes: providing a semiconductor substrate, preparing a source, a drain, and a gate on the substrate; depositing a dielectric layer on the substrate and the gate, and performing an ion implantation process under the source and the drain Form a P+ lightly doped region; perform dry etching to remove the top dielectric layer of the gate, and thin the dielectric layer on the sidewall of the gate and the substrate surface; perform ion implantation on the semiconductor substrate to form an N well; perform rapid annealing; Deposit photoresist on top of the gate; perform wet etching to further thin the dielectric layer on the sidewall of the gate and the surface of the substrate; remove the photoresist; and form P under the source and drain by deep ion implantation trap.

Further, in the above manufacturing method, the semiconductor substrate may be N-type or P-type, and the sidewall layer of the gate is composed of one or more layers of silicon oxide and/or silicon nitride.

Furthermore, the above manufacturing method further includes: contact hole preparation, metallization wiring, deposition of a passivation layer, and subsequent lead connection and packaging processes.

It can be seen from the above technical solutions that the present application implements etching of the gate sidewall layer by adding a wet etching process after the dry etching process. The key of this etching method is to use wet etching to etch and thin the dielectric layer on the side wall of the gate and the surface of the substrate, so as to avoid damage to the substrate caused by dry etching. By using the etching method provided in the present application, the lateral electric field between the channel region and the drain is reduced, and the generation of leakage current is reduced, thereby overcoming the technical drawbacks caused by the existing etching process.

Description of drawings

The drawings constituting a part of the present invention are used to provide a further understanding of the present invention, and the schematic embodiments and descriptions of the present invention are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:

FIG. 1 shows a schematic flow chart of a method for fabricating a gate sidewall layer provided in an embodiment of the present application; and

FIG. 2 shows a schematic flowchart of a method for fabricating a MOS device provided in an embodiment of the present application.

Detailed ways

The technical scheme of the present application will be described in detail below in conjunction with the specific implementation of the present application, but the following examples are only used to understand the present application, and cannot limit the present application. The embodiments in the present application and the features in the embodiments Combinable with each other, the application can be implemented in many different ways as defined and covered by the claims.

It can be seen from the background technology that the existing semiconductor devices formed by dry etching the gate sidewall layer have the problem of gate leakage current. The inventors of the present application have conducted research on the above problem. A wet etching process is creatively added to realize the etching of the gate sidewall layer without destroying the source-drain structure in the substrate and avoiding the generation of gate leakage current. The inventors found that the lateral electric field between the channel region and the drain of the semiconductor device obtained by the above method is weakened, which reduces the generation of leakage current and can improve some performances of the semiconductor device.

The fabrication method of the gate sidewall layer provided by this application includes the following steps: depositing a dielectric layer on a substrate with a gate; performing dry etching to remove the top dielectric layer of the gate, and thinning the gate sidewall and the substrate A dielectric layer on the bottom surface; depositing photoresist on the top of the gate; performing wet etching to further thin the sidewall of the gate and the dielectric layer on the substrate surface; and then removing the photoresist.

FIG. 1 shows a schematic flowchart of a method for fabricating a gate sidewall layer provided in the present application. The method for fabricating the gate sidewall layer provided by the present application will be further explained below with reference to FIG. 1 .

First, a dielectric layer is deposited on the substrate with the gate. In the subsequent preparation process, the above-mentioned dielectric layer will form a gate side wall layer after undergoing dry and wet etching processes. Therefore, the structure forming the dielectric layer may be one or more layers, and the material forming the dielectric layer may be a silicon oxide layer or a silicon nitride layer. The thickness and material of the formed dielectric layer can be selected according to the required thickness of the sidewall layer and the conditions of the subsequent dry etching. Preferably, the dielectric layer includes multiple silicon nitride layers or silicon oxide layers, or a multi-layer structure in which silicon nitride layers and silicon oxide layers are alternately formed.

The above-mentioned semiconductor substrate may be a lightly doped N-type substrate or a P-type substrate, the dopant atoms are boron, phosphorus or arsenic, and the doping process includes conventional technical processes such as ion implantation and diffusion. The formation process of the above-mentioned gate may be: depositing an oxide layer on the substrate, then depositing the gate layer, and forming the gate through processes such as photolithography and wet etching.

After completing the step of depositing a dielectric layer on the substrate with the gate, performing dry etching to remove the top dielectric layer of the gate, and thinning the dielectric layer on the sidewall of the gate and the surface of the substrate. The above dry etching process may be plasma etching, ion bombardment, or reactive ion etching. In a specific embodiment provided by the present application, plasma etching is used for dry etching, and plasma is used to bombard the surface of the dielectric layer to knock out atoms of the dielectric layer material. Since dry etching may damage the substrate surface and may cause gate leakage current, the rate of dry etching can be controlled according to the thickness of the dielectric layer and the thickness of the pre-formed gate sidewall layer. Further, the etching rate can be controlled by controlling the sputtering power and etching time of dry etching. Preferably, in a preferred embodiment of the present application, the dry etching process conditions are: the main etching gases are CF ₄ and CHF ₃ , the sputtering power is 100-300 watts, and the etching time is 50-70 seconds. More preferably, after the dielectric layer is etched by dry method, the thickness of the residual dielectric layer on the substrate surface needs to be greater than In order to ensure that the substrate will not be damaged during the dry etching process.

In a specific implementation manner provided by the present application, after performing the above dry etching, a rapid annealing process may be further performed on the semiconductor device. Performing an annealing process can restore possible damage to the top of the gate caused by the dry etching process. Preferably, the annealing temperature in the above rapid annealing process is 900 to 1030° C., and the annealing time is 20 to 40 seconds.

Next, a photoresist is deposited on top of the gate. The photoresist above is used as a mask to protect the exposed top of the gate from being corroded by the wet etching solution in the next step. The above-mentioned photoresist can be deposited by spin-coating or spray-coating, and the above-mentioned process is a prior art in the art, and will not be repeated here.

Next, wet etching is performed to further thin the gate sidewall and the dielectric layer on the substrate surface. The present application breaks through the traditional idea of only using dry etching to fabricate the sidewall layer, and creatively applies dry etching and wet etching processes to the fabrication process of the gate sidewall layer. Since the dielectric layer was thinned by dry etching in the previous step, the thickness of the dielectric layer on the surface of the substrate will be more or less thinner than the thickness of the dielectric layer on the sidewall of the gate. If dry etching is continued , will inevitably cause the dielectric layer on the substrate surface to be etched away before the gate sidewall layer is formed, so that the substrate will be damaged in the subsequent etching process. The wet etching is isotropic etching, and the thickness of the lateral etching is close to the depth of the vertical etching. Therefore, replacing the dry etching process with a wet etching process can ensure that the thinned thickness of the dielectric layer on the sidewall of the gate is basically the same as the thinned thickness of the dielectric layer on the substrate surface, thereby preventing the substrate from being exposed to the etching environment. middle. The wet etching process adopted in the present application may be a conventional wet etching process condition. Preferably, in a specific embodiment, the wet etching process is: slowly immerse the gate sidewall and the dielectric layer on the substrate surface with HF etchant, so that the etchant and the gate side on the substrate The wall layer reacts for a period of time; finally, the gate sidewall layer is gradually peeled off, and the peeled product leaves the etching surface and diffuses into the solution, and is discharged with the solution. Moreover, the control of the wet etching rate can also be realized by controlling the concentration of the etchant, the reaction temperature and the reaction time. Preferably, the concentration of HF used in this application is 0.1%-3%, and the treatment time is 30-200 seconds. More preferably, after wet etching the dielectric layer, the residual dielectric layer on the substrate surface is about More preferably controlled at about.

Finally, the photoresist is removed to complete the fabrication of the entire gate sidewall. The photoresist removal method adopted here may be in DMF, or by ultrasonic removal method, since this method is a conventional technical means, it will not be repeated here.

From the above process steps, it can be seen that the contribution of the fabrication method of the gate sidewall layer provided by the present application to the prior art lies in that a wet etching process is added after the dry etching of the gate sidewall layer. The process of stripping the sidewall layer of the gate; this etching method can complete the etching of the sidewall layer of the gate without damaging the dielectric layer on the surface of the substrate, thereby reducing the gate leakage caused by the damage of the oxide layer. The generation of current improves the anti-high voltage damage performance of the device.

In addition, another aspect of the present application is to provide a method for manufacturing a MOS device. As shown in FIG. 2 , the method includes: providing a semiconductor substrate, and preparing a source, a drain, and a gate on the substrate; A sidewall layer is formed on the gate, wherein the sidewall layer is prepared by the above gate sidewall layer manufacturing method; a P well or N well is formed under the source and drain by deep ion implantation.

In a specific embodiment provided by the present application, the above-mentioned MOS device manufacturing method includes: providing a semiconductor substrate, preparing a source, a drain, and a gate on the substrate; depositing a dielectric layer on the substrate and the gate, and passing the ion The implantation process forms a P+ lightly doped region under the source and drain; performs dry etching to remove the top dielectric layer of the gate, and thins the dielectric layer on the sidewall of the gate and the surface of the substrate; ionizes the semiconductor substrate Implantation to form an N well; perform rapid annealing; deposit photoresist on the top of the gate; perform wet etching to further thin the dielectric layer on the sidewall of the gate and the surface of the substrate; remove the photoresist; and perform deep ion implantation A P-well is formed under the source and drain.

The above-mentioned deep ion implantation process provided by the present application includes the following steps: firstly, an ion implantation process window is made on the substrate through photolithography and etching processes; then, dopant atoms are implanted into the substrate through the process window to form N+ doped impurity region or P+ doped region; N well or P well is formed after rapid annealing process. Preferably, the semiconductor substrate is P-type or N-type, and the dopant atoms include boron, phosphorus or arsenic.

The manufacturing method of the MOS device described in the present application further includes: contact hole preparation, metallized wiring, deposition of a passivation layer, subsequent lead connection, packaging and other processes to complete the manufacturing of the MOS device. In the MOS device obtained by using the gate sidewall layer manufacturing method provided in the present application, the gate leakage current is significantly reduced, and the device failure damage caused by the gate leakage current is also significantly reduced.

The selective etching method provided by the present application will be further described below with specific examples.

comparative example

First, a P-type semiconductor substrate lightly doped with boron atoms is provided, and the source, drain, and polysilicon gate are prepared on the above substrate through photolithography, etching, deposition and other processes; silicon dioxide is deposited on the substrate, The silicon dioxide on the top of the gate is removed by etching to form the sidewall layer of the gate; boron atoms are implanted under the source and drain by ion implantation to form a P+ lightly doped region (LDD).

Then, the silicon dioxide (dielectric layer) on the sidewall layer of the gate and the substrate surface is etched and removed by dry etching process, and the silicon dioxide atoms are knocked out to realize the thinning of the sidewall layer. Phosphorus ion implantation is performed on the semiconductor substrate to form an N well, followed by rapid annealing. The etching process conditions are as follows: the main etching gas is CF ₄ and CHF ₃ , the sputtering power is 250 watts, the etching temperature is 60° C., and the etching time is 60 seconds.

Finally, through the deep ion implantation process, boron atoms are implanted under the source and drain and inside the N well to form a P well; a metal silicide barrier layer (SAB) is deposited between the source, drain and gate; Hole preparation, metallization wiring, deposition of passivation layer and subsequent lead connection, packaging and other processes to complete the production of MOS devices.

Perform a performance test on the prepared MOS device, and the test content includes the off current and the breakdown voltage of the gate. The off-current (Ioff) refers to the drain current when the device is in the off state. The larger the off-current means the greater the leakage of the device, which causes more unnecessary work consumption. The test method for the off current is: the source and the substrate are grounded, the gate is also grounded, and the drain is connected to 1.1 times the operating voltage. At this time, the measured drain current is the off current. See Table 1 for the test results. The gate breakdown voltage test method is: the substrate is grounded, and the gate voltage is applied from 0. When the gate current suddenly increases, the gate voltage at this time is the breakdown voltage. See Table 2 for the test results.

Table 1 shows the off current at different locations on the surface of the test chip. It can be seen from Table 1 that the off-current at the middle of the chip is relatively large, its value exceeds 1 mA, and the highest value reaches 19.66 mA; relatively speaking, the off-current at the edge of the chip is relatively small. This shows that the leakage current of the MOS device prepared by the traditional process is relatively large, which has a great influence on the stability of the device. Table 2 shows the gate breakdown voltage at different locations on the surface of the test chip. As shown in Table 2, the gate breakdown voltage at most of the chip surface is 5 volts, and only the gate breakdown voltage at the bottom edge of the chip exceeds 18 volts. The test results show that the gate breakdown voltage of the MOS device prepared by the traditional process is low, which cannot meet the requirements of the existing device.

Table 1

Table 2

Example

First, a P-type semiconductor substrate lightly doped with boron atoms is provided, and the source, drain, and polysilicon gate are prepared on the above substrate through photolithography, etching, deposition and other processes; silicon dioxide is deposited on the substrate, Boron atoms are implanted under the source and drain through an ion implantation process to form a P+ lightly doped region (LDD).

Using dry etching to etch the silicon dioxide layer on the top of the gate, the gate sidewall layer and the substrate surface, the silicon dioxide atoms are knocked out, the silicon dioxide layer on the top of the gate is removed and the sidewall layer is realized of thinning. The etching process conditions are as follows: the main etching gas is CF ₄ and CHF ₃ , the sputtering power is 250 watts, the etching temperature is 60° C., and the etching time is 60 seconds. Phosphorus ion implantation is performed on the semiconductor substrate to form an N well, and then rapid annealing is performed, the annealing temperature is 1030° C., and the annealing time is 30 seconds. After the above dry etching, the thickness of the dielectric layer on the semiconductor substrate is

Coat a layer of photoresist on the top of the gate, and then immerse the 1% HF etching solution on the surface of the substrate, and let the HF etching solution react with the gate sidewall layer and the silicon dioxide on the substrate surface For 60 seconds, finally the silicon dioxide on the sidewall layer of the gate and the substrate surface is gradually peeled off, and the peeled product leaves the etching surface and diffuses into the solution, and is discharged with the solution. After the above wet etching, the thickness of the dielectric layer on the semiconductor substrate is

Then, the photoresist on the substrate is removed by oxygen plasma, the substrate is cleaned, and the etching process of the gate side wall layer is completed.

Finally, through the deep ion implantation process, boron atoms are implanted under the source and drain and inside the N well to form a P well; a metal silicide barrier layer (SAB) is deposited between the source, drain and gate; Hole preparation, metallization wiring, deposition of passivation layer and subsequent lead connection, packaging and other processes to complete the production of MOS devices.

Perform a performance test on the prepared MOS device, and the test content includes the off current and the breakdown voltage of the gate. The off current (Ioff) refers to the drain current when the device is in the off state. The larger the off current, the greater the leakage of the device, which will cause unnecessary power consumption. The test method for the shutdown current is: the source and the substrate are grounded, the gate is also grounded, and the drain is connected to 1.1 times the ground working voltage. The drain current measured at this time is the shutdown current. See Table 3 for the test results. The gate breakdown voltage test method is: the substrate is grounded, and the gate voltage is applied from 0. When the gate current suddenly increases, the gate voltage at this time is the breakdown voltage. See Table 4 for the test results.

Table 3 shows the off current at different locations on the surface of the test chip. As can be seen from Table 3, the off current on the chip surface is very small, which shows that the gate sidewall layer etching method provided by the present application significantly reduces the gate leakage current, and the gate leakage current of the MOS device prepared by this method It is very small and meets the requirement of current devices on leakage current. Table 4 shows the gate breakdown voltage at different locations on the surface of the test chip. It can be seen from Table 4 that the gate breakdown voltage of the MOS device prepared by using the gate sidewall layer etching method provided by the present application exceeds 18 volts, which meets the requirements of existing devices for the gate breakdown voltage.

table 3

Table 4

As can be seen from the above comparative examples and examples, the examples described in the application have achieved the following technical effects:

1. After dry etching the sidewall layer of the gate, the wet etching process is added. By controlling the wet etching, the oxide layer of the silicon substrate will not be damaged, and the dry etching of the sidewall layer of the gate is avoided. damage to the substrate;

2. Using the etching method provided in this application, the lateral electric field between the channel region and the drain is reduced, the generation of leakage current is reduced, and some performances of semiconductor devices can be improved;

3. The gate leakage current of the MOS device obtained by adopting the above etching technology is less than 1 milliampere, and the gate breakdown voltage exceeds 18 volts, which meets the requirements of existing devices on gate leakage current and breakdown voltage.

The above are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims (12)

1. A method for manufacturing a gate sidewall layer, characterized in that the method comprises: depositing a dielectric layer on the substrate with the gate; performing dry etching to remove the top dielectric layer of the gate, and thinning the dielectric layer on the sidewall of the gate and the surface of the substrate; Deposit photoresist on top of the gate; performing wet etching to further thin the gate sidewall and the dielectric layer on the substrate surface; and The photoresist is removed. 2. The manufacturing method according to claim 1, wherein the dielectric layer comprises one or more silicon oxide layers and/or silicon nitride layers. 3. The manufacturing method according to claim 1 or 2, characterized in that, after the dry etching is completed, the thickness of the dielectric layer on the surface of the substrate is greater than 4. The manufacturing method according to claim 3, wherein the sputtering power of the dry etching is 100-300 watts, and the time of the dry etching is 50-70 seconds. 5. The manufacturing method according to claim 1 or 2, characterized in that, the etching solution used in the wet etching is HF etching solution. 6. The manufacturing method according to claim 5, wherein the HF concentration of the HF etching solution is 0.1%-3%. 7. manufacturing method according to claim 5, is characterized in that, after finishing described wet etching, the medium layer thickness of described substrate surface is 8. The manufacturing method according to claim 1, characterized in that, after the dry etching is completed, a rapid annealing process is further performed. 9. A manufacturing method of a MOS device, characterized in that, the manufacturing method comprises: providing a semiconductor substrate on which a source, a drain, and a gate are prepared; forming a sidewall layer on the gate, wherein the sidewall layer is made by the manufacturing method described in any one of claims 1 to 8; A P-well or N-well is formed under the source and drain by deep ion implantation. 10. The preparation method according to claim 9, characterized in that, the preparation method comprises: providing a semiconductor substrate on which a source, a drain, and a gate are prepared; Depositing a dielectric layer on the substrate and the gate, and forming a P+ lightly doped region under the source and drain through an ion implantation process; performing dry etching to remove the top dielectric layer of the gate, and thinning the dielectric layer on the sidewall of the gate and the surface of the substrate; performing ion implantation on the semiconductor substrate to form an N well; perform rapid annealing; depositing photoresist on top of the gate; performing wet etching to further thin the gate sidewall and the dielectric layer on the substrate surface; removing the photoresist; and A P-well is formed under the source and drain by deep ion implantation. 11. The manufacturing method according to claim 9 or 10, wherein the semiconductor substrate is N-type or P-type, and the gate sidewall layer is composed of one or more layers of silicon oxide and/or nitrogen composed of a silicon layer. 12. The manufacturing method according to claim 9 or 10, characterized in that the manufacturing method further comprises: contact hole preparation, metallization wiring, deposition of a passivation layer, and subsequent lead connection and packaging processes.