CN104952723A - Manufacturing method of gate sidewall layer and manufacturing method of MOS device - Google Patents
Manufacturing method of gate sidewall layer and manufacturing method of MOS device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 118
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims description 40
- 238000001039 wet etching Methods 0.000 claims description 27
- 238000005516 engineering process Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 239000007788 liquid Substances 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000012536 packaging technology Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 24
- 230000006378 damage Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 description 12
- 238000012360 testing method Methods 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
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- 230000015572 biosynthetic process Effects 0.000 description 4
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- 238000005538 encapsulation Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- -1 Phosphonium ion Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
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- 238000010438 heat treatment Methods 0.000 description 2
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- 238000011056 performance test Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
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- 230000008859 change Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The present application provides a manufacturing method of a gate sidewall layer and a manufacturing method of a MOS device. The manufacturing method of a gate sidewall layer comprises the following steps of depositing a dielectric layer on a substrate with a gate, carrying out dry method etching to remove the top dielectric layer of the gate and thinning a gate sidewall and the dielectric layer at the surface of the substrate, depositing photoresist at the top of the gate, carrying out wet method etching and further thinning the gate sidewall and the dielectric layer at the surface of the substrate, and removing the photoresist. The manufacturing method of the MOS device comprises the steps of providing a semiconductor substrate, preparing a source electrode, a drain electrode and a gate on the substrate, forming a sidewall layer on the gate, and forming a P zone or N zone under the source electrode and the drain electrode through deep ion implantation, wherein the sidewall layer is prepared through the above manufacturing method of a gate sidewall layer. According to the manufacturing methods provided by the invention, the damage of a silicon substrate in the gate sidewall layer dry method etching process is avoided, and the generation of leakage current is reduced.
Description
Technical field
The application relates to the etching technics of semiconductor integrated circuit, particularly relates to a kind of manufacture method of gate lateral wall layer and the manufacture method of MOS device.
Background technology
Along with the develop rapidly of semiconductor integrated circuit technology, the future development of the higher density of components of semiconductor chip forward, more high integration, makes semiconductor device reach arithmetic speed, larger memory data output faster.At present, the manufacturing technology of semiconductor device has entered 32 nanometers and even 18 nanometer technologies, and it is even less that the minimum feature size of grid width has reached 45 nanometers, and the channel length below it also constantly reduces.
MOS transistor is made up of source electrode, drain electrode, blocking layer of metal silicide (SAB), grid and gate lateral wall layer.But in the manufacture process of MOS transistor, when carrying out dry etching to the side wall layer of grid, be easy to destroy the source drain structure in silicon substrate, thus cause leakage current to produce, this problem limits MOS transistor application in the semiconductor device.
Etching to reduce side wall layer the leakage current caused, mainly adopting following methods at present: be a kind of, reduce the time of dry etching, make SAB have larger thickness, to reduce the destruction to silicon substrate.But blocked up SAB can affect follow-up process window; Another kind method, carries out light dope, forms the lightly doped region (LDD) with high resistivity, thus reduce the generation of leakage current below source electrode with drain electrode; The third, after carrying out dry etching to gate lateral wall layer, increase a heat treatment process, dry etch process is restored to the infringement that silicon substrate causes, but Technology for Heating Processing can cause position between device to change, and affects the stability of device.
Specifically, at publication number be CN102867755A Chinese patent application in disclose a kind of method of nmos device of low GIDL electric current.The method is by the BF after the formation of P trap
2ion implantation technology carrys out adjusting threshold voltage, BF
2be injected into SiO
2channel region under/Si interface, suppresses the diffusion of B ion with F, reduce the transverse electric field of channel region and drain electrode, thus reduce GIDL electric current under the prerequisite not affecting device performance.The processing step of the method is: carry out trap to wafer and inject formation P trap, carry out BF to P trap
2inject with adjusting threshold voltage; At crystal column surface successively deposition of gate insulating barrier and gate polysilicon layer, etching removing excess polysilicon layer forms grid; Around grid, prepare the first side wall layer, after forming the first side wall layer, light dope is carried out to device and form lightly-doped source drain structure; In the first side wall layer periphery preparation the second side wall layer, carry out source and drain after forming the second side wall layer and inject formation source-drain electrode.Although the method can reduce the transverse electric field of channel region and drain electrode to a certain extent, reduce the generation of leakage current, but the method can not reduce the leakage current brought due to the etching of gate lateral wall layer, the destruction of grid leakage current to MOS device can not be solved completely.
Be in the Chinese patent application of CN101459140, disclose a kind of built-in EEPROM process utilizing SAB to increase width of lateral wall at publication number.The processing step of the method is: after polysilicon gate is formed and LDD injects, deposited oxide film and nitride film, and the nitride film bottom etching grid, forms side wall layer; Deposited oxide film, as ground floor silicide barrier layer; Carry out source-drain electrode injection; Deposition one deck silicon nitride is as second layer silicide barrier layer, and etching removes second layer silicide barrier layer and ground floor silicide barrier layer, finally forms silicide.Although the method can reduce the electric leakage of device to a certain extent, the method can not reduce the transverse electric field of channel region and drain electrode, can not solve the destruction of grid leakage current to MOS device completely.
Summary of the invention
In order to solve the problem of the grid leakage current that existing semiconductor device exists, the application provides a kind of manufacture method of gate lateral wall layer on the one hand.The destruction that the dry etching that this manufacture method avoids gate lateral wall layer causes substrate, thus decrease the generation of leakage current, improve the stability of device.
The application provides a kind of manufacture method of gate lateral wall layer on the one hand, and this manufacture method comprises the following steps: have the deposited on substrates dielectric layer of grid; Carry out the top dielectric layer that dry etching removes grid, and the dielectric layer of thinning gate lateral wall and substrate surface; At the deposited on top photoresist of grid; Carry out wet etching, the dielectric layer of further thinning gate lateral wall and substrate surface; Then photoresist is removed.
Further, in above-mentioned manufacture method, dielectric layer comprises one or more layers silicon oxide layer and/or silicon nitride layer.
Further, in above-mentioned manufacture method, after completing dry etching, the thickness of dielectric layers of substrate surface is greater than
Further, in above-mentioned manufacture method, the sputtering power of dry etching is 100-300 watt, and the time of dry etching is 50-70 second.
Further, in above-mentioned manufacture method, the etching liquid that wet-etching technology adopts is HF etching liquid.
Further, in above-mentioned manufacture method, the concentration of HF etching liquid is 0.1%-3%.
Further, in above-mentioned manufacture method, after completing wet etching, the thickness of dielectric layers of substrate surface is
Further, in above-mentioned manufacture method, after completing dry etching, carry out rta technique further.
The another aspect of the application there are provided a kind of manufacture method of MOS device, and this manufacture method comprises: provide Semiconductor substrate, prepares source electrode, drain electrode, grid over the substrate; Grid forms side wall layer, and wherein, described side wall layer adopts the manufacture method of the above-mentioned gate lateral wall layer of the application to be prepared from; Be infused in below source electrode and drain electrode by deep ion and form P trap or N trap.
Further, above-mentioned manufacture method comprises: provide Semiconductor substrate, and substrate is prepared source electrode, drain electrode, grid; Metallization medium layer on substrate and grid, and form P+ light doping section by ion implantation technology at source electrode and drain electrode below; Carry out the top dielectric layer that dry etching removes grid, and the dielectric layer of thinning gate lateral wall and substrate surface; Ion implantation is carried out to Semiconductor substrate and forms N trap; Carry out short annealing; At the deposited atop photoresist of grid; Carry out wet etching, the dielectric layer of further thinning gate lateral wall and substrate surface; Remove photoresist; And by deep ion be infused in source electrode and drain electrode below form P trap.
Further, in above-mentioned manufacture method, Semiconductor substrate can be N-type or P type, and gate lateral wall layer is made up of one deck or multilayer silicon oxide layer and/or silicon nitride layer.
Further, above-mentioned manufacture method comprises further: contact hole preparation, metallized traces, deposit passivation layer and follow-up lead-in wire connect and packaging technology.
As can be seen from technique scheme, the application, by adding the technique of a wet etching after dry etch process, achieves the etching to gate lateral wall layer.It is thinning that the key of this lithographic method is to adopt wet etching to carry out etching to the dielectric layer on gate lateral wall and substrate surface, avoids the destruction that dry etching causes substrate.By using the lithographic method that provides of the application, reducing the transverse electric field of channel region and drain electrode, decreasing the generation of leakage current, thus overcome the technology drawback that existing etching technics brings.
Accompanying drawing explanation
The accompanying drawing forming a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the schematic flow sheet of the manufacture method of the gate lateral wall layer that the application's execution mode provides; And
Fig. 2 shows the schematic flow sheet of the manufacture method of the MOS device that the application's execution mode provides.
Embodiment
Below in conjunction with the embodiment of the application, the technical scheme of the application is described in detail, but following embodiment is only understand the application, and the application can not be limited, embodiment in the application and the feature in embodiment can combine mutually, and the multitude of different ways that the application can be defined by the claims and cover is implemented.
From background technology, there is the problem of grid leakage current in the semiconductor device that existing dry etching gate lateral wall layer is formed, present inventor studies for the problems referred to above, at dry etching gate lateral wall layer, creatively add the technique of a wet etching, achieve the etching to gate lateral wall layer, and the source drain structure in substrate can not be destroyed, avoid the generation of grid leakage current.Inventor finds that the channel region of semiconductor device that obtains according to the method described above and the transverse electric field of drain electrode are weakened, and decreases the generation of leakage current, can improve the partial properties of semiconductor device.
The manufacture method of the gate lateral wall layer that the application provides comprises the following steps: have the deposited on substrates dielectric layer of grid; Carry out the top dielectric layer that dry etching removes grid, and the dielectric layer of thinning gate lateral wall and substrate surface; At the deposited on top photoresist of grid; Carry out wet etching, the dielectric layer of further thinning gate lateral wall and substrate surface; Then photoresist is removed.
Fig. 1 shows the schematic flow sheet of the manufacture method of the gate lateral wall layer that the application provides.The manufacture method that the gate lateral wall layer that the application provides is described is explained further below in conjunction with Fig. 1.
First, there is the deposited on substrates dielectric layer of grid.Above-mentioned dielectric layer, in follow-up preparation technology, will form gate lateral wall layer after dry method and wet-etching technology.Therefore, the structure forming this dielectric layer can be one or more layers, and the material forming dielectric layer can be silicon oxide layer or silicon nitride layer.According to the condition of side wall layer desired thickness and follow-up dry etching, formed thickness of dielectric layers and material can be selected.Preferably, this dielectric layer comprises nitride multilayer silicon layer or silicon oxide layer, or the sandwich construction that silicon nitride layer and silicon oxide layer are alternately formed.
Above-mentioned Semiconductor substrate can be lightly doped n-type substrate or P type substrate, and foreign atom is boron, phosphorus or arsenic, and doping process comprises the routine techniques such as ion implantation, diffusion technique.The formation process of above-mentioned grid can be: at deposited on substrates monoxide layer, then depositing layers, by the technique such as photoetching and wet etching, forms grid.
Complete after the step of deposited on substrates dielectric layer with grid, carry out the top dielectric layer that dry etching removes grid, and the dielectric layer of thinning gate lateral wall and substrate surface.Above-mentioned dry etch process can be plasma etching, Ions Bombardment or reactive ion etching.In the specific embodiment that the application provides, using plasma lithographic method carries out dry etching, utilizes the surface of plasma bombardment dielectric layer and then is hit by the atom of dielectric layer material.Because dry etching can damage the generation that substrate surface may cause grid leakage current, therefore, can according to the speed of the THICKNESS CONTROL dry etching of the thickness of dielectric layer and preformed gate lateral wall layer.Further, by controlling sputtering power and the etch period of dry etching, the control to etch rate is realized.Preferably, in the preferred embodiment of the application, the process conditions of dry etching are: main etching gas is CF
4and CHF
3, sputtering power is 100-300 watt, and etch period is 50-70 second.More preferably, after utilizing dry etching dielectric layer, the thickness that substrate surface remains dielectric layer needs to be greater than
to ensure that in dry etching process, substrate can not be destroyed.
In the embodiment that the application provides, after stating dry etching on the implementation, rta technique can be implemented to semiconductor device further.Implementing annealing process can make dry etch process be restored to the infringement that top portions of gates may cause.Preferably, the annealing temperature in above-mentioned rta technique is 900 to 1030 DEG C, and annealing time is 20 to 40 seconds.
Next, at the deposited on top photoresist of grid.Above-mentioned photoresist, as mask, protects the top portions of gates exposed not by the erosion of next step wet etching liquid.The mode of deposit those photoresist can adopt spin-coating method or spraying process, and above-mentioned technique is state of the art, does not repeat them here.
Next, carry out wet etching, the dielectric layer of further thinning gate lateral wall and substrate surface.The application breaks through and only adopts dry etching to carry out the traditional thought of side wall layer making, creatively by dry etching and wet-etching technology connected applications in the manufacturing process of gate lateral wall layer.Thinning owing to adopting dry etching to carry out dielectric layer in previous step, the thickness of dielectric layers that the thickness of substrate surface dielectric layer will be thinner than on gate lateral wall more or less, if continue to adopt dry etching, the dielectric layer caused on substrate surface just certainly will be etched away before gate lateral wall layer is formed, thus substrate will be destroyed in subsequent etching process.And wet etching is isotropic etching, the thickness of its lateral etching is close to the degree of depth of vertical etch.Therefore substitute dry etch process with wet-etching technology, can ensure the dielectric layer thickness thinning on gate lateral wall and the dielectric layer thickness thinning on substrate surface basically identical, thus avoid substrate be exposed to etching environment in.The wet-etching technology that the application adopts can be conventional wet lay etch technological condition.Preferably, in a kind of embodiment, this wet etching process is: dielectric layer HF etching liquid slowly being soaked gate lateral wall and substrate surface, allows the gate lateral wall layer on etching liquid and substrate react a period of time; Finally peeled off gradually by gate lateral wall layer, stripping product leaves etching surface and diffuses in solution, gets rid of with solution.And, can also by the control of the realizations such as the concentration of control etching liquid, reaction temperature and reaction time to wet-etch rate.Preferably, the application adopt the concentration of HF to be 0.1%-3%, the processing time is 30-200 second.More preferably, after utilizing wet etching dielectric layer, substrate surface dielectric layer is residual to be about
more preferably control
left and right.
Finally, remove photoresist, complete the making of whole gate lateral wall.Here adopted photoresist minimizing technology can be in DMF, or adopts ultrasonic minimizing technology, because the method is that routine techniques means have just repeated no more at this.
As can be seen from above-mentioned processing step, the manufacture method of the gate lateral wall layer that the application provides is the contribution that prior art is made: after the dry etching of gate lateral wall layer, adds the process that a wet etching peels off gate lateral wall layer; This lithographic method can complete the etching to gate lateral wall layer, can not produce again and destroy, thus decrease because oxide layer destroys the generation of the grid leakage current caused, improve the anti-high pressure destructive characteristics of device to substrate surface dielectric layer.
In addition, the another aspect of the application there are provided a kind of manufacture method of MOS device, and as shown in Figure 2, this manufacture method comprises: provide Semiconductor substrate, and substrate is prepared source electrode, drain electrode, grid; Grid forms side wall layer, and wherein, side wall layer is prepared from by above-mentioned gate lateral wall layer manufacturing method thereof; Be infused in below source electrode and drain electrode by deep ion and form P trap or N trap.
In the embodiment that the application provides, above-mentioned MOS device manufacture method comprises: provide Semiconductor substrate, and substrate is prepared source electrode, drain electrode, grid; Metallization medium layer on substrate and grid, and form P+ light doping section by ion implantation technology at source electrode and drain electrode below; Carry out the top dielectric layer that dry etching removes grid, and the dielectric layer of thinning gate lateral wall and substrate surface; Ion implantation is carried out to Semiconductor substrate and forms N trap; Carry out short annealing; At the deposited atop photoresist of grid; Carry out wet etching, the dielectric layer of further thinning gate lateral wall and substrate surface; Remove photoresist; And by deep ion be infused in source electrode and drain electrode below form P trap.
The above-mentioned deep ion injection technology that the application provides comprises the following steps: first, makes ion implantation technology window by photoetching and etching technics on substrate; Then, foreign atom is injected in substrate by process window, forms N+ doped region or P+ doped region; Through rta technique, form N trap or P trap.Preferably, described Semiconductor substrate is P type or N-type, and it is boron, phosphorus or arsenic that described foreign atom comprises foreign atom.
Described in the application, the manufacture method of MOS device comprises further: the techniques such as contact hole preparation, metallized traces, deposit passivation layer and the connection of follow-up lead-in wire, encapsulation, complete the making of MOS device.The MOS device that the gate lateral wall layer manufacturing method thereof utilizing the application to provide obtains, grid leakage current significantly reduces, and the component failure destruction caused due to grid leakage current is also significantly reduced.
The method for selective etching will further illustrating the application with specific embodiment and provide below.
Comparative example
First, the P type semiconductor substrate of light dope boron atom is provided, on above-mentioned substrate, prepares source electrode, drain electrode, polysilicon gate by techniques such as photoetching, etching, depositions; At deposited on substrates silicon dioxide, removed the silicon dioxide of top portions of gates by etching technics, form the side wall layer of grid; Inject boron atom by ion implantation technology at source electrode and drain electrode below, form P+ light doping section (LDD).
Then, utilize dry etch process to etch the silicon dioxide (dielectric layer) removing gate lateral wall layer and substrate surface, silica atoms is hit, realizes side wall layer thinning.Phosphonium ion injection is carried out to Semiconductor substrate, forms N trap, then carry out short annealing.The process conditions of etching are: main etching gas is CF
4and CHF
3, sputtering power is 250 watts, and etching temperature is 60 DEG C, and etch period is 60 seconds.
Finally, by deep ion injection technology below source electrode and drain electrode, inject boron atom inside N trap, P trap is formed; At source electrode, plated metal silicide barrier layer (SAB) between drain electrode and grid; Again through techniques such as contact hole preparation, metallized traces, deposit passivation layer and the connection of follow-up lead-in wire, encapsulation, complete the making of MOS device.
Carry out performance test to prepared MOS device, content measurement comprises close current and gate breakdown voltage.Drain current when close current (Ioff) refers to that device is in closed condition, close current is larger, and to represent the electric leakage of device larger, and the unnecessary work consumption caused is more.The method of testing of close current is: source electrode and Substrate ground, and grid is ground connection also, and drain electrode connects the operating voltage of 1.1 times, and the drain current now measured is close current, and test result asks for an interview table 1.Gate breakdown voltage method of testing is: Substrate ground, and grid is making alive from 0, and when grid current increases suddenly, grid voltage is now puncture voltage, and test result asks for an interview table 2.
Table 1 shows the close current at diverse location place, test chip surface.As can be seen from Table 1, the close current of chip middle position is comparatively large, and its numerical value has exceeded 1 milliampere, and peak reaches 19.66 milliamperes; Comparatively speaking, the close current at chip edge place is less.This illustrates that the leakage current of MOS device prepared by traditional handicraft is bigger than normal, has a great impact the stability of device.Table 2 shows the gate breakdown voltage at diverse location place, test chip surface.As shown in table 2, the gate breakdown voltage of chip surface major part position is 5 volts, only has the gate breakdown voltage at chip bottom marginal position place more than 18 volts.Test result shows, the gate breakdown voltage of MOS device prepared by traditional handicraft is lower, can not meet the requirement of existing device.
Table 1
Table 2
Embodiment
First, the P type semiconductor substrate of light dope boron atom is provided, on above-mentioned substrate, prepares source electrode, drain electrode, polysilicon gate by techniques such as photoetching, etching, depositions; At deposited on substrates silicon dioxide, and inject boron atom by ion implantation technology at source electrode and drain electrode below, form P+ light doping section (LDD).
Utilize the silicon dioxide layer on dry etching etching grid top, gate lateral wall layer and substrate surface, silica atoms is hit, eliminate the silicon dioxide layer of top portions of gates and achieve the thinning of side wall layer.The process conditions of etching are: main etching gas is CF
4and CHF
3, sputtering power is 250 watts, and etching temperature is 60 DEG C, and etch period is 60 seconds.Carry out phosphonium ion injection to Semiconductor substrate, form N trap, then carry out short annealing, the temperature of annealing is 1030 DEG C, and the time of annealing is 30 seconds.After above-mentioned dry etching, the thickness of dielectric layers in Semiconductor substrate is
Last layer photoresist is coated with at top portions of gates, then be the surface that 1%HF etching liquid is immersed in substrate by concentration, allow silicon dioxde reaction on HF etching liquid and gate lateral wall layer and substrate surface 60 seconds, finally the silicon dioxide on gate lateral wall layer and substrate surface is peeled off gradually, stripping product leaves etching surface and diffuses in solution, gets rid of with solution.After above-mentioned wet etching, the thickness of dielectric layers in Semiconductor substrate is
Then adopt the photoresist on oxygen gas plasma removal substrate, cleaning substrate, completes the etching process of gate lateral wall layer.
Finally, by deep ion injection technology below source electrode and drain electrode, inject boron atom inside N trap, P trap is formed; At source electrode, plated metal silicide barrier layer (SAB) between drain electrode and grid; Again through techniques such as contact hole preparation, metallized traces, deposit passivation layer and the connection of follow-up lead-in wire, encapsulation, complete the making of MOS device.
Carry out performance test to prepared MOS device, content measurement comprises close current and gate breakdown voltage.Drain current when close current (Ioff) refers to that device is in closed condition, close current is larger, and to represent the electric leakage of device larger, can cause unnecessary work consumption.The method of testing of close current is: source electrode and Substrate ground, and grid is ground connection also, and drain electrode connects 1.1 times of ground operating voltages, and the drain current now measured is close current, and test result asks for an interview table 3.Gate breakdown voltage method of testing is: Substrate ground, and grid is making alive from 0, and when grid current increases suddenly, grid voltage is now puncture voltage, and test result asks for an interview table 4.
Table 3 shows the close current at diverse location place, test chip surface.As can be seen from Table 3, the close current of chip surface is very little, this illustrates that the gate lateral wall layer lithographic method that the application provides significantly reduces grid leakage current, and the grid leakage current of the MOS device utilizing this method to prepare is very little, meets the requirement of existing device to leakage current.Table 4 shows the gate breakdown voltage at diverse location place, test chip surface.As can be seen from Table 4, the gate breakdown voltage of MOS device prepared by the gate lateral wall layer lithographic method utilizing the application to provide has exceeded 18 volts, meets the requirement of existing device to gate breakdown voltage.
Table 3
Table 4
As can be seen from above comparative example and embodiment, the example that the application states achieves following technique effect:
1, after dry etching gate lateral wall layer, adding wet-etching technology, silicon substrate oxide skin(coating) can not be destroyed, the destruction that the dry etching avoiding gate lateral wall layer causes substrate by controlling wet etching;
2, the lithographic method using the application to provide, reduces the transverse electric field of channel region and drain electrode, decreases the generation of leakage current, can improve the partial properties of semiconductor device;
The grid leakage current of the MOS device 3, adopting above-mentioned lithographic technique to obtain is less than 1 milliampere, and gate breakdown voltage has exceeded 18 volts, meets the requirement of existing device to grid leakage current and puncture voltage.
These are only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (12)
1. a manufacture method for gate lateral wall layer, is characterized in that, described method comprises:
There is the deposited on substrates dielectric layer of grid;
Carry out the top dielectric layer that dry etching removes described grid, and the dielectric layer of thinning described gate lateral wall and substrate surface;
At the deposited atop photoresist of grid;
Carry out wet etching, the dielectric layer of further thinning described gate lateral wall and substrate surface; And
Remove described photoresist.
2. manufacture method according to claim 1, is characterized in that, described dielectric layer comprises one or more layers silicon oxide layer and/or silicon nitride layer.
3. manufacture method according to claim 1 and 2, is characterized in that, after completing described dry etching, the thickness of dielectric layers of described substrate surface is greater than
4. manufacture method according to claim 3, is characterized in that, the sputtering power of described dry etching is 100-300 watt, and the time of described dry etching is 50-70 second.
5. manufacture method according to claim 1 and 2, is characterized in that, the etching liquid that described wet etching adopts is HF etching liquid.
6. manufacture method according to claim 5, is characterized in that, the HF concentration of described HF etching liquid is 0.1%-3%.
7. manufacture method according to claim 5, is characterized in that, after completing described wet etching, the thickness of dielectric layers of described substrate surface is
8. manufacture method according to claim 1, is characterized in that, after completing described dry etching, carries out rta technique further.
9. a manufacture method for MOS device, is characterized in that, described manufacture method comprises:
Semiconductor substrate is provided, prepares source electrode, drain electrode, grid over the substrate;
Grid forms side wall layer, and wherein, described side wall layer adopts the manufacture method according to any one of claim 1 to 8 to be made;
Be infused in below source electrode and drain electrode by deep ion and form P trap or N trap.
10. manufacture method according to claim 9, is characterized in that, described manufacture method comprises:
Semiconductor substrate is provided, prepares source electrode, drain electrode, grid over the substrate;
Metallization medium layer on described substrate and grid, and form P+ light doping section by ion implantation technology at described source electrode and drain electrode below;
Carry out the top dielectric layer that dry etching removes described grid, and the dielectric layer of thinning described gate lateral wall and substrate surface;
Ion implantation is carried out to described Semiconductor substrate and forms N trap;
Carry out short annealing;
At the deposited atop photoresist of described grid;
Carry out wet etching, the dielectric layer of further thinning described gate lateral wall and substrate surface;
Remove described photoresist; And
Be infused in below source electrode and drain electrode by deep ion and form P trap.
11. manufacture methods according to claim 9 or 10, it is characterized in that, described Semiconductor substrate is N-type or P type, and described gate lateral wall layer is made up of one deck or multilayer silicon oxide layer and/or silicon nitride layer.
12. manufacture methods according to claim 9 or 10, it is characterized in that, described manufacture method comprises further: contact hole preparation, metallized traces, deposit passivation layer and follow-up lead-in wire connect and packaging technology.
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| CN101447451A (en) * | 2007-11-30 | 2009-06-03 | 东部高科股份有限公司 | Image sensor and method for manufacturing the sensor |
| US20090162984A1 (en) * | 2007-12-24 | 2009-06-25 | Chung Kyung Jung | Method for manufacturing semiconductor device |
| CN103035529A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for improving electric leakage in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447451A (en) * | 2007-11-30 | 2009-06-03 | 东部高科股份有限公司 | Image sensor and method for manufacturing the sensor |
| US20090162984A1 (en) * | 2007-12-24 | 2009-06-25 | Chung Kyung Jung | Method for manufacturing semiconductor device |
| CN103035529A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for improving electric leakage in radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
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Application publication date: 20150930 |