CN103019883B - A kind of internal memory error correction and system - Google Patents
A kind of internal memory error correction and system Download PDFInfo
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- CN103019883B CN103019883B CN201210593465.3A CN201210593465A CN103019883B CN 103019883 B CN103019883 B CN 103019883B CN 201210593465 A CN201210593465 A CN 201210593465A CN 103019883 B CN103019883 B CN 103019883B
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Abstract
The present invention is applicable to error-correcting code technique field, provide a kind of internal memory error correction and system, described method comprises: if all wrong position of two mirror-image channels of transmission data, mirror image manager is in the error bit of described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels; The error bit of described first mirror-image channels after described mirror image manager verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.The present invention, carry out error correcting by filling correction data to error bit, meanwhile, mirror-image channels only needs to retain CRC check code, improves the space availability ratio of storer further.
Description
Technical field
The invention belongs to error-correcting code technique field, particularly relate to a kind of internal memory error correction and system.
Background technology
In fault-tolerant computer field, the performance of data reliability to whole system is most important, particularly system core data or important application data, the reliability of its data directly affects the operation of whole system, due to dynamic RAM (Dynamic random access memory, DRAM) store data easily to make mistakes, so for significant data, often adopt the method for memory mirror to carry out the data backup of 1+1.
Concrete, the method of memory mirror: in a memory mirror system, generally designate certain two double data rate (Dual data rate, DDR) passage mirror image each other, any data write operation, write two passages, two passages of mirror image always preserve identical data content so each other all simultaneously; Read operation then can read two passages simultaneously, also can choose any one and read.The method of above-mentioned memory mirror is adopted to carry out the data backup of 1+1, the common structure of mirror memory system as shown in Figure 1, memory read-write initiated by master controller, under mirror image pattern, managed by mirror image administration module between two DDR passages, when write operation initiated by primary controller, mirror image administration module, by initiating to two passages the operation writing internal memory simultaneously, ensures that two passages always have identical data image.
Wherein, primary controller has two kinds of mode process after initiating read operation, and simultaneously one reads two passages, any one first return data, or any one data check returned is correct, then its read data is returned primary controller; Another kind method is the method adopting load balancing, and first only read one of them passage, if its return data check errors, and mistake can not be corrected, then read its mirror-image channels, complete read operation.
Existing error correction method has following two kinds, first situation is: usually adopt tape error correction code (Error Correction Code in reliability memory system, ECC) dual inline memory module (Dual in-linememory module, DIMM), its data width is 72, passage valid data are 64, and other 8 may be used for the check code storing data.The most simply adopt 64 bit data+8 ECC check codes, realize the scheme of entangling 1 inspection 2, wherein entangle 1 for correction 1 bit-errors, inspection 2 is detection 2 bit-errors.This method data store, as shown in Figure 2.If the passage of two mirror images each other all creates not repairable misdata, then the error in data in mirror-image system also can not be corrected.Than in error correction as shown in Figure 2 by mistake scheme, if two of one group of data passages all there occurs 2 bit-errors, then primary controller can not obtain correct data.
Another common mode is that the data aggregate organizing 64 is got up to be formed the stronger check code of EDC error detection and correction ability more, and such as N group 64 bit data adds N group 8 bit check code, thus realizes detection and the correction of more multi-bit error.This method data store, as shown in Figure 3.But two passages of one group of data all independently adopt identical checkschema, passage redundancy backup, and the space availability ratio of storer is not high.
In sum, in existing image system, just the redundancy backup of channel data adds the reliability of data, the data of two passages are not effectively organized, two passages still independently carry out data storage and verification comparatively speaking, two passages that there are one group of data all there occurs 2 bit-errors, primary controller can not obtain correct data, the problem not high with the space availability ratio of storer, therefore, a kind of method more effectively solving the not high problem of School Affairs storage space utilization factor is needed.
Summary of the invention
Embodiments provide a kind of internal memory error correction and system, when two mirror-image channels being intended to solve one group of data in existing image system all there occurs not repairable mistake, primary controller can not obtain correct data, and the problem that the space availability ratio of storer is not high.
First aspect, provides a kind of internal memory error correction, and described internal memory error correction comprises:
If all wrong position of two mirror-image channels of transmission data, mirror image manager is in the error bit of described first mirror-image channels, and fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels;
The error bit of described first mirror-image channels after described mirror image manager verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Further, described internal memory error correction also comprises:
Described correction data acquisition be [0000,0001 ..., 1111] exhaustive data acquisition.
Further, described internal memory error correction also comprises:
Described two mirror-image channels of described mirror image manager contrast, are labeled as described error bit by different position in described two mirror-image channels.
Further, described internal memory error correction also comprises:
Described mirror image manager, according to the checkschema of described data, obtains check code.
Further, described internal memory error correction specifically comprises:
If described data are one group of independence checking data, described mirror image manager reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
If described data are many group associating checking datas, described mirror image manager, according to preset rules, combines the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
Further, described internal memory error correction also comprises:
After described first mirror-image channels verification is correct, described mirror image manager, according to described first mirror-image channels, is corrected another mirror-image channels in described two mirror-image channels.
Second aspect, provides a kind of mirror image manager, and described mirror image manager comprises:
Error correction unit, if for all wrong position of two mirror-image channels of transmitting data, to in the error bit of described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels;
Verification unit, for verifying the error bit of described first mirror-image channels after filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Further, described mirror image manager also comprises:
Error bit acquiring unit, for contrasting described two mirror-image channels, is labeled as described error bit by different position in described two mirror-image channels.
Further, described mirror image manager also comprises:
Check code acquiring unit, for the checkschema according to described data, obtains check code.
Further, described check code acquiring unit comprises:
Independent check code acquisition module, if be one group of independence checking data for described data, reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
Associating check code acquisition module, if be many group associating checking datas for described data, according to preset rules, combine the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
Further, described mirror image manager also comprises:
Mirror-image channels recovery unit, for after described first mirror-image channels verification is correct, according to described first mirror-image channels, corrects another mirror-image channels in described two mirror-image channels.
The third aspect, provides a kind of mirror image manager, and described mirror image manager comprises:
Microprocessor, if for all wrong position of two mirror-image channels of transmitting data, to in the error bit of described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels; The error bit of described first mirror-image channels after verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Further, different position in described two mirror-image channels, also for contrasting described two mirror-image channels, is labeled as described error bit by described microprocessor.
Further, described microprocessor, also for the checkschema according to described data, obtains check code.
Further, if described microprocessor is one group of independence checking data specifically for described data, the cyclic redundancy check (CRC) code of described first mirror-image channels is read, as check code; If described data are many group associating checking datas, according to preset rules, combine the cyclic redundancy check (CRC) code of multiple mirror-image channels, generate check code.
Further, described microprocessor also for after described first mirror-image channels verification is correct, according to described first mirror-image channels, is corrected another mirror-image channels in described two mirror-image channels.
Fourth aspect, provides a kind of internal memory error correction system, and described internal memory error correction system comprises described mirror image manager.
In the embodiment of the present invention, utilize the redundant data of the mirror-image channels of data, realize mirror-image channels under existing scheme all exist not correctable error time, error correcting is carried out by filling correction data to error bit, simultaneously, mirror-image channels only needs to retain CRC check code, improves the space availability ratio of storer further.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the common structure of mirror memory system that background technology provides;
Fig. 2 is that the data of 64 bit data+8 ECC that background technology provides store schematic diagram;
Fig. 3 is that the data that N group 64 bit data+N that background technology provides organizes 8 ECC store schematic diagram;
Fig. 4 is the realization flow figure of the internal memory error correction that the embodiment of the present invention one provides;
Fig. 5 is the signature of the error bit of two mirror-image channels that the embodiment of the present invention one provides;
Fig. 6 is another the applicable scene of the internal memory error correction that the embodiment of the present invention two provides;
Fig. 7 is the structured flowchart of the mirror image manager that the embodiment of the present invention three provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In embodiments of the present invention, if all wrong position of two mirror-image channels of transmission data, mirror image manager is in the error bit of described first mirror-image channels, and fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels; The error bit of described first mirror-image channels after described mirror image manager verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Below in conjunction with specific embodiment, realization of the present invention is described in detail:
Embodiment one
Fig. 4 shows the realization flow of the internal memory error correction that the embodiment of the present invention one provides, and the executive agent of this embodiment is mirror image manager, and details are as follows for the method process:
In step S401, if all wrong position of two mirror-image channels of transmission data, mirror image manager is in the error bit of described first mirror-image channels, and fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels.
In the present embodiment, described error bit is that two mirror-image channels of one group of data are passed through to contrast, the minimum data unit of the existence mistake of acquisition.Described first mirror-image channels is any one mirror-image channels of two mirror-image channels of one group of data.Described correction data acquisition is an exhaustive data acquisition, comprises multiple correction data, be specially [0000,0001 ..., 1111].
Preferably, described two mirror-image channels of mirror image manager contrast, are labeled as described error bit by different position in described two mirror-image channels.
In step S402, the error bit of described first mirror-image channels after described mirror image manager verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
In the present embodiment, after with the error bit revising the first mirror-image channels described in data stuffing, mirror image manager is with the check code of described data, verify described error bit, if verification is correct, this error bit is revised, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Preferably, before S402, described mirror image manager according to the checkschema of described data, can also obtain check code.
Concrete, described mirror image manager, according to the checkschema of described data, obtains check code, specifically comprises:
If described data are one group of independence checking data, described mirror image manager reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
If described data are many group associating checking datas, described mirror image manager, according to preset rules, combines the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
Preferably, after S402, after can also working as described first mirror-image channels verification correctly, described mirror image manager, according to described first mirror-image channels, is corrected another mirror-image channels in described two mirror-image channels.
Wherein, with dual inline memory module (Dual-Inline-Memory-Modules, DIMM) 64 bit data+8 bit strip error correcting code (Error Correction Code are adopted in, ECC), one group of Dynamic data exchange verification, wherein mirror-image channels 0,1 has the situation of 2 error bits, is described the concrete scene that the present invention is suitable for:
The data of the mirror-image channels 0,1 in Fig. 5 are compared, different position in described two mirror-image channels is labeled as described error bit, when two mirror-image channels have 2 error bits, as shown in Figure 5 by position 3,5,35,54 are marked, the concept that error in data due to two mirror-image channels appears at same position is very little, and these different mark positions are exactly the error bit of mirror-image channels 0,1.
From mirror-image channels 0 and mirror-image channels 1, arbitrarily select mirror-image channels 0, to the position 3,35 marked wherein, fill revise data acquisition [0000,0001 ..., 1111] in correction data.Fill after revising data, the error bit of the mirror-image channels 0 after mirror image manager verification filling, if verification is correct, described mirror-image channels 0 error correction success, if check errors, continue to select to revise the error bit that data stuffing enters mirror-image channels 0, until mirror-image channels 0 verifies correctly according to preset order in described correction data acquisition.Finally recover mirror-image channels 1 according to mirror-image channels 0.
Can find according to error correction procedure above, because the data of two mirror-image channels exist redundancy, so the necessity that each mirror-image channels has error correcting capability is not respectively very large, only needs error detecing capability and just can carry out error handle and recovery by the comparing of two mirror-image channels.
Under mirror image pattern, each mirror-image channels is carried out separately error correction and is had little significance, and in general realizes error correction than the check code only realizing error-detecting and need more multidigit.In other words when identical check code quantity, it is stronger than the error detecing capability of the check code realizing error correction only to realize error detection.
Such as adopt 64 bit data+8 ECC can only realize entangling the error handle of 1 inspection 2, if adopt 64 bit data+8 cyclic redundancy check (CRC) code (Cyclic Redundancy Check, CRC), then its error detecing capability is as follows:
Code word size n=72 position, information field length k=64 position, its error detection capability is as follows:
1) burst error of burst-length <=n-k;
2) mistake of most of burst-length=n-k+1, undetectable this kind of mistake only accounts for 2-(n-k-1);
3) mistake of most of burst-length >n-k+1, undetectable this kind of mistake only accounts for 2-(n-k);
4) all odd number random errors.
64 bit data+8 cyclic redundancy check (CRC) code error detecing capabilities are obviously better than 64 bit data+8 ECC schemes, under mirror image pattern, each mirror-image channels only realizes error-detecting, if when two mirror-image channels all exist mistake, the method that can be described by the present embodiment carries out Fault recovery.Error detection and correction ability under mirror image pattern will be significantly improved like this.
The present embodiment, can reach and utilize the redundancy properties of storer two mirror-image channels under mirror image pattern, realize mirror-image channels under existing scheme all exist not correctable error time, error correcting is carried out by filling correction data to error bit, make primary controller obtain correct data response, improve the error correcting capability of system, simultaneously, mirror-image channels only needs to retain CRC check code, improves the space availability ratio of storer further.
Embodiment two
The Another application scene of the internal memory error correction that the embodiment of the present invention two provides, the executive agent of this embodiment is mirror image manager, and details are as follows:
In the present embodiment, be that concrete object is described with the data of 4 groups 64, each mirror-image channels only preserves check code, only realize error-detecting and do not realize error correcting, specifically with the data of 4 groups 64 as shown in Figure 6, wherein, originally mirror-image channels 64 to 71 is ECC, and 64 to 67 is CRC.
Wherein, the first row is represented to the data of fourth line by data 0 ~ data 3, the first row is represented to the CRC of 64 to 67 positions of fourth line by cyclic redundancy check (CRC) code 0 ~ cyclic redundancy check (CRC) code 3,4 groups of data like this, 16 CRC are adopted to be check code, the data of 4 groups 64 are many groups and combine verification, described mirror image manager is according to preset rules, combine cyclic redundancy check (CRC) code 0, cyclic redundancy check (CRC) code 1, cyclic redundancy check (CRC) code 2 and cyclic redundancy check (CRC) code 3 in 4 mirror-image channels successively, generate 16 CRC check codes.In mirror-image system, when checking data 0, data 1, data 2 and data 3 are arbitrary or all existence is wrong, contrast two mirror-image channels of misdata respectively, mark the error bit of mirror-image channels.Mirror-image channels 0 is selected arbitrarily in each group mirror-image channels 0 of misdata and mirror-image channels 1, to the error bit marked wherein, fill and revise data acquisition [0000, 0001, ..., 1111] the correction data in, fill after revising data, the error bit of the mirror-image channels 0 after mirror image manager verification filling, if verification is correct, described mirror-image channels 0 error correction success, if check errors, continue to select to revise the error bit that data stuffing enters mirror-image channels 0 according to preset order in described correction data acquisition, until mirror-image channels 0 verifies correctly, finally recover mirror-image channels 1 according to mirror-image channels 0.
Originally the data bit storing 68 ~ 71 of ECC is as can be seen from Figure 6 vacant, may be used for storing other information, can easily for storage directory in such as cache coherent non-uniform memory access (Cache-Coherent Non-UniformMemory Access, CC-NUMA) system.
These data of 4 groups 64 above-mentioned, only need 4*4 position to be used for storing check code, the filling rate of check bit, for storing other information that data are relevant therewith, is improve 50% by reserved out 4*4 position storage space.
The present embodiment, can reach the feature utilizing data redundancy under mirror image pattern, and reduce the figure place of the ECC check code carried out required for error correcting, the utilization factor of check bit improves 50%, improves the space availability ratio of storer further.
Embodiment three
Fig. 7 shows the concrete structure block diagram of the mirror image manager that the embodiment of the present invention three provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.In the present embodiment, this mirror image manager comprises: error bit acquiring unit 71, error correction unit 72, check code acquiring unit 73, verification unit 74 and mirror-image channels recovery unit 75, and described check code acquiring unit 73 comprises independent check code acquisition module 731 and associating check code acquisition module 732.
Wherein, error correction unit 72, if all wrong position of two mirror-image channels for transmitting data, in the error bit of described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels;
Verification unit 74, for verifying the error bit of described first mirror-image channels after filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Further, described mirror image manager also comprises:
Error bit acquiring unit 71, for contrasting described two mirror-image channels, is labeled as described error bit by different position in described two mirror-image channels.
Further, described mirror image manager also comprises:
Check code acquiring unit 73, for the checkschema according to described data, obtains check code.
Further, described check code acquiring unit 73 comprises:
Independent check code acquisition module 731, if be one group of independence checking data for described data, reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
Associating check code acquisition module 732, if be many group associating checking datas for described data, according to preset rules, combine the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
Further, described mirror image manager also comprises:
Mirror-image channels recovery unit 75, for after described first mirror-image channels verification is correct, according to described first mirror-image channels, corrects another mirror-image channels in described two mirror-image channels.
The mirror image manager that the embodiment of the present invention provides can be applied in the embodiment of the method for aforementioned correspondence, and details, see the description of above-described embodiment, do not repeat them here.
Embodiment four
Fig. 7 shows the concrete structure block diagram of the mirror image manager that the embodiment of the present invention four provides, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention.In the present embodiment, this mirror image manager comprises: microprocessor 7.
Wherein, microprocessor 7, if all wrong position of two mirror-image channels for transmitting data, in the error bit of described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels; The error bit of described first mirror-image channels after verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
Further, different position in described two mirror-image channels, also for contrasting described two mirror-image channels, is labeled as described error bit by described microprocessor 7.
Further, described microprocessor 7, also for the checkschema according to described data, obtains check code.
Further, if described microprocessor 7 is one group of independence checking data specifically for described data, the cyclic redundancy check (CRC) code of described first mirror-image channels is read, as check code; If described data are many group associating checking datas, according to preset rules, combine the cyclic redundancy check (CRC) code of multiple mirror-image channels, generate check code.
Further, described microprocessor 7 also for after described first mirror-image channels verification is correct, according to described first mirror-image channels, is corrected another mirror-image channels in described two mirror-image channels.
The mirror image manager that the embodiment of the present invention provides can be applied in the embodiment of the method for aforementioned correspondence, and details, see the description of above-described embodiment, do not repeat them here.
It should be noted that in said system embodiment, included unit is carry out dividing according to function logic, but is not limited to above-mentioned division, as long as can realize corresponding function; In addition, the concrete title of each functional unit, also just for the ease of mutual differentiation, is not limited to protection scope of the present invention.
In addition, one of ordinary skill in the art will appreciate that all or part of step realized in the various embodiments described above method is that the hardware that can carry out instruction relevant by program has come, corresponding program can be stored in a computer read/write memory medium, described storage medium, as ROM/RAM, disk or CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. an internal memory error correction, is characterized in that, described internal memory error correction comprises:
If all wrong position of two mirror-image channels of transmission data, mirror image manager is in the error bit of the first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels, described correction data acquisition is [0000,0001 ..., 1111] exhaustive data acquisition;
The error bit of described first mirror-image channels after described mirror image manager verification filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
2. internal memory error correction as claimed in claim 1, it is characterized in that, in the error bit of described mirror image manager to described first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels also comprises before being the arbitrary mirror-image channels in described two mirror-image channels:
Described two mirror-image channels of described mirror image manager contrast, are labeled as described error bit by different position in described two mirror-image channels.
3. internal memory error correction as claimed in claim 1 or 2, is characterized in that, before the error bit of described first mirror-image channels after described verification is filled, also comprises:
Described mirror image manager, according to the checkschema of described transmission data, obtains check code.
4. internal memory error correction as claimed in claim 3, is characterized in that, described mirror image manager, according to the checkschema of described transmission data, obtains check code, is specially:
If described transmission data are one group of independence checking data, described mirror image manager reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
If described transmission data are many group associating checking datas, described mirror image manager, according to preset rules, combines the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
5. internal memory error correction as claimed in claim 3, described method also comprises:
After described first mirror-image channels verification is correct, described mirror image manager, according to described first mirror-image channels, is corrected another mirror-image channels in described two mirror-image channels.
6. a mirror image manager, is characterized in that, described mirror image manager comprises:
Error correction unit, if for all wrong position of two mirror-image channels of transmitting data, to in the error bit of the first mirror-image channels, fill the correction data revised in data acquisition, described first mirror-image channels is the arbitrary mirror-image channels in described two mirror-image channels, and described correction data acquisition is [0000,0001, ..., 1111] exhaustive data acquisition;
Verification unit, for verifying the error bit of described first mirror-image channels after filling, if verification is correct, described first mirror-image channels error correction success, if check errors, continue to select to revise the error bit that data stuffing enters described first mirror-image channels according to preset order in described correction data acquisition, until described first mirror-image channels verification is correct.
7. mirror image manager as claimed in claim 6, it is characterized in that, described mirror image manager also comprises:
Error bit acquiring unit, for contrasting described two mirror-image channels, is labeled as described error bit by different position in described two mirror-image channels.
8. mirror image manager as claimed in claims 6 or 7, it is characterized in that, described mirror image manager also comprises:
Check code acquiring unit, for the checkschema according to described transmission data, obtains check code.
9. mirror image manager as claimed in claim 8, it is characterized in that, described check code acquiring unit specifically comprises:
Independent check code acquisition module, if be one group of independence checking data for described transmission data, reads the cyclic redundancy check (CRC) code of described first mirror-image channels, as check code;
Associating check code acquisition module, if be many group associating checking datas for described transmission data, according to preset rules, combine the cyclic redundancy check (CRC) code of multiple mirror-image channels, generates check code.
10. mirror image manager as claimed in claim 8, it is characterized in that, described mirror image manager also comprises:
Mirror-image channels recovery unit, for after described first mirror-image channels verification is correct, according to described first mirror-image channels, corrects another mirror-image channels in described two mirror-image channels.
11. 1 kinds of internal memory error correction systems, is characterized in that, described internal memory error correction system comprises:
Mirror image manager as described in any one of claim 6-10.
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| CN110798225B (en) * | 2019-11-06 | 2024-07-23 | 深圳大普微电子科技有限公司 | Data error correction method, device, equipment and readable storage medium |
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