CN103019835A - System and method for optimizing interruption resources in multi-core processor - Google Patents
System and method for optimizing interruption resources in multi-core processor Download PDFInfo
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Abstract
The invention discloses a system and method for optimizing interruption resources in a multi-core processor. The system comprises a processor interrupt scheduler (105) and a plurality of processors (106), and also comprises a threaded interrupt processor (103), wherein the threaded interrupt processor (103) is used for intercepting and capturing all interrupt requests sent to the processors (106) in the multi-core processor, threading the interrupt requests for regulating priorities according to a pre-set optimizing arbitration rule and re-arranging the priorities of the interrupt requests, and sending the arranged interrupt requests to the processor interrupt scheduler (105) according to the arranged sequence for scheduling to the processors (106) for processing. According to the invention, the interrupt resource distribution of a computer is optimized and the speed of real-time tasks is increased, thus the integral performance of the computer is improved.
Description
Technical field
The present invention relates to a kind of computer resource management technical field, particularly relate to a kind of polycaryon processor interrupt resources optimization process system and method.
Background technology
In computer system, in order effectively to process some bursts, urgent, preferential task, need to be in the process of computer operation, the task that interrupts carrying out also keeps site environment and the handling interrupt task.
The interruption of work principle is: in computer system, interrupt having high priority, when the invention interrupt request, as long as produce interrupt event, computer system will be carried out corresponding interrupt task, and just carry out normal task after executing interrupt task.The interruption of existing computer system comprises program interrupt, outer interruption, IO interrupt, hardware fault interruption, supervision call interrupt etc.
In the existing computer system, can realize effectively that the method for interrupting has a variety of, for example, interrupt merging and (be mainly used in NIC(Network Interfance Card, network interface unit) reception of flow bag, wherein cause interrupt before a plurality of bags of disposable reception), mix that poll interrupts, TCP lightens the burden engine (TCP Offload Engine, TOE), RDMA(Remote Direct Memory Access, long-range immediate data access)/DDP(Direct Data Placement, immediate data is placed) etc. method.But these method major parts are for the disconnected method of the Data processing of NIC interface in the prior art, rather than for the interrupt management method of whole system, and wherein have postpone and uncertain factor interior.
And after multi-core technology proposed, polycaryon processor was the Computer Design trend of generally acknowledging, was not well optimized if the interruption of whole multiple nucleus system is processed, and then might cause the key business real-time task to can not get computational resource and process timely.
And a kind of solution of prior art is only only NIC to be interrupted being optimized, the interruption rate of processing by increasing NIC, the deficiency of solution computing power.Such optimization method had not both been considered the continuity of single-threaded Processing tasks, did not consider the correlativity of multi-core multithreading yet, caused the problems such as computing expense increase of multioperation locking and de-locking, and the cost performance of its effectively computable is not high.
For only overcoming for the existing defective of the interrupt management of NIC, people carry out multiple discussion and improvement to existing interruption optimization method.
A kind of multinuclear interrupt management method of the prior art, its same category of device is operating system default treatment mode for the priority level use of interrupting.But it is optimized the system default hardware interrupts, soft interruption is not optimized, without any optimization, and its priority is applied to the general class computer equipment for processor affinity, and bonding apparatus itself, computation requirement and performance optimization do not design.
Simultaneously, use the interruption optimized treatment method of acquiescence mode, do not consider the priority issues of soft interruption, can not concentrate superior resources to go to solve the content that data stream needs most priority processing, and processor resource is forced to the request for the low level interrupts signal of hardware device, the high concurrent data calculation task of high flow capacity can not be preferentially finished, professional demand and target at a high speed can not be satisfied.
Simultaneously, same category of device often improves performance by the requirement that has strengthened the processor self performance, and lacks the management to interrupt mode.
Another kind of improved multinuclear interrupt management method in the prior art, it is by broadcasting interrupting, and by the response that processor (heat group) interrupts, the method realizes the scheduling of load balancing by the mode of broadcasting.Interruptable controller in its computer system sends in the interrupt register of processor according to the mode of priority with broadcasting, wait for that processor interrupt schedule device extracts, and send to processor (heat group) in the mode of broadcasting and process, processor is according to the load feedback duty of self, and carry out the exchange of interrupt task to other processors, solve and interrupt the problem processed when busy.But it does not consider the continuity of processor work, expense and the attenuation problem that the soft or hard interrupt priority level is dynamically adjusted, processing signals is transmitted repeatedly.
In sum, computer system of the prior art interrupts optimizing response and the basic realization of feedback based on belonging to interrupting, do not consider in conjunction with using and reasonably optimize with different with the hardware computing power, the priority that hardware and software interrupts is not processed by the ordering that optimization is carried out again, given processor is not carried out strict restriction and control yet.And prior art is too disperseed the processing links of interrupting, and is unfavorable for unified management and running and maintenance.
Summary of the invention
The object of the present invention is to provide a kind of polycaryon processor interrupt resources optimization process system and method, the interrupt resources of its optimizing computer is distributed, and improves the speed of real-time task, thereby improves the overall performance of computing machine.
Be a kind of polycaryon processor interrupt resources optimization process system that realizes that the object of the invention provides, comprise processor interrupt schedule device, and a plurality of processors, also comprise the threading interrupt manager, be used for intercepting and capturing the interrupt request that all mails to described a plurality of processors, and according to default optimization rules of arbitration described interrupt request is carried out the priority adjustment, priority to described interrupt request is resequenced, and the described interrupt request after then will sorting sends to described processor interrupt schedule device by the order after sorting and is dispatched to described a plurality of processor processing.
More preferably, described polycaryon processor interrupt resources optimization process system also comprises a plurality of interrupt sensors, is used for after computer system produces at least one interrupt request, receive the information of described interrupt request, and the information of described interrupt request is mail to described threading interrupt manager.
More preferably, described polycaryon processor interrupt resources optimization process system also comprises and the corresponding a plurality of interrupting information registers of described a plurality of interrupt sensors, and with the corresponding a plurality of processor interrupt registers of described a plurality of processors, wherein:
Described a plurality of interrupting information register is used for buffer memory mails to the described interrupt request of described threading interrupt manager from described a plurality of interrupt sensors information;
Described a plurality of processor interrupt register is used for buffer memory sends at least one rearrangement of described processor interrupt schedule device from described threading interrupt manager the information of described interrupt request;
Described processor interrupt schedule device is according to the priority in the information of the described interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to described a plurality of processor and interrupts processing.
More preferably, described threading interrupt manager comprises the intercepting and capturing module, the sequencing table memory module, and order module, sending module, wherein:
Described intercepting and capturing module, be used for producing interrupt request when computer system, the information of described interrupt request is mail in the process of described a plurality of processors by described interrupt sensors or interrupting information register, intercept and capture the information of described interrupt request, and the information of described interrupt request is mail to order module;
Described sequencing table memory module is used for the interruption sequencing table that storage is resequenced to the priority of whole interrupt request according to default optimization rules of arbitration;
Described order module, be used for after the information that receives the described interrupt request that described intercepting and capturing module intercepts, compare with the respective interrupt request of corresponding sequencing table in the described sequencing table memory module, and re-start optimization according to interrupting the priority of sequencing table to the interrupt request of described intercepting and capturing, and the communication of the described interrupt request after will optimizing arrives described sending module;
Described sending module is used for the information of the interrupt request after the described rearrangement is sent to described processor interrupt schedule device.
More preferably, described threading interrupt manager comprises that also affinity arranges module and threading judge module, wherein:
Described affinity arranges module, is used for the classification according to described interrupt request, by preseting the affinity rule with processor interrupt register corresponding to processor of described interrupt request distribution to appointment, binds the processor of described appointment and processes described interrupt request;
Described threading judge module is optimized and revised for judging according to the nothing delay sign of described interrupt request whether this interrupt request can re-start.
For realizing that the object of the invention also provides a kind of polycaryon processor interrupt resources optimized treatment method, comprise the steps:
Steps A is intercepted and captured the interrupt request that all mails to a plurality of processors in the polycaryon processor, and according to default optimization rules of arbitration whole interrupt request is carried out the priority adjustment, and the priority of interrupt request is resequenced;
Step B sends to described processor interrupt schedule device with the described interrupt request after the ordering by the order after sorting and is dispatched to the processor processing.
More preferably, before the described steps A, also comprise the following steps:
Steps A ', after computer system produced at least one interrupt request, the information of a plurality of interrupt sensors receive interruption request entered steps A again;
After the described step B, also comprise the following steps:
Step B ', processor interrupt schedule device be according to the priority in the information of the interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to a plurality of processors and interrupts processing.
More preferably, described steps A ' comprise the following steps:
Steps A 10 ' from the interrupt request that computer system produces, comprises the interrupt request of trap, fault, termination, is transferred to the interrupt sensors place;
Wherein, the information of each interrupt request comprises a unique interrupt request numbering byte or vector, and the numbering byte of described interrupt request or vector comprise the IRQ_ID0 position, processed rank position, the mode position to the processor distribution is interrupted, survival value position of interrupt request and without postponing zone bit;
Steps A 20 ' scanned to interrupt sensors with the clock period, obtained the information of the interrupt request of interrupt sensors, dump in the middle of the interrupting information register, and the information of the interrupt request in the cleaning interrupt sensors;
More preferably, described steps A comprises the steps:
Steps A 10, threading interrupt manager intercept and capture and copy and delete the information of the interrupt request of buffer memory in the interrupting information register by the clock period of setting;
Steps A 20 is according to judging whether this interrupt request can re-start and optimize and revise without postponing sign in the described interrupt request; If so, then enter steps A 30; Otherwise, change step B ' over to, directly interrupt request is sent to processor interrupt schedule device and process;
Steps A 30, the information of interrupt request is set as index with the IRQ_ID of source interrupt request, correspond to the central source row of prioritization table of threading interrupt manager, and by being optimized adjustment corresponding to purpose row in the prioritization table of source row, again its priority is sorted, rewrite the priority processing rank of ordering, and the information of the interrupt request after will resequencing stores in the middle of the threading interrupt manager into.
More preferably, the prioritization table of described threading interrupt manager is the Database Lists module of the priority of the interrupt request that arranges according to default optimization rules of arbitration, and it comprises source row, purpose row, time value;
Described source row comprise mode, the source survival value that interrupt to the processor distribution in source IRQ_ID, source priority processing rank, source;
Described purpose row comprise mode, the purpose survival value that purpose IRQ_ID, purpose processing rank, purpose are interrupted to the processor distribution;
Described time value comprises that interrupt request attack time, last time read break period, interrupt reading the time interval and real-time record content row.
More preferably, described step B comprises the following steps:
According to the clock period of setting, judge and when satisfying condition, copy and delete the information of interrupt request from the threading interrupt manager, the mode and the survival value that comprise the good IRQ_ID of rearrangement, priority processing rank, interrupt to the processor distribution.
More preferably, described judgement also satisfies condition, and comprises the steps:
Step B10 judges in the described mode of interrupting to the processor distribution the information of the interrupt request that copies from the threading interrupt manager, and whether the ID of given processor is arranged; If the ID of given processor is arranged, then enter step B20; If there is not the ID of given processor, then enter step B30;
Step B20, the information of the interrupt request that has existed in the described mode of interrupting to the processor distribution the information of the interrupt request that will copy from the threading interrupt manager and the processor interrupt register of appointment is compared, the priority of the interrupt request whether priority of the interrupt request that judgement copies from the threading interrupt manager has more preferably had in the processor interrupt register of appointment; If so, then the described interrupt request that copies from the threading interrupt manager is transferred to the processor interrupt register of appointment; Otherwise, directly return the threading interrupt manager, and do not delete the information of described interrupt request;
Step B30, in the situation that do not specify interrupt handler, the information of interrupt request and processor interrupt register are held consultation, and determine that processor receives the processing of current interrupt request; If consult successfully, then enter step B20 and process; If fail to consultations, then return the threading interrupt manager, and it is capable not delete the record of interrupt request.
More preferably, described step B ' comprises the following steps:
Step B10 ', the processor interrupt register receives the information of the interrupt request of optimizing at threading interrupt manager place, and interrupt request sequentially resequenced by the optimization of resetting in the threading interrupt manager, be cached in the middle of the record tabulation of the interrupt request after the rearrangement of processor interrupt register;
Step B20 ', the duty of processor interrupt schedule device record current processor, and the record of pressing the interrupt request after the central rearrangement of setting cycle query processor interrupt register is tabulated, compare with the record of interrupt request in the processor interrupt schedule device, enter step B30 ';
Described duty comprises current interrupt task quantity, and whether the IRQ_ID of each interrupt task, priority level, executing state are in hang-up, the mission number of current running status;
Step B30 ', according to the processor interrupt register in the judged result compared, determine whether that the higher interrupt request of priority needs to process; If have, then enter the processor of appointment; If no, then return in the middle of the processor interrupt register, return step B10 ' etc. pending;
Step B40 ', processor be the up-to-date interrupt request that provides of receiving processor interrupt schedule device respectively, to the response of processor interrupt schedule device and inform and can suspend and current processing of the task of on-hook; And after finishing the interrupt task of highest level, carry out again the highest interrupt task of current queue medium priority.
The invention has the beneficial effects as follows: polycaryon processor interrupt resources optimization process system and method for the present invention, adjust by the soft or hard interrupt priority level behind the interrupt thread, the interrupt task of polycaryon processor is optimized ordering, the interrupt resources of its optimized processor is distributed, improve the priority processing efficient of real-time task, improve real-time task and the data processing performance of equipment, thereby improved the overall performance of polycaryon processor in the computing machine, reduced the input of hardware manufacturing cost.And it carries out vertical task by distribution processor processes, and helps to reduce the latching operation of multithread programs, increases affinity control.
Description of drawings
Fig. 1 is embodiment of the invention polycaryon processor interrupt resources optimization process system architecture schematic diagram;
Fig. 2 is the interrupt manager of threading described in Fig. 1 structural representation;
Fig. 3 is embodiment of the invention polycaryon processor interrupt resources optimized treatment method process flow diagram;
Fig. 4 is the embodiment process flow diagram of embodiment of the invention polycaryon processor interrupt resources optimized treatment method as an example of the SMP architecture example.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, polycaryon processor interrupt resources optimization process system and method for the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
The polycaryon processor interrupt resources optimization process system and method for the embodiment of the invention, by changing the order of the interrupt request priority in the run time version (comprising real-time program) in the computer system, comprise the order to hardware, software interrupt requests, right of priority is processed in the interruption of real-time task in the processor resource of change polycaryon processor, and the raising system is to the computing velocity of core application.
As shown in Figure 1, the polycaryon processor interrupt resources optimization process system of the embodiment of the invention comprises processor interrupt schedule device 105, and a plurality of processor 106.
As a kind of embodiment, the polycaryon processor interrupt resources optimization process system of the embodiment of the invention also comprises threading interrupt manager 103.
Described threading interrupt manager 103, be used for intercepting and capturing the interrupt request that all mails to a plurality of processors 106, and according to default optimization rules of arbitration described interrupt request is carried out the priority adjustment, interrupt request task to polycaryon processor is adjusted, priority to interrupt request is resequenced, and the described interrupt request after then will sorting sends to described processor interrupt schedule device 105 by the order after sorting and is dispatched to processor 106 processing.
Whole at least one interrupt request that mails to a plurality of processors 106 in the polycaryon processor of described intercepting and capturing had not only comprised soft interruption (but also claim " software interruption ") request, also comprised hard interruption (claiming again " hardware interrupts ") request.
The intercept interrupt request is a kind of prior art in the embodiment of the invention, and those skilled in the art can realize the wherein technical scheme of intercept interrupt request according to content disclosed by the invention, therefore, in embodiments of the present invention, describes in detail no longer one by one.
Preferably, the polycaryon processor interrupt resources optimization process system of the embodiment of the invention, also comprise a plurality of interrupt sensors 101, be used for after computer system produces at least one interrupt request, the information of receive interruption request, and the information of described interrupt request mail to threading interrupt manager 103.
Further, the polycaryon processor interrupt resources optimization process system of the embodiment of the invention, also comprise and described a plurality of interrupt sensors 101 corresponding a plurality of interrupting information registers 102, and with a plurality of processor 106 corresponding a plurality of processor interrupt registers 104, wherein:
Described a plurality of interrupting information register 102 is used for buffer memory mails to the described interrupt request of threading interrupt manager 103 from described a plurality of interrupt sensors 101 information.
Described a plurality of processor interrupt register 104 is used for buffer memory sends at least one rearrangement of described processor interrupt schedule device 105 from threading interrupt manager 103 the information of interrupt request.
Processor interrupt schedule device 105 is according to the priority in the information of the interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to a plurality of processors and interrupts processing.
More preferably, as shown in Figure 2, described threading interrupt manager 103 comprises and intercepts and captures module 201, sequencing table memory module 205, and order module 204, sending module 206, wherein:
Described intercepting and capturing module 201, be used for producing interrupt request when computer system, the information of described interrupt request is mail in the process of described processor 106 by described interrupt sensors 101 or interrupting information register 102, intercept and capture the information of described interrupt request, and the information of described interrupt request is mail to order module 204.
Described sequencing table memory module 205 is used for the interruption sequencing table that storage is resequenced to the priority of whole interrupt request according to default optimization rules of arbitration.
Described order module 204, be used for after the information that receives the described interrupt request that described intercepting and capturing module 201 intercepts, compare with the respective interrupt request of corresponding sequencing table in the described sequencing table memory module 205, and re-start optimization according to interrupting the priority of sequencing table to the interrupt request of described intercepting and capturing, and the communication of the described interrupt request after will optimizing arrives described sending module 206.
Described sending module 206 is used for the information of the interrupt request after the described rearrangement is sent to described processor interrupt schedule device 105.
The polycaryon processor interrupt resources optimization process system of the embodiment of the invention, bonding apparatus and applied environment, in multi-core processor system, by threading interrupt manager 105, the soft interruption of optimization system (claim not only " software interruption ") and hard interruption the (but also title " hardware interrupts ").
Further, the described threading interrupt manager 103 of the embodiment of the invention, comprise that also affinity arranges module 203, be used for the classification according to described interrupt request, by preseting the affinity rule with interrupt register 104 corresponding to processor of described interrupt request distribution to appointment, the processor of binding appointment is processed described interrupt request.
Affinity (CPU affinity) refers to one or more interrupt sources are tied on the specific interrupt handler and moves, when intercepting threading interrupt manager 105 and interrupt optimizing such as the software and hardware interrupt request, by preseting the affinity regular allocation in the processor interrupt register 104 of appointment, the processor of binding appointment is processed described interrupt request.
As a kind of embodiment, the embodiment of the invention by calling one group of relevant grand affinity module 203 that arranges, is tied to one or more processes operation on one or more interrupt handlers 106 of appointment.
For example, in operating system look-at-me catalogue, for the hardware device of registering interrupt handling routine, there is one in the capital with the catalogue IRQ# of this interrupt number name under this catalogue, a smp_affinity file (SMP architecture) is arranged under the IRQ# catalogue, it is the bitmask of a processor, be used for arranging the affinity of this interruption, default value is 0xffffffff, show interrupt request is sent to all processors 106 processing of getting on, can change its affinity by changing this bitmask, interrupt request is tied to given processor process.
Further, the described threading interrupt manager 103 of the embodiment of the invention also comprises threading judge module 202, optimizes and revises for judging according to the nothing delay sign of described interrupt request whether this interrupt request can re-start.
In computer system, not all interrupt request can be by threading, interrupting such as clock is maintenance system time and timer etc., wherein timer is the pulse of operating system, in case by threading, just might be suspended, consequence is with hardly imaginable, so should be by threading like this.Therefore, in the embodiment of the invention, by arranging without postponing zone bit, and utilize threading judge module 202 to judge whether interrupt request can re-start and optimize and revise, if certain interruption need to be processed in real-time, interrupt such as clock, with stating own non-threading without postponing sign, need to process immediately in real time, and the wait of can not resequencing.
The polycaryon processor interrupt resources optimization process system of the embodiment of the invention, whole interrupt request of computer system at first, comprise soft interruption and hard the interruption, intercepted in the middle of the such interruptable controller of threading interrupt manager, the threading optimization of interrupting, thereby make equipment can not be higher than the rank of other interrupt request to the interrupt priority level of special interrupt request computing, the priority level that comprises hardware interrupts, the handling interrupt priority level of reduction regular interrupt task (containing hardware interrupts) is accelerated the processing of data.
Correspondingly, the embodiment of the invention also provides a kind of polycaryon processor interrupt resources optimized treatment method, as shown in Figure 3, as a kind of embodiment, comprises the steps:
Step S100, intercept and capture the interrupt request that all mails to a plurality of processors 106 in the polycaryon processor, and according to default optimization rules of arbitration whole interrupt request are carried out the priority adjustment, interrupt request task to polycaryon processor is dispatched variation, and the priority of interrupt request is resequenced;
Whole at least one interrupt request that mails to a plurality of processors 106 in the polycaryon processor of described intercepting and capturing had not only comprised soft interruption (but also claim " software interruption ") request, also comprised hard interruption (claiming again " hardware interrupts ") request.
Step S200 sends to described processor interrupt schedule device 105 with the described interrupt request after the ordering by the order after sorting and is dispatched to processor 106 processing.
Preferably, before the described step S100, also comprise the following steps:
Step S100 ', after computer system produced at least one interrupt request, the information of a plurality of interrupt sensors 101 receive interruption requests entered step S100 again.
After the described step S200, also comprise the following steps:
Step S200 ', processor interrupt schedule device 105 be according to the priority in the information of the interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to a plurality of processors and interrupts processing.
The polycaryon processor interrupt resources optimized treatment method of the embodiment of the invention, effectively improve the availability of processor, concentrate the higher real-time application interrupt request of superior resources processing priority demand, satisfy the requirement of different priorities task, the high-priority interrupt task is not interrupted or polycaryon processor is in time processed because of soft or hard, thereby improve computer processor performance, particularly the processing speed requirement of the high concurrent data of end-to-end large flow.Simultaneously, by processing in the middle of the different processor that interrupt task is assigned to polycaryon processor, thereby improve computing power and the affinity of polycaryon processor.
As shown in Figure 4, the below is take SMP(Symmetrical Multi-Processing) architecture is example, describe the polycaryon processor interrupt resources optimization process system and method for the embodiment of the invention in detail, but should be noted that, computer system of the present invention is not limited to the system of SMP architecture.
Step S100 ', step S100 ', after computer system produces at least one interrupt request, the information of a plurality of interrupt sensors 101 receive interruption requests.
Described step S100 ' comprises the following steps:
Step S110 ' from the interrupt request that computer system produces, comprises the interrupt request of trap, fault, termination, is transferred to interrupt sensors 101 places.
Wherein, the information of each interrupt request comprises unique interrupt request numbering byte or a vector (as being 8 signless integers), the numbering byte of described interrupt request or vector comprise label (IRQ_ID0) position, processed rank position, the mode position to the processor distribution is interrupted, the survival value position of interrupt request and (for example use four bit representation priority behind the vector, 0000 expression the 1st priority (limit priority), 0001 represents the 2nd priority without postponing zone bit ... 000F).
More preferably, non-shielding interruption and exception vector interrupt request, as the clock interrupt request be masked as 1 without postponing, expression can not re-start and optimize and revise, and has limit priority, needs in real time without delay disposal; And the nothing of maskable interrupts postpones to be masked as 0, and expression can re-start and optimize and revise, and optimizes and revises by threading interrupt manager 103 is changed.
Step S120 ', scan to interrupt sensors 101 with the clock period, obtain the information of the interrupt request of interrupt sensors, dump in the middle of the interrupting information register 102, and the information of the interrupt request of cleaning in the interrupt sensors 101, comprise the mode of interrupting IRQ_ID, priority processing rank, interrupting to the processor distribution, survival value and without postponing zone bit.
Like this, the interrupting information register has been intercepted and captured the interrupt request of actual generation, and concrete interrupt request is carried out buffer memory.
Wherein, as a kind of embodiment, preferably, the information that an interrupting information register 102 is used for the request of buffer memory hardware interrupts can be set, such as the information of the interrupt request of network interface card and hard disk; Other arranges the information that an interrupting information register 102 is used for the cache software interrupt request, such as the information of the interrupt request of keyboard and application.
Step S100, intercept and capture the interrupt request that all mails to a plurality of processors 106 in the polycaryon processor, and according to default optimization rules of arbitration to whole interrupt request thread, carry out the priority adjustment, interrupt request task to polycaryon processor is dispatched variation, and the priority of interrupt request is resequenced;
Described step S100 comprises the steps:
Step S110, threading interrupt manager 103 intercepts and captures and copies and delete the information of the interrupt request of buffer memory in the interrupting information register 102 by the clock period of setting, the mode that comprises IRQ_ID, priority processing rank, interrupts to the processor distribution, survival value and without postponing sign etc.
Step S120 is according to judging whether this interrupt request can re-start and optimize and revise without postponing sign in the described interrupt request; If so, then enter step S130; Otherwise, change step S200 ' over to, directly interrupt request is sent to processor interrupt schedule device 105 and process.
Step S130, the information of interrupt request is set as index with the IRQ_ID of source interrupt request, correspond to the central source row of prioritization table of threading interrupt manager 103, and by being optimized adjustment corresponding to purpose row in the prioritization table of source row, again its priority is sorted, rewrite the priority processing rank of ordering, and the information of the interrupt request after will resequencing stores in the middle of the threading interrupt manager 103 into.
Preferably, for each de novo interrupt request that computer system produces, all can be again other by setting Sort Priority in this step, thus the rearrangement optimization of realization interrupt priority level.
As a kind of embodiment, the prioritization table of described threading interrupt manager 103 is Database Lists modules of the priority of the interrupt request that arranges according to default optimization rules of arbitration, and it comprises source row, purpose row, time value etc.
As a kind of embodiment, do not affecting under the prerequisite that clock interrupts and interrupt without delay, with to destination application with and relevant hardware device as optimizing direction, and adjust according to hardware performance and equipment performance target, under the full load environment, the availability of the maximum performance equipment of energy does not cause internal memory to overflow for adjusting the experience of foundation because the task time-delay causes simultaneously.For example: need optimum detection and fingerprint engine and network interface card related hardware during the end-to-end flux content detection.For selected device internal memory, processor model, according to used bandwidth traffic size and task how much, adjust and interrupt processing priority level, thereby guarantee that all tasks can normal process, core application can priority processing, in conjunction with computing power and internal memory processing power, the normal operation of assurance equipment can not overflowed.
As a kind of embodiment, described source row comprise mode, the source survival value that interrupt to the processor distribution in source IRQ_ID, source priority processing rank, source; Described purpose row comprise mode, the purpose survival value that purpose IRQ_ID, purpose processing rank, purpose are interrupted to the processor distribution; Described time value comprises that interrupt request attack time, last time read break period, interrupt reading the time interval and real-time record content row etc.
In the embodiment of the invention, as a kind of embodiment, described optimizing and revising, again its priority is sorted, rewrite the priority processing rank of ordering, can be as set take non-clock interrupt request, according to default optimization rules of arbitration, optimize the higher core stage real-time interrupt request of priority level demand, carry out the priority rearrangement by the prioritization table, and different according to business demand and hardware device, set the source priority level of look-at-me IRQ at threading interrupt manager 105, and the processor that signal is assigned to appointment is processed.
Described optimization rules of arbitration, be to real-time task after limited number of time detects, according to demand and the hardware device response time requirement of different interrupt request, set with empirical value.
As a kind of embodiment, when setting the optimization rules of arbitration, carried out meeting according to system interrupt request under the prerequisite of reasonable request of application safety engine, change network interface, the interrupt request priority level of application gateway security engine real-time program, reduced simultaneously the standby interrupt levels of last reset, repeatedly combination and the test of process and selected ardware feature and end-to-end content detection technique, these interrupt request are adjusted at the situation of system optimal, in debug process, sum up the actual effectively priority level of a cover, in conjunction with selected hardware, the priority of interrupting and application are optimized rank adjusting and set.At hardware aspect, the interrupt priority level that improves the network data interface is other, makes the response demand priority level of network data aspect higher, inserts faster formation, and the computational resource that more preferably obtains faster and more processor is processed.To having carried out the IRQ level optimization and improvement such as this real-time application of end-to-end content detection technique, improve processing priority other, and process in the middle of being automatically assigned to different processors simultaneously.
Further, as a kind of embodiment, described default optimization rules of arbitration also can according to the load pressure analysis of the on-the-spot busy state of the continuity correlativity of interrupt request and operation hours, be optimized the setting of rules of arbitration; Perhaps in conjunction with described to real-time task after limited number of time detects, demand and hardware device response time requirement according to different interrupt request are optimized the setting of rules of arbitration with empirical value.
Be optimized the setting of rules of arbitration according to the continuity correlativity of interrupt request, thereby increase its affinity; The load pressure of the on-the-spot busy state when moving with equipment is analyzed rear setting, thereby the idle processor of distributing to non-affinity restriction is processed.The interrupt request that priority level is high will have precedence over the distribution that the not low interrupt request of interrupt priority level obtains processor interrupt schedule device 105, and preferentially be carried out by processor 106; The interrupt request that priority level is low is queued and waits for the processing of processor interrupt schedule device 105 re invocations.
Step S200 sends to described processor interrupt schedule device 105 with the described interrupt request after the ordering by the order after sorting and is dispatched to processor 106 processing.
Processor interrupt register 104, according to the clock period of setting, judge and when satisfying condition, copy and delete the information of interrupt request from threading interrupt manager 103, the mode and the survival value that comprise the good IRQ_ID of rearrangement, priority processing rank, interrupt to the processor distribution.
Preferably, if specified the information of carrying out this interrupt request in the information in the mode of interrupting to processor distribution, then the information of interrupt request is stored in the middle of the processor interrupt register of appointment.
Preferably, described judgement also satisfies condition, and comprises the steps:
Step S210 judges in the described mode of interrupting to the processor distribution the information of the interrupt request that copies from threading interrupt manager 103, and whether the label (ID) of given processor is arranged; If the ID of given processor is arranged, then enter step S220; If there is not the ID of given processor, then enter step S230;
Step S220, the information of the interrupt request that has existed in the described mode of interrupting to the processor distribution the information of the interrupt request that will copy from threading interrupt manager 103 and the processor interrupt register 104 of appointment is compared, the priority of the interrupt request whether priority of the interrupt request that judgement copies from threading interrupt manager 103 has more preferably had in the processor interrupt register 104 of appointment; If so, then the described interrupt request that copies from threading interrupt manager 103 is transferred to the processor interrupt register 104 of appointment; Otherwise, directly return threading interrupt manager 103, and do not delete the information of described interrupt request;
Step S230, in the situation that do not specify interrupt handler 106, the information of interrupt request and processor interrupt register 104 are held consultation, and determine that processor receives the processing of current interrupt request; If consult successfully, then enter step S220 and process; If fail to consultations, then return threading interrupt manager 103, and it is capable not delete the record of its interrupt request.
Described negotiation determines it is a kind of prior art, therefore in embodiments of the present invention, describes in detail no longer one by one.
Step S200 ', processor interrupt schedule device 105 be according to the priority in the information of the interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to a plurality of processors and interrupts processing.
Particularly, described step S200 ' comprises the following steps:
Step S210 ', processor interrupt register 104 receives the information of the interrupt request of optimizing at threading interrupt manager 103 places, and interrupt request sequentially resequenced by the optimization of resetting in the threading interrupt manager 103, be cached in the middle of the record tabulation of the interrupt request after the rearrangement of processor interrupt register 104.
Step S220 ', the duty of processor interrupt schedule device 105 record current processors 106, and press the record tabulation of the interrupt request after the rearrangement in the middle of the setting cycle query processor interrupt register 104, compare with the record of interrupt request in the processor interrupt schedule device 105, enter step S230 ';
Described duty comprises current interrupt task quantity, and whether the IRQ_ID of each interrupt task, priority level, executing state are in hang-up, the mission number of current running status;
Step S230 ', according to processor interrupt register 104 in the judged result compared, determine whether that the higher interrupt request of priority needs to process; If have, then enter the processor 106 of appointment; If no, then return in the middle of the processor interrupt register 104, return step S210 ' etc. pending;
Like this, for non-clock interrupt request, it can not broadcast forwarding between a plurality of processors 106, can do not broadcasted to a plurality of processors 106 by processor interrupt schedule device 105 yet, any interruption that is stored in the processor interrupt register 104, the processor 106 that only can send to appointment is carried out processing, thereby has shortened the time of carrying out.
Step S240 ', processor 106 be the up-to-date interrupt request that provides of receiving processor interrupt schedule device 105 respectively, to 105 responses of processor interrupt schedule device and inform and can suspend and current processing of the task of on-hook; And after finishing the interrupt task of highest level, carry out again the highest interrupt task of current queue medium priority.
For the look-at-me that enters polycaryon processor 106, can directly wake function interruption processing threads up by calling, and bring into operation, call hard interrupt function and adjust corresponding interrupt priority level, it is processed that this function will judge whether that interruption needs, and just call the handling interrupt event functions and process if having.The handling interrupt event functions will directly call corresponding interruption processing function and finish the interruption processing.
The embodiment of the invention transforms the priority level that different software and hardwares interrupts processing by interrupt thread manager 103, submits to respectively polycaryon processor 106 and processes.When the computer system interrupt request occurs again, the interrupt request that forwards by interrupt sensors 101, no matter be soft interrupt request or hard interrupt request, its priority all re-starts and optimizes and revises, after comparing and sorting, in the formation with the interrupt request insert handling interrupt request after the rearrangement.
The polycaryon processor interrupt resources optimization process system and method for the embodiment of the invention, through reality to the end-to-end content detection of real-time program, using front and back of the present invention, show by test comparison, use polycaryon processor interrupt resources optimization process system and method for the present invention, the computing machine overall performance has promoted 10% under the large high concurrent environment of flow.
The polycaryon processor interrupt resources optimization process system and method for the embodiment of the invention can promote the holistic management that interrupt priority level is changed effectively, solves to reduce the problem that the maintainer too disperses interrupting management link.By calculating interrupting being applied in the given processor, improved processor affinity, thereby effectively reduced locking of Multi-core and subtracted latching operation, response speed and processing speed have been promoted, promoted processor to optimizing the priority processing of look-at-me, improve the handling property of core business, set up efficient application software and hardware device for device upgrade fast and effectively, but the also optimization of the Adjustment System of fast and flexible.
Should be noted that at last obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (13)
1. a polycaryon processor interrupt resources optimization process system comprises processor interrupt schedule device (105), and a plurality of processor (106), it is characterized in that:
Also comprise threading interrupt manager (103), be used for intercepting and capturing the interrupt request that all mails to described a plurality of processor (106), and according to default optimization rules of arbitration described interrupt request is carried out the priority adjustment, priority to described interrupt request is resequenced, and the described interrupt request after then will sorting sends to described processor interrupt schedule device (105) by the order after sorting and is dispatched to described a plurality of processor (106) processing.
2. polycaryon processor interrupt resources optimization process according to claim 1 system, it is characterized in that, also comprise a plurality of interrupt sensors (101), be used for after computer system produces at least one interrupt request, receive the information of described interrupt request, and the information of described interrupt request is mail to described threading interrupt manager (103).
3. polycaryon processor interrupt resources optimization process according to claim 2 system, it is characterized in that, also comprise and the corresponding a plurality of interrupting information registers of described a plurality of interrupt sensors (101) (102), and with the corresponding a plurality of processor interrupt registers of described a plurality of processors (106) (104), wherein:
Described a plurality of interrupting information registers (102) are used for buffer memory mails to the described interrupt request of described threading interrupt manager (103) from described a plurality of interrupt sensors (101) information;
Described a plurality of processor interrupt registers (104) are used for buffer memory sends at least one rearrangement of described processor interrupt schedule device (105) from described threading interrupt manager (103) the information of described interrupt request;
Described processor interrupt schedule device (105) is according to the priority in the information of the described interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to described a plurality of processor (106) and interrupts processing.
4. according to claim 1 to 3 each described polycaryon processor interrupt resources optimization process systems, it is characterized in that, described threading interrupt manager (103), comprise and intercept and capture module (201), sequencing table memory module (205), order module (204), sending module (206), wherein:
Described intercepting and capturing module (201), be used for producing interrupt request when computer system, the information of described interrupt request is mail in the process of described a plurality of processor (106) by described interrupt sensors (101) or interrupting information register (102), intercept and capture the information of described interrupt request, and the information of described interrupt request is mail to order module (204);
Described sequencing table memory module (205) is used for the interruption sequencing table that storage is resequenced to the priority of whole interrupt request according to default optimization rules of arbitration;
Described order module (204), be used for after the information that receives the described interrupt request that described intercepting and capturing module intercepts, compare with the respective interrupt request of corresponding sequencing table in the described sequencing table memory module (205), and re-start optimization according to interrupting the priority of sequencing table to the interrupt request of described intercepting and capturing, and the communication of the described interrupt request after will optimizing arrives described sending module (206);
Described sending module (206) is used for the information of the interrupt request after the described rearrangement is sent to described processor interrupt schedule device (105).
5. polycaryon processor interrupt resources optimization process according to claim 4 system is characterized in that, described threading interrupt manager (103) comprises that also affinity arranges module (203) and threading judge module (202), wherein:
Described affinity arranges module (203), be used for the classification according to described interrupt request, by preseting the affinity rule with the processor interrupt register (104) of described interrupt request distribution to processor (106) correspondence of appointment, bind the processor (106) of described appointment and process described interrupt request;
Described threading judge module (202) is optimized and revised for judging according to the nothing delay sign of described interrupt request whether this interrupt request can re-start.
6. a polycaryon processor interrupt resources optimized treatment method is characterized in that, comprises the steps:
Steps A is intercepted and captured the interrupt request that all mails to a plurality of processors (106) in the polycaryon processor, and according to default optimization rules of arbitration whole interrupt request is carried out the priority adjustment, and the priority of interrupt request is resequenced;
Step B sends to described processor interrupt schedule device (105) with the described interrupt request after the ordering by the order after sorting and is dispatched to processor (106) processing.
7. polycaryon processor interrupt resources optimized treatment method according to claim 6 is characterized in that:
Before the described steps A, also comprise the following steps:
Steps A ', after computer system produced at least one interrupt request, the information of a plurality of interrupt sensors (101) receive interruption request entered steps A again;
After the described step B, also comprise the following steps:
Step B ', processor interrupt schedule device (105) be according to the priority in the information of the interrupt request of at least one rearrangement, after described interrupt request is ranked, is input to a plurality of processors and interrupts processing.
8. polycaryon processor interrupt resources optimized treatment method according to claim 7 is characterized in that described steps A ' comprise the following steps:
Steps A 10 ' from the interrupt request that computer system produces, comprises the interrupt request of trap, fault, termination, is transferred to interrupt sensors (101) and locates;
Wherein, the information of each interrupt request comprises a unique interrupt request numbering byte or vector, and the numbering byte of described interrupt request or vector comprise the IRQ_ID0 position, processed rank position, the mode position to the processor distribution is interrupted, survival value position of interrupt request and without postponing zone bit;
Steps A 20 ' scanned to interrupt sensors (101) with the clock period, obtained the information of the interrupt request of interrupt sensors, dump in the middle of the interrupting information register (102), and the information of the interrupt request in the cleaning interrupt sensors (101).
9. according to claim 6 or 7 described polycaryon processor interrupt resources optimized treatment methods, it is characterized in that, described steps A comprises the steps:
Steps A 10, threading interrupt manager (103) intercept and capture and copy and delete the information of the interrupt request of buffer memory in the interrupting information register (102) by the clock period of setting;
Steps A 20 is according to judging whether this interrupt request can re-start and optimize and revise without postponing sign in the described interrupt request; If so, then enter steps A 30; Otherwise, change step B ' over to, directly interrupt request is sent to processor interrupt schedule device (105) and process;
Steps A 30, the information of interrupt request is set as index with the IRQ_ID of source interrupt request, correspond to the central source row of prioritization table of threading interrupt manager (103), and by being optimized adjustment corresponding to purpose row in the prioritization table of source row, again its priority is sorted, rewrite the priority processing rank of ordering, and the information of the interrupt request after will resequencing stores in the middle of the threading interrupt manager (103) into.
10. polycaryon processor interrupt resources optimized treatment method according to claim 9, it is characterized in that, the prioritization table of described threading interrupt manager (103), be the Database Lists module of the priority of the interrupt request that arranges according to default optimization rules of arbitration, it comprises source row, purpose row, time value;
Described source row comprise mode, the source survival value that interrupt to the processor distribution in source IRQ_ID, source priority processing rank, source;
Described purpose row comprise mode, the purpose survival value that purpose IRQ_ID, purpose processing rank, purpose are interrupted to the processor distribution;
Described time value comprises that interrupt request attack time, last time read break period, interrupt reading the time interval and real-time record content row.
11. according to claim 6 or 7 described polycaryon processor interrupt resources optimized treatment methods, it is characterized in that, described step B comprises the following steps:
According to the clock period of setting, judge and when satisfying condition, copy and delete the information of interrupt request from threading interrupt manager (103), the mode and the survival value that comprising the good IRQ_ID of rearrangement, priority processing rank, interrupting to the processor distribution.
12. polycaryon processor interrupt resources optimized treatment method according to claim 11 is characterized in that described judgement also satisfies condition, and comprises the steps:
Step B10 judges in the described mode of interrupting to the processor distribution the information of the interrupt request that copies from threading interrupt manager (103), and whether the ID of given processor is arranged; If the ID of given processor is arranged, then enter step B20; If there is not the ID of given processor, then enter step B30;
Step B20, the information of the interrupt request that has existed in the described mode of interrupting to the processor distribution the information of the interrupt request that will copy from threading interrupt manager (103) and the processor interrupt register (104) of appointment is compared, the priority of the interrupt request whether priority of the interrupt request that judgement copies from threading interrupt manager (103) has more preferably had in the processor interrupt register (104) of appointment; If so, then the described interrupt request that copies from threading interrupt manager (103) is transferred to the processor interrupt register (104) of appointment; Otherwise, directly return threading interrupt manager (103), and do not delete the information of described interrupt request;
Step B30, in the situation that do not specify interrupt handler (106), the information of interrupt request and processor interrupt register (104) are held consultation, and determine that processor receives the processing of current interrupt request; If consult successfully, then enter step B20 and process; If fail to consultations, then return threading interrupt manager (103), and it is capable not delete the record of interrupt request.
13. polycaryon processor interrupt resources optimized treatment method according to claim 7 is characterized in that described step B ' comprises the following steps:
Step B10 ', processor interrupt register (104) receives the information of the interrupt request that threading interrupt manager (103) locates to optimize, and interrupt request sequentially resequenced by the optimization of resetting in the threading interrupt manager (103), be cached in the middle of the record tabulation of the interrupt request after the rearrangement of processor interrupt register (104);
Step B20 ', the duty of processor interrupt schedule device (105) record current processor (106), and the record of pressing the interrupt request after the central rearrangement of setting cycle query processor interrupt register (104) is tabulated, compare with the record of interrupt request in the processor interrupt schedule device (105), enter step B30 ';
Described duty comprises current interrupt task quantity, and whether the IRQ_ID of each interrupt task, priority level, executing state are in hang-up, the mission number of current running status;
Step B30 ', according to processor interrupt register (104) in the judged result of comparison, determine whether that the higher interrupt request of priority needs to process; If have, then enter the processor (106) of appointment; If no, then return in the middle of the processor interrupt register (104), return step B10 ' etc. pending;
Step B40 ', the up-to-date interrupt request that processor (106) difference receiving processor interrupt schedule device (105) provides responds and informs meeting time-out and current processing of the task of on-hook to processor interrupt schedule device (105); And after finishing the interrupt task of highest level, carry out again the highest interrupt task of current queue medium priority.
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| CN112130904B (en) * | 2020-09-22 | 2024-04-30 | 黑芝麻智能科技(上海)有限公司 | Processing system, inter-processor communication method, and shared resource management method |
| CN112650591A (en) * | 2021-01-05 | 2021-04-13 | 上海擎昆信息科技有限公司 | Method, device and system for adjusting interrupt priority |
| CN112650591B (en) * | 2021-01-05 | 2024-05-14 | 上海擎昆信息科技有限公司 | Method, device and system for adjusting interrupt priority |
| CN113918311B (en) * | 2021-12-10 | 2022-07-01 | 北京智芯微电子科技有限公司 | Soft interrupt routing method of multi-core system and method and chip for responding soft interrupt |
| CN113918311A (en) * | 2021-12-10 | 2022-01-11 | 北京智芯微电子科技有限公司 | Soft interrupt routing method of multi-core system and method and chip for responding soft interrupt |
| CN115344374A (en) * | 2022-10-19 | 2022-11-15 | 成都菁蓉联创科技有限公司 | Interrupt response method and system thereof |
| CN117492994A (en) * | 2023-11-02 | 2024-02-02 | 北京智芯微电子科技有限公司 | Method, device, chip, equipment and medium for running interrupt program between cores |
| CN117573308A (en) * | 2023-11-15 | 2024-02-20 | 中国三峡建工(集团)有限公司 | Task interrupt arbitration method, system, chip and storage medium |
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