WO2021128249A1 - Processor, task response method, movable platform, and camera - Google Patents

Abstract

A processor (300), a task response method, a movable platform, a camera, and a computer readable storage medium. The processor (300) comprises a bus interface (306), a control register (304), and a controller (302). The bus interface (306) can be coupled to a plurality of dedicated modules (308, 310, 312, 314) at the exterior of the processor (300) and can be used to receive a plurality of task completion requests for the plurality of dedicated modules (308, 310, 312, 314). The control register (304) is used to store a plurality of response means of the processor (300) in response to the plurality of dedicated modules (308, 310, 312, 314), the plurality of response means being different. The processor (300) responds to the plurality of task completion requests of the plurality of dedicated modules (308, 310, 312, 314) according to the corresponding response means in the control register (304). System efficiency can be improved according to the described processor, task response method, movable platform, camera, and computer readable storage medium.

Description

Processor, task response method, movable platform, and camera Technical field

This application relates to the field of computer technology, and in particular to a processor, a task response method, a movable platform, a camera, and a computer-readable storage medium.

Background technique

With the continuous development of technology, the instructions or functions processed and executed by the central processing unit (Center Process Unit, hereinafter referred to as CPU) are limited. If you completely rely on the CPU to handle certain specific tasks, you will not be able to efficiently complete these specific tasks. Therefore, in order to improve the execution efficiency of the CPU and improve the system functions, co-processor units or acceleration processing units with specific functions (hereinafter collectively referred to as dedicated modules) will be added around the CPU to allow the CPU and dedicated modules to work in parallel to improve The efficiency of the overall system. However, when the CPU interacts with the dedicated module, it may interrupt the task that the CPU is processing, which results in a decrease in system efficiency.

Summary of the invention

In view of this, embodiments of the present invention provide a processor, a task response method, a movable platform, a camera, and a computer-readable storage medium.

According to the first aspect of the embodiments of the present application, a processor is provided, including a bus interface and a control register. Wherein, the bus interface can be coupled to a plurality of dedicated modules outside the processor, and is used to receive a plurality of task completion requests related to the plurality of dedicated modules. The control register is used to store a plurality of response modes of the processor in response to a plurality of the dedicated modules; wherein, a plurality of the response modes are different. The processor is coupled to the control register, and is configured to respond to the multiple task completion requests of the multiple dedicated modules according to the corresponding response mode in the control register.

According to a second aspect of the embodiments of the present application, there is provided a task response method, including: receiving multiple task completion requests corresponding to multiple dedicated modules coupled to a bus interface and located outside the processor; and obtaining the processor Respond to multiple response modes of multiple dedicated modules, and store multiple response modes in a control register; wherein multiple response modes are different; and according to the corresponding response in the control register Way, responding to a plurality of said task completion requests of a plurality of said dedicated modules.

According to a third aspect of the embodiments of the present application, a computer-readable storage medium storing computer instructions is provided. When the computer instructions are executed by one or more processors, the one or more processors perform actions including the following: receiving multiple dedicated modules that are coupled to the bus interface and located outside the processor. Task completion request; acquiring multiple response modes of the processor in response to multiple dedicated modules, and storing multiple response modes in a control register; wherein a plurality of the response modes are different; and according to the The corresponding response mode in the control register responds to a plurality of the task completion requests.

According to the fourth aspect of the embodiments of the present application, a movable platform is provided. The movable platform includes the processor mentioned in the first aspect of the embodiments of the present application.

According to a fifth aspect of the embodiments of the present application, a camera is provided. The camera includes the processor mentioned in the first aspect of the embodiments of the present application.

The processor, task response method, movable platform, camera, and computer-readable storage medium according to the embodiments of the present invention can improve system efficiency.

Description of the drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The exemplary embodiments and descriptions of the application are used to explain the application, and do not constitute an improper limitation of the application. In the attached picture:

Fig. 1 is a schematic diagram of a processor and a dedicated module according to an embodiment of the present invention;

FIG. 2 is a flowchart of the interrupt response mode of the processor shown in FIG. 1;

3 is a schematic diagram of a processor and multiple dedicated modules according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of the configuration of the control register shown in FIG. 1;

FIG. 5 is a schematic diagram of a query instruction of the processor shown in FIG. 1;

Fig. 6a is a flowchart of the processor shown in Fig. 1 responding to a dedicated module in a query mode according to an embodiment of the present invention;

Fig. 6b is a flowchart of the processor shown in Fig. 1 responding to the dedicated module in the query mode according to an embodiment of the present invention;

Fig. 7a is a schematic diagram of the processor shown in Fig. 1 using a pseudo code of a query instruction according to an embodiment of the present invention;

Fig. 7b is a schematic diagram of the processor shown in Fig. 1 using a pseudo code of a query instruction according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a detection unit in the processor shown in FIG. 1;

FIG. 9 is a schematic diagram of a detection module in the processor shown in FIG. 1;

Fig. 10 is a flowchart of a task response method according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely in conjunction with specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

With the continuous development of technology, the instructions or functions that can be executed by the central processing unit (Center Process Unit, hereinafter referred to as CPU) are limited. If you completely rely on the CPU to handle certain tasks, you will not be able to efficiently complete certain tasks. Therefore, in order to improve the execution efficiency of the CPU and improve the system functions, in today’s common systems, co-processor units or acceleration processing units with specific functions (hereinafter collectively referred to as dedicated modules) are added around the CPU, so that the CPU and dedicated Modules work in parallel to improve the efficiency of the overall system.

See Figure 1. Fig. 1 is a schematic diagram of a processor and a dedicated module according to an embodiment of the present invention. The processor 106 (for example, CPU) exchanges data with the memory 102 through the system bus 104. In addition, the processor 106 performs data interaction with various special modules through the internal bus 110. That is to say, structurally, these dedicated modules are connected to the processor through the internal bus 110, so as to receive instructions or configuration signals from the processor. Furthermore, these dedicated modules can send a completion request to the processor after completing a specific task. In addition, these dedicated modules are also connected to each other through the internal bus 110. Among them, these dedicated modules can be a graphics processing module (Graphic Process Unit, GPU) 120, a vector computing module (Vector Process Unit) 112, a floating point processing module (Floatpoint Process Unit, FPU) 114, and direct memory access A module (Direct Memory Access, DMA) 108 or a similar dedicated processing unit capable of processing a special computing task. For example, artificial intelligence (AI) accelerator 118, fast Fourier transform (Fast Fourier Transform, FFT) 116, and so on. These dedicated modules can extend the processing capabilities of the processor by extending the instruction set or providing configuration registers. However, the present invention is not limited to this, and may also include dedicated modules for realizing other functions.

Take the data transfer of the processor 106 to the memory 102 as an example. A group of DMA 108 is added between the processor 106 and the memory 102 as a dedicated module. The processor 106 sends configuration information to the DMA 108 to configure the configuration registers in the DMA 108, and informs the DMA 108 of information such as the address where the data needs to be transferred from the memory 102 and the size of the data to be transferred. After the configuration is completed, the DMA 108 transfers data to the memory 102 through the system bus 104 according to the configuration information of the processor 106. In the process of transferring data by the DMA 108, the processor 106 does not intervene in the process of transferring data by the DMA 108, so other tasks can be processed. When the DMA 108 completes the task of transferring data, the DMA 108 will issue an interrupt request to the processor 106. After the processor 106 receives the interrupt request sent by the DMA 108, it stops other tasks being processed, and responds to the interrupt request sent by the DMA 108. In the interrupt service function corresponding to the interrupt request, the processor 106 processes the memory data transported back by the DMA 108, and continues to execute the interrupted task with the result and status of this operation.

After the DMA108 task is completed, the above-mentioned response mode of the processor 106 in response to the DMA108 is called an interrupt response mode. See Figure 2. Fig. 2 is a flowchart of the interrupt response mode of the processor shown in Fig. 1. In the interrupt response mode, as shown in step S202, the processor (for example, CPU) configures a dedicated module (for example, DMA), and sends configuration signals or other instructions related to the dedicated module to the dedicated module. At this time, as shown in step S222, the dedicated module receives the configuration signal from the processor and configures the configuration register in the dedicated module, and the dedicated module receives other instructions to perform operations related to these instructions. In one embodiment, the processor sends a configuration signal to the dedicated module (for example, DMA) for configuring the configuration register in the dedicated module.

In step S204, the processor performs other tasks. At this time, as shown in step S224, the dedicated module starts to work after configuring the configuration register. For example, the dedicated module starts to perform operations or processing related to configuration signals or other instructions. As shown in step S226, after completing the operation or processing related to the configuration signal or other instructions sent by the processor, the dedicated module sends a task completion request to the processor.

In step S206, although the processor is executing other tasks, once the processor receives the task completion request sent by the dedicated module, other tasks being executed by the processor are interrupted. At this time, the processor enters the interrupt service routine.

As shown in step S208, after the interrupt service routine is executed, the processor continues to execute other tasks that were previously executed and were interrupted.

As shown in step S210, after executing the previously executed and interrupted task, the processor enters an idle state or executes a new task.

It should be pointed out that there are some shortcomings when the processor interacts with a dedicated module in an interrupt response mode, as shown below:

First of all, when the dedicated module completes the task and issues an interrupt request, no matter what the processor is currently doing, the processor needs to respond to the interrupt request sent by the dedicated module, which means that the task currently processed by the processor will definitely be interrupted. Therefore, to some extent, this way of interaction and response interferes with the process of tasks being processed by the processor. Take DMA to move data as an example. If the data that DMA needs to move is small, but the number of transfers is large, the tasks that the processor is processing will be continuously interrupted, which will reduce the efficiency of the system.

Secondly, when the dedicated module completes the task, if there is no dependency between the task processing result of the dedicated module and the task currently processed by the processor, then it does not make any sense to interrupt the task being processed by the processor. Taking DMA to transfer data as an example, if the task being processed by the processor does not require data to be transferred by DMA, then the processor responds to the interrupt request of the DMA at this time, which is meaningless for the task being processed by the processor. Moreover, if the task being processed by the processor has higher real-time requirements, then responding to the interrupt request of the dedicated module will reduce the real-time performance of the task being processed by the processor.

Based on the foregoing problems, the embodiments of the present application provide a processor, a task response method, a movable platform, a camera, and a computer-readable storage medium, which can improve system efficiency. It should be noted that the embodiments of the present application provide a processor, a task response method, and a computer-readable storage medium, which are applicable to any system with an acceleration unit or a co-processing unit. For example, the processor and the task response method can be applied to devices with networking, such as mobile phones, computers, personal tablets, or PDAs (Personal Digital Assistant, personal digital assistants). Alternatively, the processor and task response method can also be applied to mobile platforms (such as unmanned aerial vehicles, unmanned vehicles or unmanned ships), cameras, sweeping robots, or smart speakers and other equipment.

According to an embodiment of the present invention, a processor is proposed, which includes a bus interface and a control register. Among them, the bus interface can be coupled to multiple dedicated modules outside the processor, and is used to receive multiple task completion requests related to multiple dedicated modules; and a control register is used to store the processor in response to multiple dedicated modules. Response mode; wherein multiple response modes are different; wherein, the processor responds to multiple task completion requests of multiple dedicated modules according to the corresponding response mode in the control register.

According to another embodiment of the present invention, a movable platform is provided. The movable platform includes the above-mentioned processor.

According to another embodiment of the present invention, a camera is provided. The camera includes the above-mentioned processor.

It should be noted that the present invention is not limited to this, the processor may also further include a controller, which is coupled to the control register, for responding to a plurality of the dedicated modules according to the corresponding response mode in the control register A number of said task completion requests. See Figure 3. Fig. 3 is a schematic diagram of a processor and multiple dedicated modules according to another embodiment of the present invention. The processor 300 includes a controller 302, a control register 304, and a bus interface 306. Among them, the bus interface 306 can be coupled to multiple dedicated modules outside the processor 300 for receiving multiple task completion requests related to these dedicated modules. The control register 304 is used to store multiple response modes of the processor 300 in response to these dedicated modules. These multiple response modes are different from each other. The controller 302 is coupled to the control register 304, and is configured to respond to multiple task completion requests of these dedicated modules according to the corresponding response mode in the control register 304.

In FIG. 3, a processor 300 (for example, a CPU) is connected to N specific function units (SFU) through an internal bus. The system numbers N dedicated modules and ensures that the numbers of all dedicated modules are not repeated. As shown in Figure 3, the N dedicated modules are dedicated module SFU ₁ 308, dedicated module SFU ₂ 310, dedicated module SFU ₃ 312... and dedicated module SFU _N 314. It can be seen from FIG. 3 that in this embodiment, there is no need to change the connection mode of the internal bus. In another embodiment, the system can classify N dedicated modules. For example, the special modules are classified according to their functions and uses, and the special modules are numbered according to different classification results. For example, if there are two dedicated modules with different functions, the dedicated modules with different functions are numbered with different codes. If there are multiple dedicated modules A1, A2, and A3 with A function and multiple dedicated modules B1, B2, and B3 with B function, then the dedicated modules A1, A2, and A3 are encoded as 000, 001, 010, and the dedicated modules B1, B2 and B3 are coded as 100, 101, 110. That is, 4 bits are used to encode the dedicated modules A1, A2, and A3 and the dedicated modules B1, B2, and B3. Among them, when the highest bit of the number of the dedicated module is "0", it means that the dedicated module is a dedicated module with A function. When the highest bit of the dedicated module number is "1", it means that the dedicated module is a dedicated module with B function. Or, when the highest bit of the number of the dedicated module is "1", it means that the dedicated module is a dedicated module with A function. When the highest bit of the dedicated module number is "0", it means that the dedicated module is a dedicated module with B function. In other words, as long as the highest bit values of dedicated modules with different functions are different. For example, if there are multiple graphics processing modules and multiple artificial intelligence accelerators, the highest bit of the multiple image processing modules is coded as "0", and the highest bit of the multiple artificial intelligence accelerators is coded as "1". However, the present invention is not limited to this. Other coding methods that can realize the coding and classification of dedicated modules all fall into the protection scope of the present invention.

According to an embodiment of the present invention, the processor responds to the N dedicated modules in multiple response modes. For example, multiple response modes include interrupt mode and query mode. In the query mode, the processor (for example, CPU) checks whether the dedicated module has completed the task by executing the query instruction. If the dedicated module has not completed the task, the processor enters the suspended state; if it is detected that the dedicated module has completed the task, the processor can execute subsequent instructions. Since the query instruction executed by the processor is determined according to the algorithm or system requirements, it can be ensured that the processor is in an idle state when the query instruction is executed, or the processor urgently needs to use the calculation result of the dedicated module at this time.

In the processor 300, a set of control registers (CR) 304 is added, and the bit width of the control register 304 is N bits. Each bit on the control register 304 has a one-to-one correspondence with N dedicated modules. That is, each bit on the control register 304 corresponds to the dedicated module SFU ₁ 308, the dedicated module SFU ₂ 310, the dedicated module SFU ₃ 312... and the dedicated module SFU _N 314, respectively.

In one embodiment, the control register 304 includes the first bit. _{The first bit is used to store the first dedicated module (eg, dedicated module SFU 1} 308, dedicated module SFU ₂ 310, dedicated module SFU ₃ 312) among a plurality of dedicated modules (eg, N dedicated modules) corresponding to the processor 300 response. ...And the first response mode of one of the dedicated modules SFU _{N 314).} Among them, when the first bit is "0", the first response mode is the interrupt mode; when the first bit is "1", the first response mode is the query mode. Or, when the first bit is "1", the first response mode is an interrupt mode; when the first bit is "0", the first response mode is a query mode. In other words, as long as the bit values of the bits corresponding to the two response modes are different.

According to an embodiment of the present invention, each bit of the control register 304 can be configured as a logic 1 or a logic 0. When a certain bit of the control register 304 is configured as a logic 1, the response mode of the processor 300 in response to the corresponding dedicated module is the query mode. In other words, the bit is configured in the query mode at this time. When a bit of the control register 304 is configured as a logic 0, the response mode of the processor 300 in response to the corresponding dedicated module is an interrupt mode. In other words, the bit is configured in interrupt mode at this time.

In addition, in other embodiments, when a bit of the control register 304 is configured as a logic 0, the response mode of the processor 300 in response to the corresponding dedicated module is the query mode. In other words, the bit is configured in the query mode at this time. When a certain bit of the control register 304 is configured as a logic 1 (that is, the bit is configured in the interrupt mode), the response mode of the processor 300 in response to the corresponding dedicated module is the interrupt mode. In other words, the bit is configured in interrupt mode at this time.

According to an embodiment of the present invention, the interrupt mode and the query mode can coexist in N dedicated modules. When configuring the control register 304, it is necessary to configure the bits corresponding to each dedicated module at the corresponding logical value. For the processor 300, the processor 300 will determine the response mode taken by the corresponding special module among the N special modules according to the logic value configured by each bit in the control register 304. When the bit of the control register is configured as logic 1, the response mode of the processor in response to the corresponding dedicated module is query mode, and when the bit of the control register is configured as logic 0, the response mode of the processor in response to the corresponding dedicated module is interrupt mode . If the response mode of the processor 300 in response to the special module SFU ₁ 308 and the special module SFU ₃ 312 is query mode, and the response mode of the processor 300 in response to the special module SFU ₂ 310 and the special module SFU _N 314 is interrupt mode, the special module SFU ₁ The bits corresponding to 308 and the dedicated module SFU ₃ 312 are configured as logic 1, and the bits corresponding to the dedicated module SFU ₂ 310 and the dedicated module SFU _N 314 are configured as logic 0. In another embodiment, when the bit of the control register is configured as logic 0, the response mode of the processor in response to the corresponding dedicated module is query mode, and when the bit of the control register is configured as logic 1, the processor responds to the corresponding dedicated module. The response mode of the module is interrupt mode. If the response mode of the processor 300 in response to the special module SFU ₁ 308 and the special module SFU ₃ 312 is query mode, and the response mode of the processor 300 in response to the special module SFU ₂ 310 and the special module SFU _N 314 is interrupt mode, the special module SFU ₁ The bits corresponding to 308 and the dedicated module SFU ₃ 312 are configured as logic 0, and the bits corresponding to the dedicated module SFU ₂ 310 and the dedicated module SFU _N 314 are configured as logic 1.

Please refer to Fig. 4, which is a schematic diagram of the control register configuration shown in Fig. 1. As shown in Figure 4, the dedicated module SFU ₁ 420, the dedicated module SFU ₂ 422 and the dedicated module SFU ₄ 426 correspond to the bits in the control register being bit 402, bit 404, and bit 408, respectively, and bit 402, bit 404, bit The logical value of 408 is 1. The dedicated module SFU ₃ 424 and the dedicated module SFU ₅ 428 correspond to the bits in the control register being bit 406 and bit 410, respectively, and the logical values of bit 406 and bit 410 are both 0. If the bit configuration of the control register is logic 1, it means the query mode and when the bit configuration of the control register is logic 0, it means the interrupt mode, the processor responds to the response of the dedicated module SFU ₁ 420, the dedicated module SFU ₂ 422 and the dedicated module SFU ₄ 426 The modes are all query modes, and the response modes of the processor's response to the dedicated module SFU ₃ 424 and the dedicated module SFU ₅ 428 are all interrupt modes. In other words, the processor interacts with the special module SFU ₁ 420, the special module SFU ₂ 422, and the special module SFU ₄ 426 in the query mode, and the processor interacts with the special module SFU ₃ 424 and the special module SFU ₅ 428 in the interrupt mode. Conversely, if the bit configuration of the control register is logic 0, it means the query mode and when the bit configuration of the control register is logic 1, it means the interrupt mode. The processor responds to the dedicated module SFU ₁ 420, the dedicated module SFU ₂ 422 and the dedicated module SFU ₄ 426. The response mode of the processor is interrupt mode, and the response mode of the processor response to the dedicated module SFU ₃ 424 and the dedicated module SFU ₅ 428 is the query mode. That is to say, the processor interacts with the special module SFU ₁ 420, the special module SFU ₂ 422, and the special module SFU ₄ 426 through the interrupt mode, and the processor interacts with the special module SFU ₃ 424 and the special module SFU ₅ 428 through the query mode. Therefore, configuring the response mode of the CPU to respond to the N dedicated modules through the control register is the prerequisite and basis for ensuring that the system has a flexible task response mode.

It should be noted that the control register may not only include bits indicating the response mode of the processor in response to the dedicated module, and the control register may also include some other bits to implement other functions of the processor in response to the dedicated module. For example, the control processor may include a plurality of bits, where these bits are used to store a response time corresponding to the processor's request for completion of at least one of the plurality of task completion requests. When the processor responds to a dedicated module in the interrupt mode, after the processor receives at least one task completion request from the dedicated module through the bus interface, the controller in the processor delays responding to at least one task completion request, where the delay time Is the response time.

In one embodiment, the response time is a preset time. In another embodiment, the response time can be adjusted in real time according to the task completion status and task priority of the processor. For example, if the task currently processed by the processor is the highest priority task, even if the processor responds to a dedicated module in an interrupt mode, the controller will not immediately respond to the task completion request for this dedicated module. Dedicated module. Instead, it delays the response to the task completion request. Among them, the delay time is set according to the completion time of the current processing task estimated by the system. In other words, the delay time can be adjusted in real time according to the completion time of the task. In this embodiment, the flexibility of the processor is higher. In this way, the processor can not only ensure that the task with the highest optimal level is processed in time, but also ensure the efficiency of the processor in responding to the dedicated module. In addition, in order to simplify the calculation, the response time can also be preset in advance. That is, the response time is the preset time. In one embodiment, the response time is preset according to the longest time required to complete a task. It should be noted that the above embodiments are only used to explain the present invention, but not to limit the present invention.

In another embodiment, if the task currently processed by the processor is a task that is about to be processed, even if the processor responds to a dedicated module in an interrupt mode, the controller in the processor will not receive information about this dedicated module. After the task of the module completes the request, it responds to the dedicated module immediately. The controller in the processor delays in responding to the task completion request. Among them, the delay time is the response time. The response time can be a preset response time. However, if the task currently processed by the processor is a task that has just started to be processed, if the response mode of the processor in response to a dedicated module is interrupt mode, the controller in the processor receives the task completion request for this dedicated module. Respond to the dedicated module immediately. At this time, the delay time and response time are both 0. In this implementation manner, the time point for responding to the dedicated module can be determined according to the completion of the task currently processed by the processor. In this way, the task currently processed by the processor and the task completion request of the dedicated module can be taken into consideration.

According to another embodiment of the present invention, the control register includes some other bits. Among them, these bits are used to store the response conditions corresponding to the processor's request for completion of multiple tasks. When the response mode of the processor in response to the special module is interrupt mode, if the response condition is met, the controller responds to the task completion request of the special module. The response condition is that the processor receives the task completion request of the dedicated module from the dedicated module through the bus interface and the processor has processed the currently executing task. When this implementation manner is adopted, it can be ensured that the completion of the task currently processed by the processor is not disturbed by the task completion request of the dedicated module. This implementation is suitable for situations where there is no correlation between any task currently processed by the processor and the task completed by the dedicated module.

In one embodiment, if the response mode of the processor in response to the dedicated module is the query mode, the controller sends at least one query instruction on the dedicated module to determine whether the dedicated module has issued a task completion request. According to an embodiment of the present invention, the at least one query command includes at least one of the command type, the code of the dedicated module number to be queried, the first address of the dedicated module, the number of dedicated modules, and the scalable flag; wherein the scalable flag is used for Indicates whether the size of at least one query command is scalable. In one embodiment, the scalable flag indicates whether the size of the query command can be correspondingly changed according to the number of dedicated modules corresponding to the query command.

In an embodiment, assuming that the number of dedicated modules is N, log2N bits need to be used to encode the number of dedicated modules. For example, if the number of dedicated modules N=32, then 5 bits need to be used to encode the number of dedicated modules. For a CPU with a 32-bit instruction code width, it can accommodate one or more dedicated module numbers. According to the embodiment of the present invention, three available query instruction coding schemes are provided. See Figure 5. Fig. 5 is a schematic diagram of the query instruction of the processor shown in Fig. 1. In the encoding method 500, the query instruction only includes a dedicated module number numi with query. In the encoding method 502, the query instruction can encode more dedicated module numbers (for example, the dedicated module numbers numi, numj, numk, nump, numq) at one time. Different from the encoding method 500, the encoding method 502 can make full use of the reserved space (reserved) in the instruction encoding. In this implementation example, assuming that the query instruction itself requires 7 bits to encode the instruction type (represented by "opcode" in FIG. 5), then there are 25 bits of encoding space remaining. Therefore, in this embodiment, one query command can encode the IDs of up to 5 dedicated modules. In the encoding method 504, the first address of the dedicated module to be queried (represented by "start_id" in FIG. 5) and the number of the dedicated module to be queried (represented by "length" in FIG. 5) are defined. Therefore, the maximum number of the dedicated module to be queried (for example, the address of the dedicated module) that can be supported in the encoding method 504 is start_id, start_id+1, start_id+2, ..., start_id+length. It should be noted that the encoding methods of the above three query instructions can be used in one embodiment at the same time, and according to the instruction type of the query instruction, the processor (for example, CPU) decodes it, and decides the specific query that needs to be queried. Module number. However, the present invention is not limited to this, and it is also possible to use only any one of the above-mentioned three query instruction encoding methods, or any combination of the above-mentioned three query instruction encoding methods, to increase the flexibility of using the query instruction.

See Figure 6a and Figure 6b. Fig. 6a is a flowchart of the processor shown in Fig. 1 responding to a dedicated module in a query mode according to an embodiment of the present invention. Fig. 6b is a flowchart of the processor shown in Fig. 1 responding to the dedicated module in the query mode according to an embodiment of the present invention. In the query mode, the processor dynamically schedules to determine when to insert query instructions based on algorithm requirements, the idle state of the CPU, and the degree of algorithm execution. For example, when the task being executed by the processor requires the processing result of the task executed by the first dedicated module, the controller issues the at least one query instruction. Or, when the processor is in an idle state, the controller issues the at least one query instruction.

After the processor allocates tasks to multiple dedicated modules, it can perform other tasks first. In FIG. 6a, as shown in step S602, the processor (for example, CPU) configures a dedicated module (for example, DMA or other dedicated module), and sends configuration signals or other instructions regarding the dedicated module to the dedicated module. At this time, as shown in step S620, the dedicated module receives the configuration signal from the processor and configures the configuration register in the dedicated module, and the dedicated module receives other instructions to perform operations related to these instructions. In one embodiment, the processor sends a configuration signal to a dedicated module (e.g., DMA) for configuring the configuration register in the dedicated module.

In step S604, the processor performs other tasks. At this time, as shown in step S622, the dedicated module starts to work after configuring the configuration register. For example, the dedicated module starts to perform operations or processing related to configuration signals or other instructions. As shown in step S624, after completing the operation or processing related to the configuration signal or other instructions sent by the processor, the dedicated module sends a task completion request to the processor.

In step S606, the processor continues to execute other tasks until the processor completes the task being executed and enters an idle state.

As shown in step S608, after entering the idle state, the processor executes the query instruction. In one embodiment, when the processor detects a completion request issued by the dedicated processing module, the processor processes the task completed by the dedicated module.

As shown in step S610, after processing the tasks completed by the dedicated module, the processor executes a new task. In another embodiment, after processing the tasks completed by the dedicated module, the processor enters an execution idle state.

In FIG. 6b, as shown in step S632, the processor (for example, CPU) configures a dedicated module (for example, DMA), and sends configuration signals or other instructions related to the dedicated module to the dedicated module. At this time, as shown in step S650, the dedicated module receives the configuration signal from the processor and configures the configuration register in the dedicated module, and the dedicated module receives other instructions to perform operations related to these instructions. In one embodiment, the processor sends a configuration signal to the dedicated module (for example, DMA) for configuring the configuration register in the dedicated module.

In step S634, the processor performs other tasks. At this time, as shown in step S652, the dedicated module starts to work after configuring the configuration register. For example, the dedicated module starts to perform operations or processing related to configuration signals or other instructions.

As shown in step S636, if the processor finds that the task being executed requires the calculation result of the dedicated module, the processor executes the query instruction, suspends the execution of the task currently being executed, and waits for the task completion request of the dedicated module. As shown in step S654, after completing the operation or processing related to the configuration signal or other instructions sent by the processor, the dedicated module sends a task completion request to the processor.

In step S638, after receiving the task completion request issued by the dedicated module, the processor continues to execute other tasks in step S634 (that is, the task that was suspended in step S636). In one embodiment, the processor enters an idle state after executing the above-mentioned tasks.

As shown in step S640, the processor executes a new task.

It should be noted that, in the above embodiment, the dedicated module is one of a graphics processing module, a vector calculation module, a floating point processing module, a direct memory access module, an artificial intelligence accelerator, and a fast Fourier transform module. In addition, other dedicated modules that interact with the processor can also be used. In Figure 6a, when the query instruction is used, the dedicated module has completed the task, so the processor (for example, the CPU) will not enter the suspended state. However, in Figure 6b, according to the algorithm, the processor needs to use the calculation results of the dedicated module in other current tasks. Therefore, the processor executes the query instruction and waits for the task completion request of the dedicated module. Different from the interrupt mode, when the query mode is used, the processor executes the query instruction only when the processor enters the idle state after completing other tasks, or the processor urgently needs the calculation result of the dedicated module. Therefore, the use of query mode can fully improve the execution efficiency of the system.

In one embodiment, when the processor and the dedicated module cooperate to complete the same task, if the response mode of the processor in response to the dedicated module is the query mode, the time point at which the processor needs to use the processing result of the first dedicated module is estimated, And according to the time point, the time point at which the controller sends at least one query instruction on the first dedicated module is determined, so as to reduce the waiting time of the processor. Moreover, this method can improve the computational efficiency of the processor.

The processor may further include a process status register for marking the process status of the process processed by the processor. Further, according to the marked process status of the process status register, the controller dynamically adjusts the response mode of the processor in response to multiple dedicated modules, and sends the adjusted response mode to the control register. In this embodiment, the processor can adjust the response mode of the processor and multiple dedicated modules in real time.

In one embodiment, if the task currently processed by the processor is the task with the highest priority, or the task currently processed by the processor is higher than the priority of multiple dedicated modules, the value of the flag status register is set to "1". When the value of the flag status register is set to "1", the processor does not respond to the response mode of any dedicated module. Further, the above scheme can also be realized by using a logical value "0". For example, if the task currently processed by the processor is the task with the highest priority, or the task currently processed by the processor is higher than the priority of multiple dedicated modules, the value of the flag status register is set to "0". The processor does not respond to the response mode of any dedicated module.

In another embodiment, if the task currently processed by the processor is the task with the lowest priority, or the task currently processed by the processor is lower than the priority of multiple dedicated modules, the value of the flag status register is set to "1" . As long as the processor receives a complete task request from the dedicated module, the processor immediately responds to the response mode of the dedicated module. Further, the above scheme can also be realized by using a logical value "0". If the task currently processed by the processor is the task with the lowest priority, or the task currently processed by the processor is lower than the priority of multiple dedicated modules, the value of the flag status register is set to "0". As long as the processor receives a complete task request from the dedicated module, the processor immediately responds to the response mode of the dedicated module.

See Figure 7a and Figure 7b. Fig. 7a is a schematic diagram of the processor shown in Fig. 1 using a pseudo code of a query instruction according to an embodiment of the present invention. Fig. 7b is a schematic diagram of the processor shown in Fig. 1 using a pseudo code of a query instruction according to another embodiment of the present invention. When using query commands, you can use multiple query commands non-continuously or consecutively. As shown in FIG. 7a, the pseudo code 700 is a non-continuous execution or a single execution query instruction. Specifically, in the code lines 702 to 706, the dedicated module i to the dedicated module k are configured first. In code line 708, the processor performs other tasks. In code line 710, the processor executes query instruction 1. After executing the code line 710, the processor executes some other codes (not shown). In code line 712, the processor executes query instruction 2. After executing the code line 712, the processor executes some other codes (shown in the figure). In code line 714, the processor executes other instructions.

As shown in FIG. 7b, the pseudo code 720 is to execute multiple query instructions continuously. Specifically, in the code lines 722-726, the dedicated module i to the dedicated module k are configured first. In code line 728, the processor performs other tasks. In code line 730, the processor executes query instruction 1. After executing the code line 730, the processor executes the code line 732. In code line 732, the processor executes query instruction 2. After executing the code line 732, the processor executes some other codes (shown in the figure). In code line 734, the processor executes other instructions. It can be seen from the above that query instruction 1 and query instruction 2 are two query instructions that are executed continuously. In one embodiment, since the processor continuously uses multiple query instructions, the processor can execute other subsequent instructions only after all dedicated modules specified by the query instructions report the task completion request.

According to an embodiment of the present invention, the same query command can be used for multiple dedicated modules. In this query instruction, it is not necessary to indicate the ID of the dedicated module (for example, the dedicated module code), address information, or other attribute information. At this point, you can query whether any one of the multiple dedicated modules has sent a task completion request. If any dedicated module has sent a task completion request, the processor responds to the task completion request. In this way, the types of instructions can be reduced, and instruction resources and space for storing query instructions can be saved. In addition, the same query command can also be used for multiple dedicated modules of the same type. At this time, it is necessary to add identification information about the same type of dedicated module in the query command. For example, the codes of these dedicated modules, or attribute flags. When multiple dedicated modules of the same type process certain specific tasks in parallel, only one instruction can be sent to improve the utilization rate of the instruction. In another embodiment, multiple query commands may also be used to apply different query commands to different types of dedicated modules. However, the present invention is not limited to this. In another embodiment, it is also possible to combine the above-mentioned ways of using several query instructions to improve the flexibility of using the query instructions.

When the processor executes the query instruction, it records the number of the dedicated module to be queried in the pipeline processing, and uses an independent register in the processor to record whether the dedicated module to be queried has issued a task completion request. For a processor (for example, CPU) with a three-stage pipeline structure, the processor can be divided into three-stage pipelines of fetching, decoding, and execution. After the query instruction is streamed to the execution level, the number of the dedicated module to be queried will be recorded on the execution level. Different encoding methods of query instructions require different methods of recording dedicated modules.

According to an embodiment of the present invention, the processor further includes one or more detection units. In other words, the number of detection units can be determined according to different hardware design schemes. According to an embodiment of the present invention, the processor includes a detection module. The detection module includes at least one detection unit. Among them, the detection unit includes a comparator and a data register. The data register is used to store the first dedicated module number corresponding to the first dedicated module among the plurality of dedicated modules; and when the detecting unit receives the second task completion request, the detecting unit determines the second dedicated module number of the second task request, The second dedicated module number is compared with the first dedicated module number in the data register through a comparator to determine the dedicated module corresponding to the second task completion request. The detection unit further includes a result register. The detection unit stores multiple comparison results in the result register. When the controller sends the query command, the controller responds to the second task request according to the value in the result register.

The detection module further includes an AND gate for receiving a plurality of first comparison results from a plurality of first detection units, and the AND gate performs an AND operation on a plurality of the first comparison results to determine a plurality of Whether the dedicated modules all issue corresponding task completion requests respectively.

See Figure 8. Fig. 8 is a schematic diagram of a detection unit in the processor shown in Fig. 1. As shown in FIG. 8, the processor further detects the unit 800. The detection unit 800 includes a comparator 802 (for example, a comparison circuit), a data register 804 and a result register 806. After the dedicated module issues the task completion request, the comparator in the detection unit 800 detects whether the dedicated module number corresponding to the task completion request is consistent with the dedicated module number num stored in the data register 804 corresponding to the detection unit 800. If the dedicated module number stored in the data register 804 of the detection unit 800 is consistent with the dedicated module number corresponding to the task completion request, the detection result is valid, and the detection result is recorded in the result register 806. If the dedicated module number stored in the data register 806 of the detection unit 800 and the dedicated module number corresponding to the task completion request are both inconsistent, the detection result is invalid.

According to another embodiment of the present invention, the processor further includes a flag register, which is used to store information about whether the first dedicated module of the plurality of dedicated modules is sent by the processor when the response mode of the first dedicated module is a query mode. The record of the first task completion request. For example, the processor includes a flag register A. Among them, the mark register A corresponds to the dedicated module SFU ₀ . If it detects that the dedicated module SFU ₀ sends a task completion request, the value of the flag register A is set to "1". Otherwise, the value of the flag register A is "0". Or, if the task completion request from the dedicated module SFU _{0 is} detected, the value of the flag register A is set to "0". Otherwise, the value of the flag register A is "1". The flag register A may be the result register 806. However, the flag register may also be another register capable of storing records about whether the dedicated module issues a task completion request.

According to an embodiment of the present invention, if the multiple response modes of the processor in response to the multiple dedicated modules are the query mode, the controller sends query instructions on the multiple dedicated modules to determine whether the multiple dedicated processing modules issue multiple tasks. Complete the request. If all task completion requests have been issued, the processor executes tasks related to multiple dedicated processing modules.

See Figure 9. Fig. 9 is a schematic diagram of a detection module in the processor shown in Fig. 1. The processor further includes a detection module 900 for detecting whether multiple dedicated processing modules (for example, dedicated processing modules SFU ₀ , SFU ₁ ,..., SFU _N ) all issue task completion requests. The detection module 900 includes a detection unit 906 to a detection unit 914. The detection unit 906 to the detection unit 914 respectively include a comparator (for example, a comparison circuit), a data register, and a result register. Among them, the data register is used to store the code of the special module to be queried. The result register is used to store the comparison result of the comparator. For example, the detection unit 906 includes a comparator 904, a data register 916, and a result register 920. Among them, the data register 816 is used to store the dedicated module code numi. It should be noted that the detection unit 908 to the detection unit 914 have a structure similar to that of the detection unit 906. For the sake of brevity, I won't repeat it.

After any one of the special module SFU ₀ , the special module SFU ₁ , the special module SFU ₂ ,..., and the special module SFU _N issues a task completion request, each comparator in the detection unit 906 to the detection unit 914 Respectively detect whether the dedicated module number corresponding to the task completion request is consistent with the dedicated module number stored in the data register corresponding to the detection unit. If there is at least one special module number stored in the data register in the detection unit 906 to the detection unit 914 that is consistent with the special module number corresponding to the task completion request, the detection result is valid, and the detection result is recorded in the result register. If the dedicated module numbers stored in all data registers in the detection unit 906 to the detection unit 914 are inconsistent with the dedicated module numbers corresponding to the task completion request, the detection result is invalid. When the result registers of all detection units are valid, it indicates that all the dedicated modules to be queried in the detection modules have completed calculations. At this time, the output result of the AND gate 902 is valid. In other words, the processor outputs the query instruction completion signal, the query instruction leaves the execution level, and the processor can continue to execute subsequent instructions.

See Figure 10. Fig. 10 is a flowchart of a task response method according to an embodiment of the present invention. The task response method can be applied to the interaction between processing and dedicated modules. Among them, the dedicated module can be a graphics processing module (Graphic Process Unit, GPU), a vector computing module (Vector Process Unit), a floating point processing module (Floatpoint Process Unit, FPU), and a direct memory access module (Direct Memory Access, DMA). ) Or similar dedicated processing units that can handle a special computing task, such as artificial intelligence (AI) accelerators, fast Fourier transform (Fast Fourier Transform, FFT), and so on. Structurally, these dedicated modules are connected to the processor through an internal bus and are interconnected through the internal bus. These dedicated modules receive instructions or configuration signals from the CPU, and can also send completion requests to the CPU after completing specific tasks.

As shown in FIG. 10, the task response method includes step S1002 to step S1006.

In step S1002, receiving multiple task completion requests corresponding to multiple dedicated modules external to the processor coupled to the bus interface;

In step S1004, obtain multiple response modes of the processor in response to multiple dedicated modules, and store the multiple response modes in the control register; wherein, the multiple response modes are different; and

In step S1006, respond to multiple task completion requests of multiple dedicated modules according to the corresponding response mode in the control register.

In an embodiment, the multiple response modes include an interrupt mode and a query mode; and the task response method includes: when the response mode of the processor responding to the first dedicated module of the plurality of dedicated modules is the query mode, storing information about the first dedicated module Whether the module issues a record of the first task completion request.

In one embodiment, multiple bits are used to store the response time of the processor corresponding to at least one task completion request of the multiple task completion requests; the response time is a preset time; and when the processor responds to the first dedicated module When the one response mode is the interrupt mode, after receiving at least one task completion request from the first dedicated module through the bus interface, the response to the at least one task completion request is delayed, and the delay time is the response time.

In an embodiment, a plurality of bits are used to store a response condition corresponding to the processor's request for completion of a plurality of tasks; the response condition is that the processor receives the first dedicated module from the first dedicated module of the plurality of dedicated modules through the bus interface When the processor responds to the first dedicated module in the interrupt mode, and if the response condition is met, the processor responds to the task completion request of the first dedicated module.

In an embodiment, the first bit is used to store the first response mode corresponding to the processor responding to the first dedicated module among the plurality of dedicated modules; and wherein, when the first bit is 0, the first response mode is an interrupt mode ; When the first bit is 1, the second response mode is the query mode; or when the first bit is 1, the first response mode is the interrupt mode; when the first bit is 0, the second response mode is the query mode.

In an embodiment, if the response mode of the processor in response to the first dedicated module is the query mode, at least one query instruction regarding the first dedicated module is sent to determine whether the first dedicated module has issued at least one first task completion request .

In an embodiment, when the task being executed by the processor requires the processing result of the task executed by the first dedicated module, the processor (for example, the controller in the processor) issues at least one query instruction; or when the processor is idle In the state, the processor (for example, the controller in the processor) issues at least one query command.

In one embodiment, the at least one query instruction includes at least one of the instruction type, the code of the dedicated module number, the first address of the dedicated module, the number of dedicated modules, and the scalable flag; wherein the scalable flag is used to indicate at least one query Whether the size of the instruction is scalable.

In one embodiment, the first dedicated module number corresponding to the multiple dedicated modules is stored through the data register; and when the second task completion request is received by the detection unit, the second dedicated module requested by the second task is determined by the detection unit And compare the second dedicated module number with the first dedicated module number in the data register through a comparator to determine the dedicated module corresponding to the second task completion request.

In an embodiment, a plurality of comparison results are stored in a result register; and when the processor (for example, the controller in the processor) sends a query command, respond to the second task according to the values in the plurality of result registers request.

In an embodiment, a plurality of comparison results are received, and the plurality of comparison results are ANDed to determine whether a plurality of dedicated modules respectively issue corresponding task completion requests.

In an embodiment, if the multiple response modes of the processor in response to multiple dedicated modules are query modes, it sends query instructions for multiple dedicated modules to determine whether multiple dedicated processing modules issue multiple task completion requests; if All task completion requests have been issued, and tasks related to multiple dedicated processing modules are executed.

In an embodiment, when the processor and the first dedicated module of the plurality of dedicated modules cooperate to complete the same task, if the response mode of the processor in response to the first dedicated module is the query mode, it is estimated that the processor needs to use the first dedicated module. The time point of the processing result of a dedicated module, and according to the time point, determine the time point at which the processor (for example, the controller in the processor) sends at least one query instruction about the first dedicated module, so as to reduce the waiting time of the processor .

In one embodiment, the process status of the process processed by the processor is marked; and the response mode of the processor in response to multiple dedicated modules is dynamically adjusted according to the marked process status of the process status register, and the adjusted response mode is stored.

The embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores a computer program, the computer program includes program instructions, and the processor executes the program instructions to execute the following action:

Receiving multiple task completion requests corresponding to multiple dedicated modules external to the processor coupled to the bus interface;

Obtain multiple response modes of the processor in response to multiple dedicated modules, and store the multiple response modes in the control register; wherein, the multiple response modes are different; and

According to the corresponding response mode in the control register, respond to multiple task completion requests.

In the embodiment of the present application, the memory is used to store a computer program, and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to realize the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage devices or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEAROM), erasable and programmable Read only memory (EAROM), programmable read only memory (AROM), read only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

In the embodiment of the present application, the processor may be any hardware processing device that can execute the foregoing method logic. Optionally, the processor may be a central processing unit (Central Arocessing Unit, CAU), a graphics processor (GraAhics Arocessing Unit, GAU), or a micro control unit (Microcontroller Unit, MCU); it may also be a Field Programmable Gate Array (Field Programmable Gate Array). -Arogrammable Gate Array (FAGA), Programmable Array Logic Device (Arogrammable Array Logic, AAL), General Array Logic Device (General Array Logic, GAL), Complex Programmable Logic Device (ComAlex Arogrammable Logic Device, CALD) and other programmable devices ; Or it may be an Advanced Reduced Instruction Set (RISC) processor (Advanced RISC Machines, ARM) or a system chip (System on ChiA SOC), but not limited to this.

It should be noted that the descriptions of "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent a sequence, nor do they limit the "first" and "second" Are different types.

Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may adopt the form of a computer program product implemented on one or a computer-usable storage medium (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

The present invention is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are used to generate It is a device that realizes the functions specified in a flow or a flow in the flowchart and/or a block or a block in the block diagram.

These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device. The device implements the functions specified in a flow chart or a flow and/or a block or a block in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment. The instructions provide steps for implementing functions specified in a flow or a flow in the flowchart and/or a block or a block in the block diagram.

In a typical configuration, the computing device includes an OR processor (CAU), input/output interface, network interface, and memory.

The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.

Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (ARAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEAROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or also include elements inherent to such processes, methods, commodities, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other same elements in the process, method, commodity, or equipment that includes the element.

The above descriptions are only examples of the present application, and are not used to limit the present application. For those skilled in the art, this application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the scope of the claims of this application.

Claims (33)

1. A processor, characterized in that it comprises:

   A bus interface, capable of being coupled to a plurality of dedicated modules outside the processor, and configured to receive a plurality of task completion requests for the plurality of dedicated modules; and

   The control register is used to store a plurality of response modes of the processor in response to a plurality of the dedicated modules; wherein, a plurality of the response modes are different;

   Wherein, the processor responds to the multiple task completion requests of the multiple dedicated modules according to the corresponding response manner in the control register.
2. The processor of claim 1, wherein:

   The multiple response modes include interrupt mode and query mode; and

   The processor further includes a flag register for storing information about whether the first dedicated module issues the first task when the response mode of the processor in response to the first dedicated module of the plurality of dedicated modules is a query mode Complete the requested record.
3. The processor of claim 1, wherein:

   The control register includes a plurality of bits; wherein, the plurality of bits are used to store a response time corresponding to the processor for at least one task completion request among the plurality of task completion requests; and

   When the first response mode of the processor in response to the first dedicated module is an interrupt mode, after the processor receives the at least one task completion request from the first dedicated module through the bus interface, the processing The device delays responding to the at least one task completion request, where the delay time is the response time.
4. The processor of claim 1, wherein:

   The control register includes a plurality of bits; wherein, the plurality of bits are used to store response conditions corresponding to the processor with respect to the plurality of task completion requests; and

   When the first response mode of the processor in response to the first dedicated module is an interrupt mode, if the response condition is met, the processor responds to the task completion request of the first dedicated module;

   The response condition is that the processor receives the task completion request of the first dedicated module from the first dedicated module of the plurality of dedicated modules through the bus interface, and the processor has processed the currently executing task. task.
5. The processor of claim 1, wherein:

   The control register includes a first bit, and the first bit is used to store a first response manner corresponding to the processor responding to the first dedicated module among the plurality of dedicated modules; and

   Wherein, when the first bit is 0, the first response mode is an interrupt mode; when the first bit is 1, the first response mode is a query mode; or

   When the first bit is 1, the first response mode is an interrupt mode; when the first bit is 0, the first response mode is a query mode.
6. The processor of claim 1, wherein:

   If the response mode of the processor in response to the first dedicated module is a query mode, the processor sends at least one query instruction on the first dedicated module to determine whether the first dedicated module has issued the first task Complete the request.
7. The processor of claim 6, wherein:

   When the task being executed by the processor requires the processing result of the task executed by the first dedicated module, the processor issues the at least one query instruction; or

   When the processor is in an idle state, the processor issues the at least one query instruction.
8. The processor of claim 6, wherein:

   The at least one query instruction includes at least one of the instruction type, the code of the dedicated module number, the first address of the dedicated module, the number of dedicated modules, and a scalable flag; wherein, the scalable flag is used to indicate the at least one query Whether the size of the instruction is scalable.
9. The processor according to claim 1, further comprising:

   The detection module includes a detection unit, wherein the detection unit includes a comparator and a data register, and the data register is used to store a first dedicated module number corresponding to a first dedicated module among the plurality of dedicated modules; and

   When the detection unit receives the second task completion request, the detection unit determines the second dedicated module number of the second task request, and compares the second dedicated module number with the data through the comparator. The number of the first dedicated module in the register is compared to determine the dedicated module corresponding to the second task completion request.
10. The processor according to claim 9, wherein:

    The detection unit further includes a result register; and

    The detection unit stores the comparison result in the result register, and

    When the processor sends the query instruction, the processor responds to the second task request according to the value in the result register.
11. The processor according to claim 9, wherein:

    The detection module further includes an AND gate for receiving a plurality of first comparison results from a plurality of first detection units, and the AND gate performs an AND operation on a plurality of the first comparison results to determine Whether a plurality of the dedicated modules respectively issue corresponding task completion requests.
12. The processor of claim 1, wherein:

    If the multiple of the response modes of the processor in response to the multiple of the dedicated modules are query modes, the processor sends a query instruction on the multiple of the dedicated modules to determine whether the multiple of the dedicated processing modules are Issue multiple task completion requests;

    If all task completion requests have been issued, the processor executes tasks related to a plurality of the dedicated processing modules.
13. The processor of claim 1, wherein:

    When the processor and the first dedicated module of the plurality of dedicated modules cooperate to complete the same task, if the response mode of the processor in response to the first dedicated module is a query mode, the processing is estimated The processor needs to use the time point of the processing result of the first dedicated module, and according to the time point, determine the time point at which the processor sends at least one query instruction about the first dedicated module, so as to reduce the processing time. The waiting time of the device.
14. The processor according to claim 1, further comprising:

    Process status register, used to mark the process status of the process processed by the processor; and

    According to the process status marked by the process status register, the processor dynamically adjusts the response mode of the processor in response to the plurality of dedicated modules, and sends the adjusted response mode to the control register.
15. The processor of claim 1, wherein:

    The multiple dedicated modules are one of a graphics processing module, a vector calculation module, a floating point processing module, a direct memory access module, an artificial intelligence accelerator, and a fast Fourier transform module.
16. A task response method is characterized in that it includes:

    Receiving multiple task completion requests corresponding to multiple dedicated modules external to the processor coupled to the bus interface;

    Acquire multiple response modes of the processor in response to the multiple dedicated modules, and store the multiple response modes in a control register; wherein, a plurality of the response modes are different; and

    According to the corresponding response manner in the control register, respond to the multiple task completion requests of the multiple dedicated modules.
17. The task response method of claim 16, wherein:

    The multiple response modes include interrupt mode and query mode; and

    The task response method includes:

    When the response mode of the processor in response to the first dedicated module among the plurality of dedicated modules is a query mode, a record about whether the first dedicated module issues a first task completion request is stored.
18. The task response method of claim 16, wherein:

    Using a plurality of bits to store a response time corresponding to the processor with respect to at least one task completion request among the plurality of task completion requests; the response time is a preset time; and

    When the first response mode of the processor in response to the first dedicated module is the interrupt mode, after receiving the at least one task completion request from the first dedicated module through the bus interface, it delays responding to the at least one task Complete the request, where the delay time is the response time.
19. The task response method of claim 16, wherein:

    A plurality of bits are used to store a response condition corresponding to the processor with respect to the plurality of task completion requests; the response condition is that the processor obtains the first dedicated module from the plurality of dedicated modules through the bus interface Receiving the task completion request of the first dedicated module and the processor has processed the currently executing task; and

    When the first response mode of the processor in response to the first dedicated module is an interrupt mode, if the response condition is satisfied, the processor responds to the task completion request of the first dedicated module.
20. The task response method of claim 16, wherein:

    Using the first bit to store the first response mode corresponding to the processor in response to the first dedicated module among the plurality of dedicated modules; and

    Wherein, when the first bit is 0, the first response mode is an interrupt mode; when the first bit is 1, the second response mode is a query mode; or

    When the first bit is 1, the first response mode is an interrupt mode; when the first bit is 0, the second response mode is a query mode.
21. The task response method of claim 16, wherein:

    If the response mode of the processor in response to the first dedicated module is the query mode, at least one query instruction on the first dedicated module is sent to determine whether the first dedicated module has issued at least one first task completion request .
22. The task response method of claim 21, wherein:

    When the task being executed by the processor requires the processing result of the task executed by the first dedicated module, the processor issues the at least one query instruction; or

    When the processor is in an idle state, the processor issues the at least one query instruction.
23. The task response method of claim 21, wherein:

    The at least one query instruction includes at least one of the instruction type, the code of the dedicated module number, the first address of the dedicated module, the number of dedicated modules, and a scalable flag; wherein, the scalable flag is used to indicate the at least one query Whether the size of the instruction is scalable.
24. The task response method of claim 16, wherein:

    Store the first dedicated module numbers corresponding to the plurality of dedicated modules through a data register; and

    When the detection unit receives the second task completion request, the detection unit determines the second dedicated module number of the second task request, and compares the second dedicated module number with the number in the data register through a comparator. The first dedicated module numbers are compared to determine the dedicated module corresponding to the second task completion request.
25. The task response method of claim 24, wherein:

    Store multiple comparison results in the result register; and

    When the processor sends the query instruction, it responds to the second task request according to the values in the multiple result registers.
26. The task response method of claim 25, wherein:

    Receive a plurality of the comparison results, and perform an AND operation on the plurality of the comparison results to determine whether a plurality of the dedicated modules respectively issue corresponding task completion requests.
27. The task response method of claim 16, wherein:

    If the plurality of the response modes of the processor in response to the plurality of the dedicated modules are query modes, then send a query instruction on the plurality of the dedicated modules to determine whether the plurality of the dedicated processing modules issue multiple tasks Complete the request;

    If all task completion requests have been issued, then tasks related to a plurality of the dedicated processing modules are executed.
28. The task response method of claim 16, wherein:

    When the processor and the first dedicated module of the plurality of dedicated modules cooperate to complete the same task, if the response mode of the processor in response to the first dedicated module is a query mode, the processing is estimated The processor needs to use the time point of the processing result of the first dedicated module, and according to the time point, determine the time point at which the processor sends at least one query instruction about the first dedicated module, so as to reduce the processing time. The waiting time of the device.
29. The task response method of claim 16, wherein:

    Mark the process status of the process processed by the processor; and

    According to the process status marked by the process status register, the response mode of the processor in response to the plurality of dedicated modules is dynamically adjusted, and the adjusted response mode is stored.
30. The task response method of claim 16, wherein:

    The multiple dedicated modules are one of a graphics processing module, a vector calculation module, a floating point processing module, a direct memory access module, an artificial intelligence accelerator, and a fast Fourier transform module.
31. A computer-readable storage medium storing computer instructions, wherein when the computer instructions are executed by one or more processors, the one or more processors perform actions including the following:

    Receiving multiple task completion requests corresponding to multiple dedicated modules external to the processor coupled to the bus interface;

    Acquire multiple response modes of the processor in response to the multiple dedicated modules, and store the multiple response modes in a control register; wherein, a plurality of the response modes are different; and

    Responding to a plurality of the task completion requests according to the corresponding response manner in the control register.
32. A movable platform, wherein the movable platform comprises the processor according to claims 1-15.
33. A camera, characterized in that the camera comprises the processor according to claims 1-15.

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