CN110865951A

CN110865951A - Method and device for supporting single-root dual-processor interrupt communication

Info

Publication number: CN110865951A
Application number: CN201911070375.4A
Authority: CN
Inventors: 张剑锋; 龚锐; 张英; 石伟; 任巨; 刘威; 周理; 铁俊波; 王蕾; 周宏伟; 王永文
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2019-11-05
Filing date: 2019-11-05
Publication date: 2020-03-06
Anticipated expiration: 2039-11-05
Also published as: CN110865951B

Abstract

The invention relates to the field of micro-architecture design of a microprocessor, in particular to a method and a device for supporting single-root dual-processor interrupt communication. The invention has the advantages of high performance, low cost, easy realization and flexible use, and can be flexibly applied to the design of the existing processor.

Description

Method and device for supporting single-root dual-processor interrupt communication

Technical Field

The invention relates to the field of micro-architecture design of microprocessors, in particular to a method and a device for supporting single-root dual-processor interrupt communication.

Background

The traditional method for improving the performance of the processor by increasing the frequency of the processor has less and less profit in the technological development to the present generation, which is largely because the space for increasing the frequency of the processor is also very limited, so in recent years researchers have focused more on how to increase the number of the computing cores in the processor to pursue higher performance. From single cores, previously, through dual cores, quad cores, 16 cores to the maximum 64 cores that are now well documented, the number of processor cores has grown to scale, however increasing the number of processor cores also brings new technical challenges, such as: how to maintain data consistency among different computing cores, how to ensure efficient data transmission and size and cost of a single die by a network, therefore, it is currently accepted that the number of cores of a single processor does not exceed 64, which is also a scale capable of ensuring maximum performance benefit, however, for a contradiction of an application scenario represented by high-performance computing to a demand of a server computing capacity, if processor interconnection expansion can be realized, an effective means for effectively solving the contradiction is provided.

It should be noted that, in the current high-performance processor, the interrupt system plays a very important role, and is an efficient means for ensuring the performance of the processor, that is, the processor will enter the interrupt service program to perform the relevant operation only after the interrupt is triggered, and jump back to process the interrupted task after the interrupt service program is executed. Meanwhile, the interrupts are divided into different types according to different interrupt sources, different interrupt initiating modes and different processing modes, and the method specifically includes the following steps: the core initiates a core private interrupt with its own response processing; the software initiates different cores to carry out inter-machine interruption of work cooperation; shared device interrupt initiated by the IO device and the storage device; IO device initiated message interrupts, commonly referred to as PCIe devices.

Therefore, it is a difficult problem for researchers to ensure efficient interrupt response and processing for improving processor performance by using a processor interconnection manner, because each processor has its own interrupt control unit when the processors are interconnected, but currently, each manufacturer standard system kernel is of a single structure, that is, only one interrupt control unit is supported for initialization, so that how to enable a certain interrupt control unit to work and other interrupt control units to not work when the processors are interconnected, how to enable a certain interrupt control unit to control interrupts of all interconnected processors, how to enable interrupt requests in processors in which other interrupt control units that do not work to be transmitted to processors in which the interrupt control units that are in a working state are located, and the like.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: the invention has the advantages of high performance, low cost, easy realization and flexible use, and is simple to realize and can be flexibly applied to the design of the existing processor.

In order to solve the technical problems, the invention adopts the technical scheme that:

a method for supporting single-root dual-processor interrupt communication is implemented and comprises the following steps:

1) the method comprises the steps that an interrupt control unit of a root processor receives an interrupt request from the root processor or a non-root processor through a network on chip, the interrupt request from the non-root processor is transmitted to the network on chip of the root processor through an inter-processor high-speed interconnection interface, the interrupt request is redirected and mapped to a certain computing cluster control unit in the interrupt control unit, the root processor and the non-root processor respectively occupy half of the cluster control units, and the number of core control units in each cluster control unit is twice as large as that of cores in computing clusters of the root processor and the non-root processor;

2) unpacking the interrupt request to obtain a logic ID and sending the logic ID to a computing cluster control unit corresponding to the logic ID;

3) acquiring the relevant configuration of the interrupt request through a computing cluster control unit corresponding to the logic ID;

4) generating an interrupt interactive command for the interrupt request according to the relevant configuration by the computing cluster control unit corresponding to the logic ID;

5) remapping the logical IDs to physical IDs of the cores and target compute clusters of the corresponding root processor or non-root processors;

6) packaging the interrupt interaction command to generate an interrupt interaction command message, wherein the destination of the interrupt interaction command message is the physical ID of a target computing cluster and a core which are remapped to a corresponding root processor or a non-root processor;

7) arbitrating the interrupt interaction command message;

8) and after the arbitration is successful, the interrupt interaction command message is output in a routing way, and is directly transmitted to a target computing cluster and a core of the root processor through the network on chip when the interrupt request comes from the root processor, and is transmitted to the target computing cluster and the core of the non-root processor through the network on chip and the high-speed interconnection interface between the processors when the interrupt request comes from the non-root processor.

Optionally, the detailed steps of step 5) include:

5.1) judging the source of the interrupt request, and if the source of the interrupt request is the root processor, skipping to execute the step 5.2); if the source of the interrupt request is a non-root processor, skipping to execute step 5.3);

5.2) remapping the logical IDs to the physical IDs of the corresponding root processor's target compute cluster and core based on the following rules: redirecting a calculation cluster control unit with logic IDs of 0 to i/2-1 to the 0 to i calculation clusters of the root processor, redirecting the calculation cluster control unit with the logic ID of 0 to the 0 to 1 calculation clusters of the root processor, redirecting a calculation cluster control unit with the logic ID of 1 to the 2 to 3 calculation clusters of the root processor, repeating the steps, redirecting the calculation cluster control unit with the logic ID of i/2-1 to the i-2 to i-1 calculation clusters of the root processor, redirecting the core control units with the numbers of 0 to n and n +1 to 2n +1 in the same calculation cluster control unit to the cores of 0 to n in two adjacent calculation clusters of the root processor respectively, wherein the number of the cores in the calculation clusters of the root processor and the non-root processor is n, and the total number of the calculation clusters of the root processor and the non-root processor and the calculation cluster control units is i, the root processor corresponds to the computing cluster control units from No. 0 to No. i/2-1, and the non-root processor corresponds to the computing cluster control units from No. i/2 to No. i-1; final jump execution step 6);

5.3) remapping the logical IDs to the physical IDs of the corresponding target compute clusters and cores of the non-root processor based on the following rules: redirecting the computing cluster control unit with the logic ID from i/2 to i-1 to the computing clusters from 0 to i of the non-root processor, so that the computing cluster control unit with the logic ID from i/2 is redirected to the computing clusters from 0 to 1 of the non-root processor, the computing cluster control unit with the logic ID from i/2+1 is redirected to the computing clusters from 2 to 3 of the non-root processor, and so on, the computing cluster control unit with the logic ID from i-1 is redirected to the computing clusters from i-2 to i-1 of the non-root processor, and the core control units from 0 to n and from n +1 to 2n +1 in the same computing cluster control unit are respectively redirected to cores from 0 to n in two adjacent computing clusters of the non-root processor; jump execution step 6).

Optionally, step 1) is preceded by a step of initiating an interrupt request by the root processor, and the step is one of the following three ways:

mode (1.1): a core in a certain computing cluster of a root processor initiates an interrupt request, the interrupt request is private interrupt or inter-machine interrupt, the root processor remaps the physical IDs of the computing cluster and the core which initiate the interrupt request to the logic ID of a corresponding computing cluster control unit in the root processor, the logic ID is packaged to form an interrupt message, the routing destination of the interrupt message is the computing cluster control unit corresponding to the logic ID in the root processor, and the interrupt message is routed to the interrupt control unit of the root processor through a network on chip;

mode (1.2): an IO device of a root processor initiates an interrupt request aiming at a target computing cluster and a core, the interrupt request is shared device interrupt or device message interrupt, the root processor packages the initiated interrupt request to form an interrupt message, the interrupt message comprises physical IDs of the target computing cluster and the core, the routing destination of the interrupt message is a computing cluster control unit corresponding to the physical IDs of the target computing cluster and the core in the root processor, and the interrupt message is routed to the interrupt control unit of the root processor through a network on chip;

mode (1.3): the storage device of the root processor initiates an interrupt request aiming at a target computing cluster and a core, the interrupt request is interrupt of a sharing device, the root processor packages the initiated interrupt request to form an interrupt message, the interrupt message comprises physical IDs of the target computing cluster and the core, the routing destination of the interrupt message is a computing cluster control unit corresponding to the physical IDs of the target computing cluster and the core in the root processor, and the interrupt message is routed to the interrupt control unit of the root processor through the on-chip network.

Optionally, the detailed step of remapping the physical IDs of the compute cluster and the core that initiate the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in the manner (1.1) includes: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the root processor to the No. 0 to i/2-1 computing cluster control unit with logic IDs in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of No. 0 in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of No. 1 in the root processor, and so on, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of No. i/2-1 in the root processor, and the cores from 0 to n in two adjacent computing clusters of the root processor are respectively redirected to the core control units from 0 to n and the core control units from n +1 to 2n +1 in the same computing cluster control unit of the root processor.

Optionally, step 1) is preceded by a step of initiating an interrupt request by a non-root processor, and the step is one of the following three ways:

mode (2.1): a core in a computing cluster of a non-root processor initiates an interrupt request, the interrupt request is a private interrupt or an inter-machine interrupt, the non-root processor remaps a physical ID of the computing cluster and the core which initiate the interrupt request to a logic ID of a corresponding computing cluster control unit in the root processor, the logic ID is packaged to form an interrupt message, the routing destination of the interrupt message is the computing cluster control unit corresponding to the logic ID in the root processor, and the interrupt message is routed to the interrupt control unit of the root processor through a network-on-chip of the non-root processor, an inter-processor high-speed interconnection interface and the network-on-chip of the root processor;

mode (2.2): an IO device of a non-root processor initiates an interrupt request, the interrupt request of the non-root processor is shared device interrupt or device message interrupt, the initiated interrupt request is packaged to form an interrupt message, the interrupt message comprises physical IDs of a target computing cluster and a core, the routing destination of the interrupt message is a computing cluster control unit corresponding to the physical IDs of the target computing cluster and the core in the root processor, and the interrupt message is routed to an interrupt control unit of the root processor through an on-chip network of the non-root processor, an inter-processor high-speed interconnection interface and the on-chip network of the root processor;

mode (2.3): the storage device of the non-root processor initiates an interrupt request, the interrupt request of the non-root processor is a shared device interrupt, the initiated interrupt request is packaged to form an interrupt message, the interrupt message comprises physical IDs of a target computing cluster and a core, the routing destination of the interrupt message is a computing cluster control unit corresponding to the physical IDs of the target computing cluster and the core in the root processor, and the interrupt message is routed to the interrupt control unit of the root processor through a network on chip of the non-root processor, an inter-processor high-speed interconnection interface and the network on chip of the root processor.

Optionally, the detailed step of remapping the physical IDs of the compute cluster and the core that initiate the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in the manner (2.1) includes: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the non-root processor to a computing cluster control unit with the logical IDs of the No. 0 to i-1 computing cluster in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of the No. i/2 computing cluster in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of the No. i/2+1 computing cluster in the root processor, and repeating the steps, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of the No. i-1 computing cluster in the root processor, and respectively redirecting the No. 0 to the No. n cores in two adjacent computing clusters to the No. 0 to n core control units with the same number of the root processor and the No. n +1 to No. 2n +1 core control units.

The invention also provides a device for supporting single-root dual-processor interrupt communication, which comprises:

an inter-processor high-speed interconnect interface for enabling communication between a root processor and a non-root processor;

the network on chip is used for realizing data transmission among the network on chip connecting parts;

the system comprises a computing cluster unit, a network-on-chip and a network-on-chip, wherein the computing cluster unit comprises i computing clusters with the serial numbers of 0-i-1, each computing cluster comprises n +1 cores with the serial numbers of 0-n, a corresponding interruption packaging unpacking module is arranged between each computing cluster and the network-on-chip, and the interruption packaging unpacking module comprises an interruption message unpacking submodule, a computing cluster redirection submodule and an interruption message packing submodule;

the IO interruption unit comprises IO equipment and a first interruption message packaging module, wherein the IO equipment is connected with the on-chip network through the first interruption message packaging module;

the storage device interruption unit comprises a storage device and a second interruption message packaging module, and the storage device is connected with the network on chip through the second interruption message packaging module;

an interrupt control unit for executing the steps of the method of claim 1 or 2 for supporting single root dual processor interrupt communication as an interrupt response execution component in a root processor;

the inter-processor high-speed interconnection interface, the computing cluster unit, the IO interruption unit, the storage device interruption unit and the interruption control unit are respectively connected with the network on chip.

Optionally, the interrupt control unit includes:

the interrupt message unpacking unit is used for unpacking the interrupt message from the network on chip;

the interrupt message arbitration unit is used for arbitrating and outputting an interrupt interaction command message sent to the on-chip network;

the number of the computing cluster control units is i, and the computing cluster control units are used for making interrupt response according to the logic ID of the interrupt message;

the computing cluster interaction interrupt control unit is used for acquiring the relevant configuration of the interrupt request for the computing cluster control unit;

the calculation cluster control unit includes:

an interrupt message cache FIFO for caching the interrupt message of the interrupt message after unpacking and executing scheduling output;

the core control units are 2n +2 in number and used for generating interrupt interaction commands for the interrupt requests according to the related configuration;

a compute cluster control unit redirection module for remapping the logical IDs to physical IDs of cores and target compute clusters of the corresponding root processor or non-root processor;

and the interrupt message packing unit is used for packing the interrupt interaction command to generate an interrupt interaction command message and outputting the interrupt interaction command message to the interrupt message arbitration unit, and the destination of the interrupt interaction command message is the physical ID of the target computing cluster and core which are remapped to the corresponding root processor or non-root processor.

The invention also provides a single-root dual-processor device, which comprises a root processor and a non-root processor which have the same structure, and is characterized in that the root processor and the non-root processor both comprise the device supporting single-root dual-processor interrupt communication, and the root processor and the non-root processor are mutually connected through an inter-processor high-speed interconnection interface.

Compared with the prior art, the invention has the following advantages:

1. high performance. Because the invention supports single-root dual-processor interrupt communication, the tasks can be distributed to the computing clusters on different processors for execution by scheduling when the program runs, and the shared device interrupt and the device message interrupt can be distributed on different processors according to the idle of the cores in the computing clusters, thereby improving the performance of the processors.

2. The realization cost is low. The invention can be realized in the existing processor design only by configuring the number of the core control units in the computing cluster control unit in the interrupt control unit to be twice of the number of the cores in the computing cluster of the processor, simultaneously adding a computing cluster control unit redirection module in the interrupt control unit, adding a computing cluster redirection module in the computing cluster and adding a high-speed interconnection interface between processors in the processor, so the realization cost is low, the realization is simple, and the invention can be flexibly applied to the existing processor design.

3. The use is flexible, and the existing single processor interrupt path is not influenced. The method for supporting single-root dual-processor interrupt communication provided by the invention does not influence the existing interrupt path, namely when a dual-processor single-root mechanism is not required to be realized, software can configure the processors into root processors, and all interrupt requests and responses are processed in the respective root processors.

Drawings

FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a frame structure of an apparatus according to an embodiment of the present invention.

FIG. 3 is a flow chart illustrating a process of a root processor initiating an interrupt request and response according to an embodiment of the present invention.

FIG. 4 is a flow diagram illustrating a non-root processor initiating an interrupt request and response according to an embodiment of the present invention.

Illustration of the drawings: 1. an inter-processor high-speed interconnect interface; 2. a network on chip; 3. calculating a cluster unit; 31. a computing cluster; 32. the packing and unpacking module is interrupted; 4. an IO interruption unit; 41. IO devices; 42. a first interrupt message packing module; 5. a storage device interrupt unit; 51. a storage device; 52. a second interrupt message packing module; 6. an interrupt control unit; 61. an interrupt message unpacking module; 62. an interrupt message arbitration unit; 63. a computing cluster control unit; 631. interrupting message cache FIFO; 632. a core control unit; 633. a computing cluster control unit redirection module; 64. and calculating a cluster interaction interruption control unit.

Detailed Description

As shown in fig. 1, the implementation steps of the method for supporting single-root dual-processor interrupt communication in this embodiment include:

7) arbitrating the interrupt interaction command message;

The device for supporting single-root dual-processor interrupt communication in this embodiment needs to provide support for controlling an interrupt request during dual-processor interconnection for interrupt type interrupt control units such as core private interrupt, inter-machine interrupt, shared device interrupt, device message interrupt, and the like to implement single-root control, where a single root means that only an interrupt control unit of a root processor works and an interrupt control unit of a non-root processor does not work when dual processors are interconnected.

It should be noted that the root processor or the non-root processor may be specified as needed, one of the processors is specified as the root processor, and the other processor is specified as the non-root processor, and the root processor interrupt control unit needs to be able to distinguish the interrupt request of the root processor from the interrupt request of the non-root processor when processing the interrupt request. For the root processor, core private interrupt, inter-machine interrupt, shared device interrupt and device message interrupt all need to be converted into interrupt messages to be routed to the root processor interrupt control unit. For a non-root processor, a core private interrupt and an inter-machine interrupt request are converted into an interrupt message through a computing cluster interrupt packaging and unpacking module, and the interrupt message is routed to a root processor interrupt control unit through an inter-processor high-speed interconnection interface through a network on chip; the shared device interrupt and the device message interrupt request are converted into interrupt messages through the corresponding interrupt packaging module, and the interrupt messages are routed to the root processor interrupt control unit through the inter-processor high-speed interconnection interface through the network on chip. Aiming at a root processor interrupt control unit, distinguishing and realizing the control of a root processor interrupt request and a non-root processor interrupt request through different computing cluster control units; aiming at the root processor interrupt control unit, the interaction of the non-root processor computing cluster interrupt command needs to be packaged into an interrupt message, and then the interrupt message is routed to the non-root processor computing cluster through the root processor on-chip network, the high-speed interconnection interface between the root processor and the non-root processor, and the non-root processor on-chip network. Meanwhile, after the interrupt requests of the non-root processor computing cluster, the IO device and the storage device are packed into a network, routing to the root processor interrupt control unit needs to be finally realized, and when the root processor interrupt control unit realizes interaction with the non-root processor computing cluster interrupt commands, routing to the non-root processor computing cluster needs to be finally realized. Aiming at an interrupt request initiated by a non-root processor, when the interrupt message conversion is realized, the physical ID capable of carrying an interconnection interface module between the non-root processors is required to be taken as intermediate routing information, and then the physical ID of an interrupt control unit of the root processor is taken as a final routing destination. Aiming at the interaction of the interrupt command of the computing cluster of the non-root processor initiated by the root processor, the physical ID capable of carrying the interconnection interface module between the root processors is required to be taken as intermediate routing information when the interrupt message conversion is realized, and then the physical ID of the computing cluster of the non-root processor is taken as a final routing destination. All types of interrupts are packed into interrupt messages, and the interrupt messages are finally routed to a root processor interrupt control unit, wherein non-root processor interrupt messages need to be transmitted to the root processor network-on-chip through an inter-processor interconnection module and then routed to the root processor interrupt control unit, and the root processor interrupt messages are directly routed to the root processor interrupt control unit through the network-on-chip; the interrupt control unit needs to be able to distinguish whether the interrupt source is from the root processor or the non-root processor, and specifically, the interrupt control unit is implemented by a computing cluster control unit redirection module connected to each computing cluster control unit, that is, interrupt requests initiated by computing clusters of the root processor and the non-root processor need to be mapped to different computing cluster control units in the root processor interrupt control unit through the computing cluster redirection module; the interrupt message transmitted by the interrupt message packaging unit in the interrupt control unit needs to realize round training arbitration through the interrupt message arbitration unit so as to prevent a certain interrupt interactive command from being unresponsive all the time.

In this embodiment, the detailed steps of step 5) include:

In this embodiment, step 1) further includes, before initiating the interrupt request, a step of the root processor, where the step is one of the following three ways:

In this embodiment, the detailed step of remapping the physical IDs of the compute cluster and the core that initiate the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in the manner (1.1) includes: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the root processor to the No. 0 to i/2-1 computing cluster control unit with logic IDs in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of No. 0 in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of No. 1 in the root processor, and so on, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of No. i/2-1 in the root processor, and the cores from 0 to n in two adjacent computing clusters of the root processor are respectively redirected to the core control units from 0 to n and the core control units from n +1 to 2n +1 in the same computing cluster control unit of the root processor.

In this embodiment, step 1) further includes, before initiating the interrupt request, a step of initiating an interrupt request by a non-root processor, where the step is one of the following three ways:

In this embodiment, the detailed step of remapping the physical IDs of the compute cluster and the core that initiate the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in the manner (2.1) includes: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the non-root processor to a computing cluster control unit with the logical IDs of the No. 0 to i-1 computing cluster in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of the No. i/2 computing cluster in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of the No. i/2+1 computing cluster in the root processor, and repeating the steps, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of the No. i-1 computing cluster in the root processor, and respectively redirecting the No. 0 to the No. n cores in two adjacent computing clusters to the No. 0 to n core control units with the same number of the root processor and the No. n +1 to No. 2n +1 core control units.

As shown in fig. 2, the apparatus for supporting single-root dual-processor interrupt communication in this embodiment includes:

an inter-processor high-speed interconnection interface 1 for realizing communication between a root processor and a non-root processor;

the network on chip 2 is used for realizing data transmission among network on chip connecting parts;

the computing cluster unit 3 includes i computing clusters 31 (respectively represented as 0 computing cluster-i-1 computing cluster in fig. 2, the number in the front represents the number), each computing cluster 31 includes n +1 cores (respectively represented as 0 core-n core in fig. 2, the number in the front represents the number) with the number of 0-n, a corresponding interrupt packing and unpacking module 32 is provided between each computing cluster 31 and the on-chip network 2 (for example, the 0 computing cluster is correspondingly provided with a 0 interrupt packing and unpacking module, the 1 computing cluster is correspondingly provided with a1 interrupt packing and unpacking module, and so on), and the interrupt packing and unpacking module 32 includes an interrupt message unpacking submodule, a computing cluster redirection submodule, and an interrupt message packing submodule;

the IO interrupt unit 4 includes an IO device 41 and a first interrupt packet packing module 42, and the IO device 41 is connected to the network on chip 2 through the first interrupt packet packing module 42;

the storage device interrupt unit 5 includes a storage device 51 and a second interrupt packet packing module 52, and the storage device 51 is connected to the network on chip through the second interrupt packet packing module 52;

an interrupt control unit 6, configured to execute, as an interrupt response execution component in the root processor, the steps of the aforementioned method for supporting single-root dual-processor interrupt communication in this embodiment;

the inter-processor high-speed interconnection interface 1, the computing cluster unit 3, the IO interruption unit 4, the storage device interruption unit 5 and the interruption control unit 6 are respectively connected with the network-on-chip 2, and interface support is provided for the routing of the non-root processor interruption request.

In this embodiment, the interrupt control unit 6 includes:

an interrupt packet unpacking unit 61, configured to unpack an interrupt packet from the network on chip 2;

an interrupt message arbitration unit 62, configured to arbitrate and output an interrupt interaction command message sent to the network on chip 2; in this embodiment, the interrupt packet arbitration unit 62 performs arbitration by using a polling policy, so as to prevent a certain interrupt interaction command from being unresponsive.

A number of i computing cluster control units 63 (respectively indicated as 0 computing cluster control unit-i-1 computing cluster control unit in fig. 2, the number in the front indicates a number) for making an interrupt response according to the logic ID of the interrupt packet;

a computing cluster interaction interrupt control unit 64, configured to obtain a relevant configuration of the interrupt request for the computing cluster control unit 63;

the calculation cluster control unit 63 includes:

an interrupt message buffer FIFO 631, configured to buffer the interrupt message of the interrupt message after unpacking and perform scheduling output;

the core control units 632, the number of which is 2n +2 (respectively shown as 0 core control unit-2 n +1 core control unit in fig. 2, the number in the front indicates a number), are used for generating an interrupt interaction command for the interrupt request according to the relevant configuration;

a compute cluster control unit redirect module 633 for remapping the logical IDs to the physical IDs of the cores and the target compute clusters of the corresponding root processor or non-root processors;

the interrupt packet packing unit 634 is configured to pack the interrupt interaction command to generate an interrupt interaction command packet and output the interrupt interaction command packet to the interrupt packet arbitration unit 62, where the destination of the interrupt interaction command packet is the physical ID of the target compute cluster and core remapped to the corresponding root processor or non-root processor.

As shown in fig. 2, this embodiment further provides a single-root dual-processor apparatus, which includes a root processor and a non-root processor with the same structure, where the root processor and the non-root processor both include the foregoing apparatus supporting single-root dual-processor interrupt communication in this embodiment, and the root processor and the non-root processor are connected to each other through an inter-processor high-speed interconnect interface 1.

As shown in fig. 3, the steps of initiating the interrupt request and response flow by the root processor are as follows:

A1. a core in a certain compute cluster 31 of the root processor initiates private interrupts and inter-machine interrupts;

A2. the computation cluster redirection submodule in the interrupt packing and unpacking module 32 corresponding to the computation cluster 31 implements remapping of the computation cluster and the core physical ID for the interrupt request initiated in step a1, specifically: redirecting the number 0 to i-1 computing clusters 31 in the root processor to the number 0 to i/2-1 computing cluster control unit 12 in the root processor interrupt control unit, wherein the number 0 and 1 computing clusters 31 are redirected to the number 0 computing cluster control unit 12 of the root processor, the number 2 and 3 computing clusters 31 are redirected to the number 1 computing cluster control unit 12 of the root processor, and so on, the number i-2 and the number i-1 computing clusters 31 are redirected to the number i/2-1 computing cluster control unit 12 of the root processor, and it is worth noting that the numbers 0 to n in two adjacent computing clusters 31 are respectively redirected to the numbers 0 to n and the numbers n +1 to 2n +1 core control units in the same computing cluster control unit 12;

A3. the interrupt message packing submodule packs the interrupt request remapped in the step A2 to form an interrupt message, wherein the routing destination is the remapped computing cluster control unit 12 in the root processor interrupt control unit;

the above-mentioned a 1-A3 are the first way for a root processor to initiate an interrupt request.

A4. The root processor IO device 41 initiates a shared device interrupt and a device message interrupt;

A5. the first interrupt packet packing module 42 packs the interrupt request initiated in step a4 to form an interrupt packet, where the routing destination is the computing cluster control unit 12 of the interrupt request destination in the root processor interrupt control unit;

the above-mentioned a 4-a 5 are the second way for the root processor to initiate an interrupt request.

A6. The root processor storage device 51 initiates a shared device interrupt;

A7. the second interrupt packet packing module 52 packs the interrupt request initiated in step a6 to form an interrupt packet, where the routing destination is the computing cluster control unit 12 of the interrupt request destination in the root processor interrupt control unit;

the above-mentioned a 6-a 7 are the third way for the root processor to initiate an interrupt request.

A8. The interrupt message formed in the steps A3, A5 and A7 is routed to the root processor interrupt control unit through the network on chip 2;

A9. an interrupt message unpacking unit 61 of the root processor interrupt control unit unpacks the received interrupt message;

A10. buffering the unpacked interrupt message to an interrupt message buffer FIFO 631 corresponding to the interrupt request destination computing cluster control unit 12;

A11. if the interrupt message buffer FIFO 631 is not empty, the interrupt request is transmitted to the corresponding computing cluster control unit 12;

A12. after receiving the interrupt request, the computing cluster control unit 12 further transmits the interrupt request to the computing cluster interaction interrupt control unit 64 to implement acquisition of the relevant configuration of the interrupt request;

A13. the computation cluster interaction interrupt control unit 64 feeds back the interrupt request configuration to the computation cluster control unit 12, and the computation cluster control unit 12 performs an interrupt response, that is, feeds back an interrupt interaction command;

A14. the interrupt interaction command fed back by the computing cluster control unit 12 needs to be redirected by the computing cluster control unit redirection module 633 to redirect the computing cluster and core physical IDs, specifically: the number 0 to i/2-1 computing cluster control unit 12 redirects to the number 0 to i computing clusters 31 of the root processor, wherein the number 0 computing cluster control unit 12 redirects to the number 0 to 1 computing clusters 31 of the root processor, the number 1 computing cluster control unit 12 redirects to the number 2 to 3 computing clusters 31 of the root processor, and so on, the number i/2-1 is redirected to the number i-2 to i-1 computing clusters 31 of the root processor, and meanwhile, the numbers 0 to n and n +1 to 2n +1 in the number 0 to 2n +1 core control unit in the computing cluster control unit 12 are respectively redirected to the numbers 0 to n in the two adjacent computing clusters 31;

A15. the redirected interrupt interaction command is packaged by the interrupt packet packaging unit 634 to form an interrupt packet, wherein the routing destination is the computing cluster 31 of the root processor interrupt request destination;

A16. an interrupt message arbitration unit 62 in the interrupt control unit arbitrates the received interrupt interactive command message to prevent a situation that a certain interrupt interactive command message is fed back all the time and does not return to the interrupt request destination computing cluster 31;

A17. the interrupt message arbitrated in the step A16 is routed to an interrupt packaging and unpacking submodule of a computing cluster corresponding to a root processor interrupt request destination computing cluster through the network on chip 2;

A18. the interrupt packaging and unpacking submodule unpacks the received interrupt interaction command message;

A19. the unpacked interrupt interaction command is transmitted to the interrupt request destination computing cluster 31.

As shown in fig. 4, the steps of initiating the interrupt request and response flow by the non-root processor in this embodiment are as follows:

B1. a core in the non-root processor computing cluster 31 initiates private interrupts and inter-machine interrupts;

B2. the computation cluster redirection module in the interrupt packing and unpacking module 32 of the computation cluster 31 implements remapping of the computation cluster and the core physical ID for the interrupt request initiated in step B1, specifically: redirecting the No. 0 to i-1 computing cluster 31 in the non-root processor to the No. i/2 to i-1 computing cluster control unit 63 in the root processor interrupt control unit, wherein the No. 0 and No. 1 computing cluster 31 are redirected to the No. i/2 computing cluster control unit 63 of the root processor, the No. 2 and No. 3 computing cluster 31 are redirected to the No. i/2+1 computing cluster control unit 63 of the root processor, and so on, the No. i-2 and No. i-1 computing cluster 31 are redirected to the No. i-1 computing cluster control unit 63 of the root processor, and it is worth noting that the No. 0 to n cores in two adjacent computing clusters 31 are respectively redirected to the No. 0 to n and the No. n +1 to No. 2n +1 core control units in the same computing cluster control unit 63;

B3. the interrupt message packing submodule packs the interrupt request remapped in the step B2 to form an interrupt message, wherein the destination in the middle of the route is the high-speed interconnection interface 2 between the non-root processors, and the final destination is the calculation cluster control unit 63 remapped in the interrupt control unit of the root processor;

the above-mentioned B1-B3 are the first way for a non-root processor to initiate an interrupt request.

B4. The IO device 41 of the non-root processor initiates a shared device interrupt and a device message interrupt;

B5. the first interrupt packet packing unit 42 packs the interrupt request initiated in step B4 to form an interrupt packet, where the intermediate destination of the route is the inter-processor high-speed interconnect interface 1 of the non-root processor, and the final destination is the remapped compute cluster control unit 63 in the root processor interrupt control unit;

the above-mentioned B4-B5 are the second way for a non-root processor to initiate an interrupt request.

B6. The storage device 51 of the non-root processor initiates a shared device interrupt;

B7. the second interrupt packet packing unit 52 packs the interrupt request initiated in step B6 to form an interrupt packet, where the destination in the middle of the route is the non-root inter-processor high-speed interconnect interface 1, and the final destination is the remapped compute cluster control unit 63 in the root processor interrupt control unit;

the above-mentioned B6-B7 are the third way for a non-root processor to initiate an interrupt request.

B8. B3, B5 and B7 form interrupt message through non-root processor on-chip network 2 route to non-root processor inter-processor high speed interconnection interface 1;

B9. the non-root processor network-on-chip 2 further transmits the interrupt message to an inter-processor high-speed interconnection interface (17) of the root processor;

B10. an inter-processor high-speed interconnection interface 1 of a root processor transmits a non-root processor interrupt message transmitted by a network-on-chip 2 to the network-on-chip 2 of the root processor;

B11. the network on chip 2 of the root processor transmits the non-root processor interrupt message to the root processor interrupt control unit;

B12. an interrupt message unpacking unit 61 in the root processor interrupt control unit 6 unpacks the received non-root processor interrupt message;

B13. the unpacked non-root processor interrupt message is cached in an interrupt message cache FIFO 631 corresponding to the interrupt request destination computing cluster control unit 63;

B14. if the interrupt message buffer FIFO 631 is not empty, transmitting the non-root processor interrupt request to the compute cluster control unit 63 corresponding thereto;

B15. after receiving the non-root processor interrupt request, the computing cluster control unit 63 further transmits the non-root processor interrupt request to the computing cluster interaction interrupt control unit 64 to realize the acquisition of the relevant configuration of the non-root processor interrupt request;

B16. the computing cluster interaction interrupt control unit 64 feeds back the non-root processor interrupt request configuration to the computing cluster control unit 63, and the computing cluster control unit 63 further performs interrupt response, that is, feeds back an interrupt interaction command;

B17. the non-root processor interrupt interaction command fed back by the compute cluster control unit 63 needs to be redirected by the compute cluster control unit redirection module 633 to implement redirection of compute cluster and core physical IDs, specifically: the i/2 to i-1 computing cluster control unit 63 redirects to the non-root processors 0 to i computing clusters 31, wherein the i/2 computing cluster control unit 63 redirects to the non-root processors 0 to 1 computing clusters 31, the i/2+1 computing cluster control unit 63 redirects to the non-root processors 2 to 3 computing clusters 31, and so on, the i-1 computing cluster control unit redirects to the non-root processors i-2 to i-1 computing clusters 31, and meanwhile, the 0 to n numbers and the n +1 to 2n +1 numbers in the 0 to 2n +1 core control units in the computing cluster control unit 63 are respectively redirected to the 0 to n numbers of cores in the two adjacent computing clusters 31;

B18. the redirected non-root processor interrupt interaction command is packed by the interrupt packet packing unit 634 to form a non-root processor interrupt interaction packet, wherein the intermediate destination of the route is the inter-processor high-speed interconnection interface 1 of the root processor, and the final destination is the redirected calculation cluster 31 of the non-root processor;

B19. the interrupt message arbitration unit 62 in the root processor interrupt control unit 6 arbitrates the received non-root processor interrupt interactive command message to prevent a situation that a certain non-root processor interrupt interactive command message is fed back to the computing cluster 31 which does not return the interrupt request;

B20. b19, the arbitrated message of non-root processor interrupt interaction command is routed to the inter-processor high-speed interconnection interface 1 of the root processor through the network on chip 2;

B21. the inter-processor high-speed interconnection interface 1 of the root processor further transmits the non-root processor interrupt interaction command message to the inter-processor high-speed interconnection interface 1 of the non-root processor;

B22. the network-on-chip 2 of the non-root processor transmits the non-root processor interrupt interactive command message transmitted by the inter-processor high-speed interconnection interface 1 to the network-on-chip 2 of the non-root processor;

B23. the network-on-chip 2 of the non-root processor transmits the non-root processor interrupt interaction command message to an interrupt packaging and unpacking module 32 corresponding to the non-root processor interrupt request destination computing cluster 31;

B24. an interrupt message unpacking submodule in the interrupt packing and unpacking module 32 unpacks the received non-root processor interrupt interaction command message;

B25. the non-root processor interrupt interactive command unpacked by the interrupt message unpacking submodule is transmitted to the interrupt request destination computing cluster 31.

In summary, the technical route of the present embodiment supporting the single dual-processor interrupt communication can be divided into four major parts: 1. the interrupt control unit increases the number of the core control units in each computing cluster control unit to be twice of the number of the cores in the computing cluster on the premise of not increasing the number of the computing cluster control units so as to realize redirection of a single-root dual-processor interrupt request, specifically, a modified single computing cluster control unit can realize control over two computing clusters, and meanwhile, the computing cluster control units with low half part numbers and high half part numbers in the modified root processor interrupt control unit respectively realize interrupt control over a root processor and a non-root processor. 2. After initiating an interrupt request (including core private interrupt and inter-machine interrupt), a root processor computing cluster first needs to be redirected to a computing cluster control unit with a lower part of a serial number in an interrupt control unit of the root processor through a computing cluster redirection module, and then forms an interrupt message on-chip network through an interrupt message packaging unit, wherein the routing destination of the interrupt message is the root processor interrupt control unit. Meanwhile, shared device interrupt and IO device message interrupt initiated by IO and storage devices also form an interrupt message network-on-chip through an interrupt message packaging unit, and the routing destination of the interrupt message network-on-chip is also a root processor interrupt control unit. 3. After initiating an interrupt request (including core private interrupt and inter-processor interrupt), a non-root processor computing cluster firstly needs to be redirected to a computing cluster control unit with a higher number half in an interrupt control unit of a root processor through a computing cluster redirection module, then forms an inter-non-root processor on-chip network on an interrupt message through an interrupt message packaging unit, then routes the non-root processor on-chip network to an inter-processor high-speed interconnection interface of a non-root processor, then transmits the non-root processor on-chip network to the root processor on-chip network through the inter-root processor high-speed interconnection interface, and then routes the non-root processor on-chip network to the interrupt control unit of the root processor. Meanwhile, shared device interrupt and IO device message interrupt initiated by IO and storage devices also form an on-chip network of non-root processors on an interrupt message through an interrupt message packaging unit, the middle purpose of the routing is also a high-speed interconnection interface between the non-root processors, and the on-chip network of the root processors is transmitted through the high-speed interconnection interface between the root processors and then is routed to an interrupt control unit of the root processors. 4. The root processor interrupt control unit receives the interrupt request, and distinguishes whether the interrupt request source is a root processor or a non-root processor through the computing cluster control unit number, however, the process of implementing interrupt management in the interrupt control unit needs to perform interrupt command interaction with the computing cluster of the interrupt request destination (which can be located in the root processor and the non-root processor), so the root processor computing cluster control unit first needs to implement remapping of the computing cluster of the interrupt request destination through the computing cluster control unit redirection module corresponding to the root processor computing cluster control unit, specifically: the numbered low half part computing cluster control unit redirects to the computing cluster of the root processor, and the numbered high half part computing cluster control unit redirects to the computing cluster of the non-root processor. Secondly, the redirected interrupt interaction command needs to form an interrupt message network-on-chip through an interrupt message packaging unit, wherein the routing destination of the interrupt interaction command message redirected to the root processor is a computing cluster of the root processor, and the routing of the interrupt interaction command message redirected to the non-root processor needs to be routed to the computing cluster of the non-root processor through an intermediate destination inter-processor high-speed interconnection interface.

The method aims at a computing cluster redirection module in a processor computing cluster and a computing cluster control unit redirection module in an interrupt control unit, and has the functions of realizing redirection with a computing cluster control unit in a root processor interrupt control unit when an interrupt request is initiated and redirection with a computing cluster of a root processor and a computing cluster of a non-root processor when an interrupt command is interacted. Meanwhile, the interrupt message packing unit in the root processor computing cluster interrupt packing and unpacking module configures the interrupt message routing destination to be the interrupt control unit, and the interrupt message packing unit in the non-root processor computing cluster interrupt packing and unpacking module configures the interrupt message routing intermediate destination to be the non-root inter-processor high-speed interconnection interface and the final destination to be the root processor interrupt control unit. In addition, the interrupt packet packing unit in the root processor interrupt control unit configures different routing destinations according to the number of the computing cluster control unit, wherein the interrupt packet packing unit corresponding to the lower half computing cluster control unit configures the formed interrupt packet routing destination as the root processor computing cluster, and the interrupt packet packing unit corresponding to the higher half computing cluster control unit configures the formed interrupt packet routing information to be added with an intermediate routing destination as the inter-root processor high-speed interconnection interface and the final destination as the non-root processor computing cluster.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims

1. A method for supporting single root dual processor interrupt communication, the method comprising the steps of:

7) arbitrating the interrupt interaction command message;

2. The method of claim 1, wherein the detailed steps of step 5) include:

3. The method of claim 1, further comprising the step of initiating an interrupt request by the root processor before step 1), and wherein the step is one of the following three ways:

4. A method for supporting single root dual processor interrupt communication according to claim 3, wherein the detailed step of remapping the physical IDs of the compute cluster and core initiating the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in manner (1.1) comprises: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the root processor to the No. 0 to i/2-1 computing cluster control unit with logic IDs in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of No. 0 in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of No. 1 in the root processor, and so on, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of No. i/2-1 in the root processor, and the cores from 0 to n in two adjacent computing clusters of the root processor are respectively redirected to the core control units from 0 to n and the core control units from n +1 to 2n +1 in the same computing cluster control unit of the root processor.

5. The method of claim 1, further comprising the step of initiating an interrupt request by a non-root processor before step 1), and wherein the step is one of the following three ways:

6. The method of claim 5, wherein the detailed step of remapping the physical IDs of the compute cluster and core that initiated the interrupt request to the logical ID of the corresponding compute cluster control unit in the root processor in manner (2.1) comprises: redirecting the No. 0 to i-1 computing clusters initiating the interrupt request in the non-root processor to a computing cluster control unit with the logical IDs of the No. 0 to i-1 computing cluster in the interrupt control unit of the root processor, redirecting the No. 0 and No. 1 computing clusters to a computing cluster control unit with the logical ID of the No. i/2 computing cluster in the root processor, redirecting the No. 2 and No. 3 computing clusters to a computing cluster control unit with the logical ID of the No. i/2+1 computing cluster in the root processor, and repeating the steps, redirecting the No. i-2 and No. i-1 computing clusters to a computing cluster control unit with the logical ID of the No. i-1 computing cluster in the root processor, and respectively redirecting the No. 0 to the No. n cores in two adjacent computing clusters to the No. 0 to n core control units with the same number of the root processor and the No. n +1 to No. 2n +1 core control units.

7. An apparatus for supporting single root dual processor interrupt communication, comprising:

an inter-processor high-speed interconnect interface (1) for enabling communication between a root processor and a non-root processor;

the network on chip (2) is used for realizing data transmission among network on chip connecting parts;

the computing cluster unit (3) comprises i computing clusters (31) with the serial numbers of 0-i-1, each computing cluster (31) comprises n +1 cores with the serial numbers of 0-n, a corresponding interrupt packaging and unpacking module (32) is arranged between each computing cluster (31) and the network-on-chip (2), and the interrupt packaging and unpacking module (32) comprises an interrupt message unpacking submodule, a computing cluster redirection submodule and an interrupt message packing submodule;

the IO interruption unit (4) comprises IO equipment (41) and a first interruption message packaging module (42), wherein the IO equipment (41) is connected with the network on chip (2) through the first interruption message packaging module (42);

the storage device interrupt unit (5) comprises a storage device (51) and a second interrupt message packaging module (52), and the storage device (51) is connected with the network on chip through the second interrupt message packaging module (52);

an interrupt control unit (6) for executing the steps of the method of supporting single root dual processor interrupt communication of claim 1 or 2 as an interrupt response execution means in the root processor;

the inter-processor high-speed interconnection interface (1), the computing cluster unit (3), the IO interruption unit (4), the storage device interruption unit (5) and the interruption control unit (6) are respectively connected with the network on chip (2).

8. An apparatus supporting single root dual processor interrupt communication according to claim 7, wherein the interrupt control unit (6) comprises:

an interrupt message unpacking unit (61) for unpacking the interrupt message from the network-on-chip (2);

an interrupt message arbitration unit (62) for arbitrating output of an interrupt interaction command message sent to the network-on-chip (2);

the number of the computing cluster control units (63) is i, and the computing cluster control units are used for making interrupt response according to the logic ID of the interrupt message;

a computing cluster interaction interrupt control unit (64) for acquiring the relevant configuration of the interrupt request for the computing cluster control unit (63);

the calculation cluster control unit (63) includes:

an interrupt message buffer FIFO (631) for buffering the interrupt message of the interrupt message after unpacking and executing scheduling output;

the core control units (632) are 2n +2 in number and are used for generating interrupt interaction commands for the interrupt requests according to the related configuration;

a compute cluster control unit redirection module (633) to remap the logical IDs to physical IDs of cores and target compute clusters of the corresponding root processor or non-root processors;

and the interrupt message packing unit (634) is used for packing the interrupt interaction command to generate an interrupt interaction command message and outputting the interrupt interaction command message to the interrupt message arbitration unit (62), and the destination of the interrupt interaction command message is the physical ID of the target computing cluster and core which are remapped to the corresponding root processor or non-root processor.

9. A single root dual processor apparatus comprising root and non-root processors of identical structure, wherein the root and non-root processors each comprise the apparatus for supporting single root dual processor interrupt communication according to claim 7 or 8, and the root and non-root processors are interconnected via an inter-processor high speed interconnect interface (1).